commit b081d67f3e96896ea0ca7426a18c5fe153419ee0
author Patrik Gustavsson <patrik.gustavsson@arm.com> Wed Aug 25 13:49:25 2021 +0200
committer Patrik Gustavsson <patrik.gustavsson@arm.com> Fri Sep 03 14:37:43 2021 +0200
tree a62a36256836b9bebcf318fe71793ad800099267
parent df99510f04aef99d1b8e9be9bfcde8fc1738b65f

TOSA: Added support for ADD, SUB and MUL

Added support for ADD, SUB and MUL

Signed-off-by: Patrik Gustavsson <patrik.gustavsson@arm.com>
Change-Id: I52acdc126b16e2cf4096bcf7a77023ea7d204998

ethosu/vela/register_command_stream_generator.py

diff --git a/ethosu/vela/register_command_stream_generator.py b/ethosu/vela/register_command_stream_generator.py
index 6ee0005..d74f4d2 100644
--- a/ethosu/vela/register_command_stream_generator.py
+++ b/ethosu/vela/register_command_stream_generator.py
@@ -729,7 +729,9 @@
             output_scale = 1 / 0x3000
 
         if npu_op.sub_op_type == NpuElementWiseOp.MUL:
-            if None in (input_scale, input2_scale, output_scale):
+            if npu_op.rescale:
+                ofm_scale, shift = npu_op.rescale
+            elif None in (input_scale, input2_scale, output_scale):
                 ofm_scale = 1
                 shift = 0
             else: