commit b81e1bb92be8ea5b29625cf2f361e9160286b16a
author Fredrik Svedberg <fredrik.svedberg@arm.com> Tue Oct 11 21:50:51 2022 +0200
committer Fredrik Svedberg <fredrik.svedberg@arm.com> Wed Oct 12 11:22:17 2022 +0000
tree 0963851b6d449224f67cce10ba510830db7b4172
parent 3e3faa90def7c2c4aaaf71543726c881f05f53b5

MLBEDSW-6971 Fix output diff when cascading elementwise operators

Fixed output diff when cascading elementwise operators with
reversed operand order.

Signed-off-by: Fredrik Svedberg <fredrik.svedberg@arm.com>
Change-Id: Iac2e28cfb53037b929459af213f4fa7715b3e6de

ethosu/vela/high_level_command_stream_generator.py

diff --git a/ethosu/vela/high_level_command_stream_generator.py b/ethosu/vela/high_level_command_stream_generator.py
index 7e13b62..e71fb6e 100644
--- a/ethosu/vela/high_level_command_stream_generator.py
+++ b/ethosu/vela/high_level_command_stream_generator.py
@@ -74,6 +74,8 @@
         _,
         _,
     ) = parent_op.get_ifm_ifm2_weights_biases_ofm()
+    if sched_op.reversed_operands:
+        ifm2_tensor, ifm_tensor = ifm_tensor, ifm2_tensor
     ifm = sched_op.ifm
     ifm2 = sched_op.ifm2
     ofm_shape = sched_op.ofm.shape
@@ -236,4 +238,5 @@
                     ifm2_box=ifm2_box,
                     pad_top=pad_top,
                     pad_bottom=pad_bottom,
+                    reversed_operands=sched_op.reversed_operands,
                 )