MLBEDSW-3465: Add memory settings into sys config
Signed-off-by: Diqing Zhong <diqing.zhong@arm.com>
Change-Id: I4a5c53d0c5957595fc639b174b2b227ea043d409
diff --git a/vela.ini b/vela.ini
index 94ab4fa..47fa669 100644
--- a/vela.ini
+++ b/vela.ini
@@ -26,7 +26,13 @@
axi0_port=Sram
axi1_port=OffChipFlash
Sram_clock_scale=1.0
+Sram_burst_length=32
+Sram_read_latency=32
+Sram_write_latency=32
OffChipFlash_clock_scale=0.0625
+OffChipFlash_burst_length=128
+OffChipFlash_read_latency=64
+OffChipFlash_write_latency=64
; Ethos-U55 High-End Embedded: SRAM (4 GB/s) and Flash (0.5 GB/s)
[System_Config.Ethos_U55_High_End_Embedded]
@@ -34,7 +40,13 @@
axi0_port=Sram
axi1_port=OffChipFlash
Sram_clock_scale=1.0
+Sram_burst_length=32
+Sram_read_latency=32
+Sram_write_latency=32
OffChipFlash_clock_scale=0.125
+OffChipFlash_burst_length=128
+OffChipFlash_read_latency=64
+OffChipFlash_write_latency=64
; Ethos-U65 Embedded: SRAM (8 GB/s) and Flash (0.5 GB/s)
[System_Config.Ethos_U65_Embedded]
@@ -42,7 +54,13 @@
axi0_port=Sram
axi1_port=OffChipFlash
Sram_clock_scale=1.0
+Sram_burst_length=32
+Sram_read_latency=32
+Sram_write_latency=32
OffChipFlash_clock_scale=0.0625
+OffChipFlash_burst_length=128
+OffChipFlash_read_latency=64
+OffChipFlash_write_latency=64
; Ethos-U65 Mid-End: SRAM (8 GB/s) and DRAM (3.75 GB/s)
[System_Config.Ethos_U65_Mid_End]
@@ -50,7 +68,13 @@
axi0_port=Sram
axi1_port=Dram
Sram_clock_scale=1.0
+Sram_burst_length=32
+Sram_read_latency=32
+Sram_write_latency=32
Dram_clock_scale=0.46875
+Dram_burst_length=128
+Dram_read_latency=500
+Dram_write_latency=250
; Ethos-U65 High-End: SRAM (16 GB/s) and DRAM (3.75 GB/s)
[System_Config.Ethos_U65_High_End]
@@ -58,7 +82,13 @@
axi0_port=Sram
axi1_port=Dram
Sram_clock_scale=1.0
+Sram_burst_length=32
+Sram_read_latency=32
+Sram_write_latency=32
Dram_clock_scale=0.234375
+Dram_burst_length=128
+Dram_read_latency=500
+Dram_write_latency=250
; Ethos-U65 Client-Server: SRAM (16 GB/s) and DRAM (12 GB/s)
[System_Config.Ethos_U65_Client_Server]
@@ -66,7 +96,13 @@
axi0_port=Sram
axi1_port=Dram
Sram_clock_scale=1.0
+Sram_burst_length=32
+Sram_read_latency=32
+Sram_write_latency=32
Dram_clock_scale=0.75
+Dram_burst_length=128
+Dram_read_latency=500
+Dram_write_latency=250
; -----------------------------------------------------------------------------
; Memory Mode
@@ -96,4 +132,4 @@
; The non-SRAM memory is assumed to be read-writeable
[Memory_Mode.Dedicated_Sram_512KB]
inherit=Memory_Mode.Dedicated_Sram
-cache_sram_size=524288
\ No newline at end of file
+cache_sram_size=524288