commit fed918bfb26dc330a5f066ea5947bc5eb2db4651
author Diqing Zhong <diqing.zhong@arm.com> Mon Apr 27 10:27:34 2020 +0200
committer Tim Hall <tim.hall@arm.com> Wed May 13 15:56:19 2020 +0100
tree 9200ba8ed1d88789aa74223adb12bb2930c9da2a
parent b7311708b81e7022105d335c5e67efcd8f155610

Update to HI 0.169

Change-Id: I897bea10ae744162fd285838ee2b2c018695a278
(cherry picked from commit d5ac9b55faa899ac686433e79900cadd321b71bf)
Signed-off-by: Diqing Zhong <diqing.zhong@arm.com>

ethosu/vela/register_command_stream_generator.py

diff --git a/ethosu/vela/register_command_stream_generator.py b/ethosu/vela/register_command_stream_generator.py
index 5563b96..faae2cf 100644
--- a/ethosu/vela/register_command_stream_generator.py
+++ b/ethosu/vela/register_command_stream_generator.py
@@ -861,14 +861,14 @@
 
             if ifm_dtype.size_in_bits() == 8:
                 if ifm_dtype.type & BaseType.Signed:
-                    prec = ifm_precision.W8_S8
+                    prec = ifm_precision.S8
                 else:
-                    prec = ifm_precision.W8_U8
+                    prec = ifm_precision.U8
             elif ifm_dtype.size_in_bits() == 16:
                 if ifm_dtype.type & BaseType.Signed:
-                    prec = ifm_precision.W8_S16
+                    prec = ifm_precision.S16
                 else:
-                    prec = ifm_precision.W8_U16
+                    prec = ifm_precision.U16
 
             ifm_prec = prec.value
             ifm2_prec = ifm_prec