| Tim Hall | 1bd531d | 2020-11-01 20:59:36 +0000 | [diff] [blame^] | 1 | ; Copyright (C) 2020 Arm Limited or its affiliates. All rights reserved. |
| 2 | ; |
| 3 | ; SPDX-License-Identifier: Apache-2.0 |
| 4 | ; |
| 5 | ; Licensed under the Apache License, Version 2.0 (the License); you may |
| 6 | ; not use this file except in compliance with the License. |
| 7 | ; You may obtain a copy of the License at |
| 8 | ; |
| 9 | ; www.apache.org/licenses/LICENSE-2.0 |
| 10 | ; |
| 11 | ; Unless required by applicable law or agreed to in writing, software |
| 12 | ; distributed under the License is distributed on an AS IS BASIS, WITHOUT |
| 13 | ; WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 14 | ; See the License for the specific language governing permissions and |
| 15 | ; limitations under the License. |
| 16 | |
| 17 | ; ----------------------------------------------------------------------------- |
| 18 | ; Vela configuration file |
| 19 | |
| 20 | ; ----------------------------------------------------------------------------- |
| 21 | ; System Configuration |
| 22 | |
| 23 | ; Ethos-U55 Deep Embedded: SRAM (1.6 GB/s) and Flash (0.1 GB/s) |
| 24 | [System_Config.Ethos_U55_Deep_Embedded] |
| 25 | core_clock=200e6 |
| 26 | axi0_port=Sram |
| 27 | axi1_port=OffChipFlash |
| 28 | Sram_clock_scale=1.0 |
| 29 | OffChipFlash_clock_scale=0.0625 |
| 30 | |
| 31 | ; Ethos-U55 High-End Embedded: SRAM (4 GB/s) and Flash (0.5 GB/s) |
| 32 | [System_Config.Ethos_U55_High_End_Embedded] |
| 33 | core_clock=500e6 |
| 34 | axi0_port=Sram |
| 35 | axi1_port=OffChipFlash |
| 36 | Sram_clock_scale=1.0 |
| 37 | OffChipFlash_clock_scale=0.125 |
| 38 | |
| 39 | ; Ethos-U65 Embedded: SRAM (8 GB/s) and Flash (0.5 GB/s) |
| 40 | [System_Config.Ethos_U65_Embedded] |
| 41 | core_clock=500e6 |
| 42 | axi0_port=Sram |
| 43 | axi1_port=OffChipFlash |
| 44 | Sram_clock_scale=1.0 |
| 45 | OffChipFlash_clock_scale=0.0625 |
| 46 | |
| 47 | ; Ethos-U65 Mid-End: SRAM (8 GB/s) and DRAM (3.75 GB/s) |
| 48 | [System_Config.Ethos_U65_Mid_End] |
| 49 | core_clock=500e6 |
| 50 | axi0_port=Sram |
| 51 | axi1_port=Dram |
| 52 | Sram_clock_scale=1.0 |
| 53 | Dram_clock_scale=0.46875 |
| 54 | |
| 55 | ; Ethos-U65 High-End: SRAM (16 GB/s) and DRAM (3.75 GB/s) |
| 56 | [System_Config.Ethos_U65_High_End] |
| 57 | core_clock=1e9 |
| 58 | axi0_port=Sram |
| 59 | axi1_port=Dram |
| 60 | Sram_clock_scale=1.0 |
| 61 | Dram_clock_scale=0.234375 |
| 62 | |
| 63 | ; Ethos-U65 Client-Server: SRAM (16 GB/s) and DRAM (12 GB/s) |
| 64 | [System_Config.Ethos_U65_Client_Server] |
| 65 | core_clock=1e9 |
| 66 | axi0_port=Sram |
| 67 | axi1_port=Dram |
| 68 | Sram_clock_scale=1.0 |
| 69 | Dram_clock_scale=0.75 |
| 70 | |
| 71 | ; ----------------------------------------------------------------------------- |
| 72 | ; Memory Mode |
| 73 | |
| 74 | ; SRAM Only: only one AXI port is used and the SRAM is used for all storage |
| 75 | [Memory_Mode.Sram_Only] |
| 76 | const_mem_area=Axi0 |
| 77 | arena_mem_area=Axi0 |
| 78 | cache_mem_area=Axi0 |
| 79 | |
| 80 | ; Shared SRAM: the SRAM is shared between the Ethos-U and the Cortex-M software. |
| 81 | ; The non-SRAM memory is assumed to be read-only |
| 82 | [Memory_Mode.Shared_Sram] |
| 83 | const_mem_area=Axi1 |
| 84 | arena_mem_area=Axi0 |
| 85 | cache_mem_area=Axi0 |
| 86 | |
| 87 | ; Dedicated SRAM: the SRAM (384KB) is only for use by the Ethos-U |
| 88 | ; The non-SRAM memory is assumed to be read-writeable |
| 89 | [Memory_Mode.Dedicated_Sram] |
| 90 | const_mem_area=Axi1 |
| 91 | arena_mem_area=Axi1 |
| 92 | cache_mem_area=Axi0 |
| 93 | cache_sram_size=393216 |
| 94 | |
| 95 | ; Dedicated SRAM 512KB: the SRAM (512KB) is only for use by the Ethos-U |
| 96 | ; The non-SRAM memory is assumed to be read-writeable |
| 97 | [Memory_Mode.Dedicated_Sram_512KB] |
| 98 | inherit=Memory_Mode.Dedicated_Sram |
| 99 | cache_sram_size=524288 |