Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 1 | # Copyright (C) 2020 Arm Limited or its affiliates. All rights reserved. |
| 2 | # |
| 3 | # SPDX-License-Identifier: Apache-2.0 |
| 4 | # |
| 5 | # Licensed under the Apache License, Version 2.0 (the License); you may |
| 6 | # not use this file except in compliance with the License. |
| 7 | # You may obtain a copy of the License at |
| 8 | # |
| 9 | # www.apache.org/licenses/LICENSE-2.0 |
| 10 | # |
| 11 | # Unless required by applicable law or agreed to in writing, software |
| 12 | # distributed under the License is distributed on an AS IS BASIS, WITHOUT |
| 13 | # WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 14 | # See the License for the specific language governing permissions and |
| 15 | # limitations under the License. |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 16 | # Description: |
| 17 | # NPU performance estimation functions to estimate performance of a Pass and CascadedPass. Uses a model that takes the |
| 18 | # maximum of the 'cycles required for bandwidth' and 'cycles required for computing'. |
| 19 | # |
| 20 | # Called during scheduling to evaluate different proposals, as well as post-scheduling to provide a final performance |
| 21 | # estimate. |
Diqing Zhong | e168b96 | 2020-11-05 17:18:47 +0100 | [diff] [blame] | 22 | from enum import auto |
| 23 | from enum import IntEnum |
Diego Russo | ea6111a | 2020-04-14 18:41:58 +0100 | [diff] [blame] | 24 | |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 25 | import numpy as np |
Diego Russo | ea6111a | 2020-04-14 18:41:58 +0100 | [diff] [blame] | 26 | |
| 27 | from . import numeric_util |
Diqing Zhong | 09387e2 | 2020-09-28 18:46:22 +0200 | [diff] [blame] | 28 | from .architecture_features import Accelerator |
Diego Russo | e8a1045 | 2020-04-21 17:39:10 +0100 | [diff] [blame] | 29 | from .architecture_features import Block |
Diqing Zhong | e8887a3 | 2020-09-24 09:53:48 +0200 | [diff] [blame] | 30 | from .data_type import DataType |
Diego Russo | e8a1045 | 2020-04-21 17:39:10 +0100 | [diff] [blame] | 31 | from .nn_graph import PassPlacement |
| 32 | from .nn_graph import SchedulerRewrite |
Diego Russo | ea6111a | 2020-04-14 18:41:58 +0100 | [diff] [blame] | 33 | from .operation import NpuBlockType |
Diqing Zhong | e8887a3 | 2020-09-24 09:53:48 +0200 | [diff] [blame] | 34 | from .operation import Op |
Diqing Zhong | 09387e2 | 2020-09-28 18:46:22 +0200 | [diff] [blame] | 35 | from .shared_buffer_allocation import is_acc_40bits_used |
Diqing Zhong | f842b69 | 2020-12-11 13:07:37 +0100 | [diff] [blame] | 36 | from .tensor import BandwidthDirection |
Diego Russo | e8a1045 | 2020-04-21 17:39:10 +0100 | [diff] [blame] | 37 | from .tensor import MemArea |
| 38 | from .tensor import shape_num_elements |
Diqing Zhong | ef0c7fe | 2020-11-24 14:38:20 +0100 | [diff] [blame] | 39 | from .tensor import Tensor |
Diego Russo | e8a1045 | 2020-04-21 17:39:10 +0100 | [diff] [blame] | 40 | from .tensor import TensorBlockTraversal |
Diqing Zhong | e168b96 | 2020-11-05 17:18:47 +0100 | [diff] [blame] | 41 | from .tensor import TensorFormat |
Diego Russo | e8a1045 | 2020-04-21 17:39:10 +0100 | [diff] [blame] | 42 | from .tensor import TensorPurpose |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 43 | |
| 44 | |
| 45 | def rolling_buffer_dims_from_passes(arch, ps1, block_config_ps1, ps2, block_config_ps2): |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 46 | ofm_block = Block(block_config_ps2[-3], block_config_ps2[-4], block_config_ps2[-1]) |
Tim Hall | 4ed38bc | 2020-10-20 18:54:20 +0100 | [diff] [blame] | 47 | kernel = ps2.primary_op.kernel |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 48 | |
Michael McGeagh | f3e3ad7 | 2020-12-02 12:39:03 +0000 | [diff] [blame] | 49 | if ps2.npu_block_type in (NpuBlockType.ConvolutionMxN, NpuBlockType.VectorProduct): |
Louis Verhaard | 93dc553 | 2020-06-07 12:40:18 +0200 | [diff] [blame] | 50 | op = ps2.primary_op |
Patrik Gustavsson | 2349d42 | 2020-12-01 16:02:29 +0100 | [diff] [blame^] | 51 | ifm_block_depth = arch.calc_ifm_block_depth(op.ifm_shapes[0][-1], op.ifm.dtype.size_in_bits()) |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 52 | else: |
| 53 | ifm_block_depth = block_config_ps2[-1] |
| 54 | |
Louis Verhaard | 93dc553 | 2020-06-07 12:40:18 +0200 | [diff] [blame] | 55 | ifm_block = arch.get_ifm_block_size(ifm_block_depth, ofm_block, kernel, arch.ofm_block_max) |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 56 | |
| 57 | # The performed height calculation is for worst case |
| 58 | height = numeric_util.round_up(ifm_block.height + block_config_ps1[0], block_config_ps1[0]) |
| 59 | width = ifm_block.width |
Louis Verhaard | 93dc553 | 2020-06-07 12:40:18 +0200 | [diff] [blame] | 60 | return [height, width] |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 61 | |
| 62 | |
Diqing Zhong | e168b96 | 2020-11-05 17:18:47 +0100 | [diff] [blame] | 63 | class PassCycles(IntEnum): |
Diqing Zhong | 42e833d | 2020-10-02 13:18:42 +0200 | [diff] [blame] | 64 | Npu = 0 |
Diqing Zhong | e168b96 | 2020-11-05 17:18:47 +0100 | [diff] [blame] | 65 | SramAccess = auto() |
| 66 | DramAccess = auto() |
| 67 | OnChipFlashAccess = auto() |
| 68 | OffChipFlashAccess = auto() |
| 69 | Total = auto() |
| 70 | Size = auto() |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 71 | |
| 72 | def display_name(self): |
Tim Hall | 1bd531d | 2020-11-01 20:59:36 +0000 | [diff] [blame] | 73 | return ("NPU", "SRAM Access", "DRAM Access", "On-chip Flash Access", "Off-chip Flash Access", "Total", "Size",)[ |
| 74 | self.value |
| 75 | ] |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 76 | |
| 77 | def identifier_name(self): |
Tim Hall | 1bd531d | 2020-11-01 20:59:36 +0000 | [diff] [blame] | 78 | return ("npu", "sram_access", "dram_access", "on_chip_flash_access", "off_chip_flash_access", "total", "size",)[ |
| 79 | self.value |
| 80 | ] |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 81 | |
| 82 | @staticmethod |
| 83 | def all(): |
| 84 | return ( |
Diqing Zhong | 42e833d | 2020-10-02 13:18:42 +0200 | [diff] [blame] | 85 | PassCycles.Npu, |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 86 | PassCycles.SramAccess, |
| 87 | PassCycles.DramAccess, |
| 88 | PassCycles.OnChipFlashAccess, |
| 89 | PassCycles.OffChipFlashAccess, |
| 90 | PassCycles.Total, |
| 91 | ) |
| 92 | |
| 93 | |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 94 | def make_bandwidth_array(): |
| 95 | return np.zeros((MemArea.Size, TensorPurpose.Size, BandwidthDirection.Size)) |
| 96 | |
| 97 | |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 98 | def make_cycles_array(): |
| 99 | return np.zeros(PassCycles.Size) |
| 100 | |
| 101 | |
| 102 | def make_metrics_arrays(): |
Diqing Zhong | 69aadd0 | 2020-12-08 13:08:48 +0100 | [diff] [blame] | 103 | return (make_bandwidth_array(), 0, make_cycles_array()) |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 104 | |
| 105 | |
Diqing Zhong | 42e833d | 2020-10-02 13:18:42 +0200 | [diff] [blame] | 106 | def get_ifm_block_depth(npu_block_type, ifm_depth, ifm_elemwidth, block_traversal, ofm_blk_depth): |
| 107 | ifm_blk_depth = ofm_blk_depth |
| 108 | |
Diqing Zhong | 69aadd0 | 2020-12-08 13:08:48 +0100 | [diff] [blame] | 109 | if npu_block_type in (NpuBlockType.ConvolutionMxN, NpuBlockType.VectorProduct, NpuBlockType.ReduceSum): |
Diqing Zhong | 42e833d | 2020-10-02 13:18:42 +0200 | [diff] [blame] | 110 | if ifm_elemwidth == 16 or block_traversal == TensorBlockTraversal.PartKernelFirst: |
| 111 | ifm_blk_depth = 16 |
| 112 | elif ifm_elemwidth == 8: |
| 113 | ifm_blk_depth = 32 |
| 114 | else: |
| 115 | ifm_blk_depth = 8 |
| 116 | |
| 117 | return min(ifm_depth, ifm_blk_depth) |
| 118 | |
| 119 | |
Diqing Zhong | ef0c7fe | 2020-11-24 14:38:20 +0100 | [diff] [blame] | 120 | def get_minimal_cmd_cycles(arch, ifm_tensor, ofm_tensor, ifm_blk: Block, ofm_blk: Block, output_cycles, dpu_cycles=0): |
Diqing Zhong | ef0c7fe | 2020-11-24 14:38:20 +0100 | [diff] [blame] | 121 | ifm_tens_blk = Tensor((1, ifm_blk.height, ifm_blk.width, ifm_blk.depth), ifm_tensor.dtype, "ifm_blk") |
| 122 | ofm_tens_blk = Tensor((1, ofm_blk.height, ofm_blk.width, ofm_blk.depth), ofm_tensor.dtype, "ofm_blk") |
| 123 | cycles_ifm_blk = ( |
Diqing Zhong | 69aadd0 | 2020-12-08 13:08:48 +0100 | [diff] [blame] | 124 | estimate_memory_transfer_efficiency(arch, ifm_tensor.mem_area, BandwidthDirection.Read, ifm_tens_blk, ifm_blk) |
Diqing Zhong | ef0c7fe | 2020-11-24 14:38:20 +0100 | [diff] [blame] | 125 | / arch.memory_bandwidths_per_cycle[ifm_tensor.mem_area] |
| 126 | ) |
| 127 | cycles_ofm_blk = ( |
Diqing Zhong | 69aadd0 | 2020-12-08 13:08:48 +0100 | [diff] [blame] | 128 | estimate_memory_transfer_efficiency(arch, ofm_tensor.mem_area, BandwidthDirection.Write, ofm_tens_blk, ofm_blk) |
Diqing Zhong | ef0c7fe | 2020-11-24 14:38:20 +0100 | [diff] [blame] | 129 | / arch.memory_bandwidths_per_cycle[ofm_tensor.mem_area] |
| 130 | ) |
| 131 | return ( |
Diqing Zhong | f842b69 | 2020-12-11 13:07:37 +0100 | [diff] [blame] | 132 | arch.memory_latency[ifm_tensor.mem_area][BandwidthDirection.Read] |
Diqing Zhong | ef0c7fe | 2020-11-24 14:38:20 +0100 | [diff] [blame] | 133 | + cycles_ifm_blk |
| 134 | + dpu_cycles |
| 135 | + output_cycles |
Diqing Zhong | f842b69 | 2020-12-11 13:07:37 +0100 | [diff] [blame] | 136 | + arch.memory_latency[ofm_tensor.mem_area][BandwidthDirection.Write] |
Diqing Zhong | ef0c7fe | 2020-11-24 14:38:20 +0100 | [diff] [blame] | 137 | + cycles_ofm_blk |
| 138 | ) / 4 |
| 139 | |
| 140 | |
Diqing Zhong | 42e833d | 2020-10-02 13:18:42 +0200 | [diff] [blame] | 141 | def estimate_output_cycles( |
Diqing Zhong | ef0c7fe | 2020-11-24 14:38:20 +0100 | [diff] [blame] | 142 | arch, |
| 143 | npu_block_type, |
| 144 | primary_op, |
| 145 | num_elems, |
| 146 | ifm_tensor, |
| 147 | ofm_tensor, |
| 148 | use_acc_40bits=False, |
| 149 | ifm2_tensor=None, |
| 150 | block_config: Block = None, |
Diqing Zhong | 09387e2 | 2020-09-28 18:46:22 +0200 | [diff] [blame] | 151 | ): |
Louis Verhaard | e8a5a78 | 2020-11-02 18:04:27 +0100 | [diff] [blame] | 152 | faf = None if primary_op.activation is None else primary_op.activation.op_type |
Diqing Zhong | 09387e2 | 2020-09-28 18:46:22 +0200 | [diff] [blame] | 153 | if npu_block_type == NpuBlockType.ElementWise and ifm_tensor.dtype == DataType.int32: |
| 154 | if ifm2_tensor is None: |
Diqing Zhong | e8887a3 | 2020-09-24 09:53:48 +0200 | [diff] [blame] | 155 | # Unary op |
| 156 | output_perf_index = 0 |
| 157 | else: |
| 158 | # Binary op |
| 159 | output_perf_index = 1 |
Diqing Zhong | 09387e2 | 2020-09-28 18:46:22 +0200 | [diff] [blame] | 160 | elif primary_op.type == Op.Mul and ofm_tensor.dtype == DataType.int32: |
Diqing Zhong | e8887a3 | 2020-09-24 09:53:48 +0200 | [diff] [blame] | 161 | output_perf_index = 2 |
Diqing Zhong | 09387e2 | 2020-09-28 18:46:22 +0200 | [diff] [blame] | 162 | elif primary_op.type == Op.Mul or ( |
Diqing Zhong | e8887a3 | 2020-09-24 09:53:48 +0200 | [diff] [blame] | 163 | npu_block_type |
| 164 | in ( |
| 165 | NpuBlockType.ConvolutionMxN, |
| 166 | NpuBlockType.ConvolutionDepthWise, |
| 167 | NpuBlockType.Pooling, |
| 168 | NpuBlockType.ReduceSum, |
| 169 | NpuBlockType.VectorProduct, |
| 170 | ) |
Diqing Zhong | 09387e2 | 2020-09-28 18:46:22 +0200 | [diff] [blame] | 171 | and use_acc_40bits |
Diqing Zhong | e8887a3 | 2020-09-24 09:53:48 +0200 | [diff] [blame] | 172 | ): |
| 173 | output_perf_index = 3 |
Diqing Zhong | 09387e2 | 2020-09-28 18:46:22 +0200 | [diff] [blame] | 174 | elif primary_op.type in (Op.Add, Op.Sub): |
| 175 | input_scale = ifm_tensor.quantization.scale_f32 |
| 176 | input2_scale = ifm2_tensor.quantization.scale_f32 |
| 177 | output_scale = ofm_tensor.quantization.scale_f32 |
Diqing Zhong | e8887a3 | 2020-09-24 09:53:48 +0200 | [diff] [blame] | 178 | |
| 179 | if "resizebilinear" in primary_op.attrs: |
| 180 | output_scale = input2_scale |
| 181 | |
| 182 | if None in (input_scale, input2_scale, output_scale) or input_scale == input2_scale: |
| 183 | # Simple Add/Sub |
| 184 | output_perf_index = 4 |
| 185 | else: |
| 186 | # Advanced Add/Sub |
| 187 | output_perf_index = 5 |
Diqing Zhong | 09387e2 | 2020-09-28 18:46:22 +0200 | [diff] [blame] | 188 | elif primary_op.type.is_maxpool_op(): |
Diqing Zhong | e8887a3 | 2020-09-24 09:53:48 +0200 | [diff] [blame] | 189 | output_perf_index = 6 |
| 190 | else: |
| 191 | output_perf_index = 7 |
| 192 | |
| 193 | if faf in (Op.Sigmoid, Op.Tanh, Op.LUT): |
| 194 | activation_perf_index = 0 |
| 195 | elif faf in (Op.Relu, Op.Relu6, Op.ReluN1To1): |
| 196 | activation_perf_index = 1 |
| 197 | else: |
| 198 | activation_perf_index = 2 |
| 199 | |
Diqing Zhong | e8887a3 | 2020-09-24 09:53:48 +0200 | [diff] [blame] | 200 | cycle_per_elem = max( |
| 201 | arch.output_cycles_per_elem[output_perf_index], arch.activation_cycles_per_elem[activation_perf_index] |
| 202 | ) |
Diqing Zhong | 986e319 | 2020-11-16 16:15:56 +0100 | [diff] [blame] | 203 | |
Diqing Zhong | ef0c7fe | 2020-11-24 14:38:20 +0100 | [diff] [blame] | 204 | if primary_op.type.is_elementwise_op() and block_config is not None: |
| 205 | num_elems_blk = block_config.width * block_config.height * block_config.depth |
| 206 | cycle_cmd = get_minimal_cmd_cycles( |
| 207 | arch, ifm_tensor, ofm_tensor, block_config, block_config, num_elems_blk * cycle_per_elem |
| 208 | ) |
| 209 | cycle_per_elem = max(cycle_per_elem, cycle_cmd / num_elems_blk) |
| 210 | |
Diqing Zhong | e8887a3 | 2020-09-24 09:53:48 +0200 | [diff] [blame] | 211 | return num_elems * cycle_per_elem |
| 212 | |
| 213 | |
Diqing Zhong | 42e833d | 2020-10-02 13:18:42 +0200 | [diff] [blame] | 214 | def estimate_conv_pooling_cycles( |
Diqing Zhong | 986e319 | 2020-11-16 16:15:56 +0100 | [diff] [blame] | 215 | arch, |
| 216 | npu_block_type, |
| 217 | primary_op, |
Diqing Zhong | ef0c7fe | 2020-11-24 14:38:20 +0100 | [diff] [blame] | 218 | ifm_block: Block, |
| 219 | ofm_block: Block, |
Diqing Zhong | 986e319 | 2020-11-16 16:15:56 +0100 | [diff] [blame] | 220 | block_traversal, |
| 221 | kernel_dims, |
| 222 | ifm_tensor, |
| 223 | ofm_tensor, |
| 224 | scale_tensor=None, |
Diqing Zhong | 09387e2 | 2020-09-28 18:46:22 +0200 | [diff] [blame] | 225 | ): |
Diqing Zhong | e5204a6 | 2020-10-13 11:42:37 +0200 | [diff] [blame] | 226 | ofm_ublock = Block(arch.config.ofm_ublock.width, arch.config.ofm_ublock.height, arch.config.ofm_ublock.depth) |
Patrik Gustavsson | 2349d42 | 2020-12-01 16:02:29 +0100 | [diff] [blame^] | 227 | ifm_tens_shape = primary_op.ifm_shapes[0] |
| 228 | ofm_tens_shape = primary_op.ofm_shapes[0] |
Diqing Zhong | e5204a6 | 2020-10-13 11:42:37 +0200 | [diff] [blame] | 229 | |
| 230 | if ( |
| 231 | arch.config.ofm_ublock.height == 2 |
| 232 | and npu_block_type |
| 233 | in (NpuBlockType.ConvolutionMxN, NpuBlockType.ConvolutionDepthWise, NpuBlockType.VectorProduct) |
| 234 | and ofm_tens_shape[1] == 1 |
| 235 | # Optimisation only applies for even width tensors |
| 236 | and ofm_tens_shape[2] % 2 == 0 |
| 237 | and kernel_dims[0] == 1 |
| 238 | ): |
| 239 | ofm_ublock.width = 4 |
| 240 | ofm_ublock.height = 1 |
Diqing Zhong | ef0c7fe | 2020-11-24 14:38:20 +0100 | [diff] [blame] | 241 | ofm_block.height = 1 |
Diqing Zhong | e5204a6 | 2020-10-13 11:42:37 +0200 | [diff] [blame] | 242 | |
Diqing Zhong | ef0c7fe | 2020-11-24 14:38:20 +0100 | [diff] [blame] | 243 | num_ublk_x = numeric_util.round_up_divide(ofm_block.width, ofm_ublock.width) |
| 244 | num_ublk_y = ofm_block.height // ofm_ublock.height |
| 245 | num_ublk_xy = num_ublk_x * num_ublk_y |
| 246 | num_ublk_z = ofm_block.depth // ofm_ublock.depth |
Diqing Zhong | 09387e2 | 2020-09-28 18:46:22 +0200 | [diff] [blame] | 247 | num_ofm_blk = 0 |
| 248 | total_cycles = 0 |
Diqing Zhong | ef0c7fe | 2020-11-24 14:38:20 +0100 | [diff] [blame] | 249 | num_elems_blk = ofm_block.width * ofm_block.height * ofm_block.depth |
Diqing Zhong | 09387e2 | 2020-09-28 18:46:22 +0200 | [diff] [blame] | 250 | use_acc_40bits = is_acc_40bits_used(npu_block_type, ifm_tensor, ofm_tensor) |
| 251 | |
| 252 | sub_kernel_limits = arch.sub_kernel_limits[npu_block_type] |
| 253 | n_sub_kernels_y = numeric_util.round_up_divide(kernel_dims[0], sub_kernel_limits[0]) |
| 254 | n_sub_kernels_x = numeric_util.round_up_divide(kernel_dims[1], sub_kernel_limits[1]) |
| 255 | sub_kernel_x = [ |
| 256 | min((kernel_dims[1] - i * sub_kernel_limits[1]), sub_kernel_limits[1]) for i in range(n_sub_kernels_x) |
| 257 | ] |
| 258 | sub_kernel_y = [ |
| 259 | min((kernel_dims[0] - i * sub_kernel_limits[0]), sub_kernel_limits[0]) for i in range(n_sub_kernels_y) |
| 260 | ] |
| 261 | sub_kernel_size = (x * y for y in sub_kernel_y for x in sub_kernel_x) |
| 262 | |
Diqing Zhong | 09387e2 | 2020-09-28 18:46:22 +0200 | [diff] [blame] | 263 | cycles_dpu_blk = 0 |
Diqing Zhong | 986e319 | 2020-11-16 16:15:56 +0100 | [diff] [blame] | 264 | cycles_wb = 32 * ofm_ublock.depth // 8 |
Diqing Zhong | 09387e2 | 2020-09-28 18:46:22 +0200 | [diff] [blame] | 265 | |
| 266 | for num_kernel_elems in sub_kernel_size: |
| 267 | if npu_block_type == NpuBlockType.Pooling: |
Diqing Zhong | ef0c7fe | 2020-11-24 14:38:20 +0100 | [diff] [blame] | 268 | num_kernel_steps = 1 |
Diqing Zhong | 986e319 | 2020-11-16 16:15:56 +0100 | [diff] [blame] | 269 | cycles = max(4, num_kernel_elems) * num_ublk_xy * num_ublk_z |
Diqing Zhong | 09387e2 | 2020-09-28 18:46:22 +0200 | [diff] [blame] | 270 | if ifm_tensor.dtype.size_in_bits() == 16 and arch.accelerator_config != Accelerator.Ethos_U55_32: |
| 271 | cycles *= 2 |
| 272 | elif npu_block_type == NpuBlockType.ConvolutionDepthWise: |
Diqing Zhong | 986e319 | 2020-11-16 16:15:56 +0100 | [diff] [blame] | 273 | cycles = 4 * num_ublk_xy |
Diqing Zhong | 09387e2 | 2020-09-28 18:46:22 +0200 | [diff] [blame] | 274 | if ifm_tensor.dtype.size_in_bits() == 16: |
| 275 | cycles *= 2 |
Diqing Zhong | ef0c7fe | 2020-11-24 14:38:20 +0100 | [diff] [blame] | 276 | num_kernel_steps = numeric_util.round_up_divide(num_kernel_elems, 4) |
| 277 | cycles = max(cycles_wb, cycles) * num_kernel_steps * num_ublk_z |
Diqing Zhong | 09387e2 | 2020-09-28 18:46:22 +0200 | [diff] [blame] | 278 | elif ( |
| 279 | (npu_block_type == NpuBlockType.ConvolutionMxN and block_traversal != TensorBlockTraversal.PartKernelFirst) |
| 280 | or npu_block_type == NpuBlockType.VectorProduct |
| 281 | or npu_block_type == NpuBlockType.ReduceSum |
| 282 | ): |
Diqing Zhong | ef0c7fe | 2020-11-24 14:38:20 +0100 | [diff] [blame] | 283 | num_kernel_steps = num_kernel_elems |
| 284 | cycles = max(cycles_wb, 4 * num_ublk_xy) * num_kernel_steps * num_ublk_z |
Diqing Zhong | 09387e2 | 2020-09-28 18:46:22 +0200 | [diff] [blame] | 285 | else: |
| 286 | assert block_traversal == TensorBlockTraversal.PartKernelFirst |
| 287 | divider = 2 if ifm_tensor.dtype.size_in_bits() == 16 else 4 |
Diqing Zhong | ef0c7fe | 2020-11-24 14:38:20 +0100 | [diff] [blame] | 288 | num_kernel_steps = numeric_util.round_up_divide(num_kernel_elems, divider) |
Diqing Zhong | 986e319 | 2020-11-16 16:15:56 +0100 | [diff] [blame] | 289 | cycles = max(cycles_wb, 4 * num_ublk_xy) * ( |
Diqing Zhong | ef0c7fe | 2020-11-24 14:38:20 +0100 | [diff] [blame] | 290 | num_kernel_steps * numeric_util.round_up_divide(ifm_block.depth, 8) * num_ublk_z |
Diqing Zhong | 09387e2 | 2020-09-28 18:46:22 +0200 | [diff] [blame] | 291 | ) |
Diqing Zhong | ef0c7fe | 2020-11-24 14:38:20 +0100 | [diff] [blame] | 292 | |
| 293 | delay_cycles = 0 |
| 294 | if arch.accelerator_config is Accelerator.Ethos_U55_32: |
| 295 | delay = 7 if use_acc_40bits else 3 |
| 296 | if num_ublk_x == 1 and num_ublk_y == 1: |
| 297 | if num_ublk_z == 1: |
| 298 | delay_cycles = delay * num_kernel_steps |
| 299 | elif num_kernel_steps > 1: |
| 300 | delay_cycles = delay * (num_kernel_steps - 1) * num_ublk_z |
| 301 | if (num_ublk_x == 1 or num_ublk_y == 1) and num_ublk_z > 1 and use_acc_40bits: |
| 302 | delay_cycles += delay * num_ublk_z |
| 303 | else: |
| 304 | delay = ( |
| 305 | 3 |
| 306 | if use_acc_40bits and arch.accelerator_config in (Accelerator.Ethos_U55_64, Accelerator.Ethos_U55_128) |
| 307 | else 2 |
| 308 | ) |
| 309 | if num_ublk_x == 1 and num_ublk_y == 1: |
| 310 | if num_ublk_z == 1: |
| 311 | delay_cycles = delay * num_kernel_steps |
| 312 | elif num_kernel_steps > 1: |
| 313 | delay_cycles = delay * (num_kernel_steps - 1) * num_ublk_z |
| 314 | |
| 315 | if npu_block_type == NpuBlockType.ConvolutionMxN and block_traversal == TensorBlockTraversal.PartKernelFirst: |
| 316 | delay_cycles *= numeric_util.round_up_divide(ifm_block.depth, 8) |
| 317 | |
Diqing Zhong | 09387e2 | 2020-09-28 18:46:22 +0200 | [diff] [blame] | 318 | cycles_dpu_blk += cycles |
Diqing Zhong | ef0c7fe | 2020-11-24 14:38:20 +0100 | [diff] [blame] | 319 | cycles_dpu_blk += delay_cycles |
| 320 | |
| 321 | if npu_block_type in (NpuBlockType.ConvolutionMxN, NpuBlockType.VectorProduct, NpuBlockType.ReduceSum): |
| 322 | cycles_dpu_blk *= numeric_util.round_up_divide(ifm_tens_shape[3], ifm_block.depth) |
Diqing Zhong | 09387e2 | 2020-09-28 18:46:22 +0200 | [diff] [blame] | 323 | |
| 324 | cycles_dpu_blk /= arch.ncores |
| 325 | |
| 326 | num_ofm_blk = ( |
Diqing Zhong | ef0c7fe | 2020-11-24 14:38:20 +0100 | [diff] [blame] | 327 | numeric_util.round_up_divide(ofm_tens_shape[1], ofm_block.height) |
| 328 | * numeric_util.round_up_divide(ofm_tens_shape[2], ofm_block.width) |
| 329 | * numeric_util.round_up_divide(ofm_tens_shape[3], ofm_block.depth) |
Diqing Zhong | 09387e2 | 2020-09-28 18:46:22 +0200 | [diff] [blame] | 330 | ) |
| 331 | |
Diqing Zhong | 42e833d | 2020-10-02 13:18:42 +0200 | [diff] [blame] | 332 | cycles_output_blk = estimate_output_cycles( |
Diqing Zhong | ef0c7fe | 2020-11-24 14:38:20 +0100 | [diff] [blame] | 333 | arch, npu_block_type, primary_op, num_elems_blk, ifm_tensor, ofm_tensor, use_acc_40bits |
Diqing Zhong | 09387e2 | 2020-09-28 18:46:22 +0200 | [diff] [blame] | 334 | ) |
| 335 | |
Diqing Zhong | 986e319 | 2020-11-16 16:15:56 +0100 | [diff] [blame] | 336 | if scale_tensor: |
Diqing Zhong | f842b69 | 2020-12-11 13:07:37 +0100 | [diff] [blame] | 337 | cycles_bias_blk = ( |
| 338 | 10 |
| 339 | * min(ofm_block.depth, ofm_tens_shape[3]) |
| 340 | * arch.memory_latency[scale_tensor.mem_area][BandwidthDirection.Read] |
| 341 | / 256 |
| 342 | ) |
Diqing Zhong | 986e319 | 2020-11-16 16:15:56 +0100 | [diff] [blame] | 343 | cycles_output_blk = max(cycles_output_blk, cycles_bias_blk) |
| 344 | |
Diqing Zhong | ef0c7fe | 2020-11-24 14:38:20 +0100 | [diff] [blame] | 345 | cycles_cmd = get_minimal_cmd_cycles( |
| 346 | arch, ifm_tensor, ofm_tensor, ifm_block, ofm_block, cycles_dpu_blk, cycles_output_blk |
| 347 | ) |
| 348 | cycles_dpu_blk = max(cycles_dpu_blk, cycles_cmd) |
| 349 | cycles_output_blk = max(cycles_output_blk, cycles_cmd) |
| 350 | |
Diqing Zhong | 09387e2 | 2020-09-28 18:46:22 +0200 | [diff] [blame] | 351 | if cycles_dpu_blk > cycles_output_blk: |
| 352 | total_cycles = cycles_dpu_blk * num_ofm_blk + cycles_output_blk |
| 353 | else: |
| 354 | total_cycles = cycles_output_blk * num_ofm_blk + cycles_dpu_blk |
| 355 | |
| 356 | return total_cycles |
| 357 | |
| 358 | |
Diqing Zhong | 69aadd0 | 2020-12-08 13:08:48 +0100 | [diff] [blame] | 359 | def estimate_memory_transfer_efficiency(arch, mem_area, direction, tensor, block_size: Block, replace_bw=None): |
Diqing Zhong | e168b96 | 2020-11-05 17:18:47 +0100 | [diff] [blame] | 360 | if tensor.format not in (TensorFormat.NHWC, TensorFormat.NHCWB16): |
| 361 | return tensor.bandwidth() if replace_bw is None else replace_bw |
| 362 | |
| 363 | # Estimate memory transfer efficiency by calculating the burst length |
| 364 | # this is related to data format, block shape, and tensor shape, etc. |
Diqing Zhong | e168b96 | 2020-11-05 17:18:47 +0100 | [diff] [blame] | 365 | burst_len = 0 |
| 366 | elem_size = tensor.dtype.size_in_bytes() |
| 367 | is_ifm = direction == BandwidthDirection.Read |
| 368 | tens = tensor.clone() |
| 369 | if not tens.avoid_NHCWB16: |
| 370 | tens.set_format(TensorFormat.NHCWB16, arch) |
| 371 | |
| 372 | if tens.format == TensorFormat.NHCWB16: |
| 373 | if tens.get_strides()[1] == block_size.depth: |
| 374 | burst_len = elem_size * block_size.depth * block_size.width |
| 375 | elif is_ifm: |
| 376 | burst_len = 16 * elem_size * block_size.width |
| 377 | else: |
| 378 | burst_len = 16 * elem_size * block_size.width * arch.ncores |
| 379 | else: |
| 380 | assert tens.format == TensorFormat.NHWC |
| 381 | if is_ifm: |
| 382 | if tens.get_strides()[3] == block_size.depth: |
| 383 | burst_len = elem_size * block_size.depth * block_size.width |
| 384 | else: |
| 385 | burst_len = elem_size * block_size.depth |
| 386 | else: |
| 387 | if block_size.depth <= 16 and tens.get_strides()[3] == block_size.depth: |
| 388 | burst_len = elem_size * block_size.depth * block_size.width |
| 389 | else: |
| 390 | burst_len = min(64, 16 * elem_size * arch.ncores, block_size.depth * elem_size) |
| 391 | |
Diqing Zhong | f842b69 | 2020-12-11 13:07:37 +0100 | [diff] [blame] | 392 | burst_len = min(arch.memory_burst_length[mem_area], burst_len) |
Diqing Zhong | e168b96 | 2020-11-05 17:18:47 +0100 | [diff] [blame] | 393 | bw = tens.bandwidth() if replace_bw is None else replace_bw |
| 394 | |
Diqing Zhong | f842b69 | 2020-12-11 13:07:37 +0100 | [diff] [blame] | 395 | return bw * (arch.memory_burst_length[mem_area] / burst_len) |
Diqing Zhong | e168b96 | 2020-11-05 17:18:47 +0100 | [diff] [blame] | 396 | |
| 397 | |
Michael McGeagh | 6f72526 | 2020-12-03 15:21:36 +0000 | [diff] [blame] | 398 | def performance_metrics_for_pass(arch, ps, block_config=None, rewrite_list=None, force_outputs_to_fast_storage=False): |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 399 | if block_config is None: |
| 400 | block_config = ps.block_config |
| 401 | bws = make_bandwidth_array() |
Diqing Zhong | 69aadd0 | 2020-12-08 13:08:48 +0100 | [diff] [blame] | 402 | scaled_bws = make_bandwidth_array() # scaled bw with memory transfer efficiency |
| 403 | macs = 0 |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 404 | cycles = make_cycles_array() |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 405 | ifm_read_multiple = 1 |
| 406 | weight_read_multiple = 0 |
| 407 | |
Michael McGeagh | f3e3ad7 | 2020-12-02 12:39:03 +0000 | [diff] [blame] | 408 | if ps.placement in (PassPlacement.MemoryOnly, PassPlacement.StartupInit): |
Diqing Zhong | 69aadd0 | 2020-12-08 13:08:48 +0100 | [diff] [blame] | 409 | return bws, macs, cycles, ifm_read_multiple, weight_read_multiple # nothing real happening in this pass |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 410 | |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 411 | explicit_padding = (0, 0, 0, 0) |
| 412 | primary_op = ps.primary_op |
| 413 | replacement_read_bws = {} |
Diqing Zhong | e168b96 | 2020-11-05 17:18:47 +0100 | [diff] [blame] | 414 | ofm_block = Block(block_config[1], block_config[0], block_config[3]) |
| 415 | ifm_block = Block(block_config[1], block_config[0], block_config[3]) |
| 416 | |
Tim Hall | 1bd531d | 2020-11-01 20:59:36 +0000 | [diff] [blame] | 417 | if ps.placement == PassPlacement.Npu and primary_op: |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 418 | explicit_padding = primary_op.attrs.get("explicit_padding", explicit_padding) |
Louis Verhaard | aee5d75 | 2020-09-30 09:01:52 +0200 | [diff] [blame] | 419 | assert primary_op.type.npu_block_type == ps.npu_block_type |
| 420 | npu_block_type = primary_op.type.npu_block_type |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 421 | |
| 422 | ifm_tensor, _, weight_tensor, ofm_tensor = ps.get_primary_op_ifm_ifm2_weights_ofm() |
Patrik Gustavsson | 2349d42 | 2020-12-01 16:02:29 +0100 | [diff] [blame^] | 423 | ifm_tensor_shape = list(ps.primary_op.ifm_shapes[0]) |
| 424 | ofm_tensor_shape = list(ps.primary_op.ofm_shapes[0]) |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 425 | |
Diqing Zhong | ef0c7fe | 2020-11-24 14:38:20 +0100 | [diff] [blame] | 426 | if npu_block_type == NpuBlockType.ReduceSum: |
| 427 | block_traversal = TensorBlockTraversal.DepthFirst |
| 428 | elif npu_block_type in ( |
| 429 | NpuBlockType.ConvolutionMxN, |
| 430 | NpuBlockType.ConvolutionDepthWise, |
| 431 | NpuBlockType.VectorProduct, |
| 432 | ): |
| 433 | block_traversal = weight_tensor.block_traversal |
| 434 | else: |
| 435 | block_traversal = TensorBlockTraversal.Default |
| 436 | ifm_block_depth = get_ifm_block_depth( |
| 437 | npu_block_type, ifm_tensor_shape[3], ifm_tensor.dtype.size_in_bits(), block_traversal, ofm_block.depth |
| 438 | ) |
| 439 | ifm_block = arch.get_ifm_block_size( |
| 440 | ifm_block_depth, ofm_block, primary_op.kernel, ifm_resampling_mode=ifm_tensor.resampling_mode |
| 441 | ) |
| 442 | |
Michael McGeagh | f3e3ad7 | 2020-12-02 12:39:03 +0000 | [diff] [blame] | 443 | if npu_block_type in ( |
| 444 | NpuBlockType.ConvolutionMxN, |
| 445 | NpuBlockType.ConvolutionDepthWise, |
Diqing Zhong | 69aadd0 | 2020-12-08 13:08:48 +0100 | [diff] [blame] | 446 | NpuBlockType.VectorProduct, |
Michael McGeagh | f3e3ad7 | 2020-12-02 12:39:03 +0000 | [diff] [blame] | 447 | NpuBlockType.Pooling, |
| 448 | NpuBlockType.ReduceSum, |
Tim Hall | c30f495 | 2020-06-15 20:47:35 +0100 | [diff] [blame] | 449 | ): |
Charles Xu | 3e9c434 | 2020-04-22 08:31:43 +0200 | [diff] [blame] | 450 | # extent the ifm to full dimension |
Diqing Zhong | 42e833d | 2020-10-02 13:18:42 +0200 | [diff] [blame] | 451 | batch_size = ifm_tensor_shape[0] |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 452 | |
| 453 | # add in padding |
| 454 | ifm_tensor_shape[1] += explicit_padding[0] + explicit_padding[2] # height += top and bottom |
| 455 | ifm_tensor_shape[2] += explicit_padding[1] + explicit_padding[3] # width += left and right |
| 456 | |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 457 | if npu_block_type != NpuBlockType.Pooling: |
Diqing Zhong | 09387e2 | 2020-09-28 18:46:22 +0200 | [diff] [blame] | 458 | if npu_block_type == NpuBlockType.ReduceSum: |
Diqing Zhong | 09387e2 | 2020-09-28 18:46:22 +0200 | [diff] [blame] | 459 | weight_tensor_shape = [1, 1, ifm_tensor.shape[3], ofm_tensor.shape[3]] |
| 460 | weight_tensor_bandwidth_shape = [0] * 4 |
| 461 | weight_tensor_element_size = 0 |
| 462 | weight_tensor_bandwidth_compression_scale = 0.0 |
| 463 | else: |
Diqing Zhong | 69aadd0 | 2020-12-08 13:08:48 +0100 | [diff] [blame] | 464 | # For Vector product, weight format of IO is extended to HWIO, with H=W=1 |
| 465 | weight_tensor_shape = numeric_util.full_shape(4, weight_tensor.shape, 1) |
| 466 | weight_tensor_bandwidth_shape = numeric_util.full_shape(4, weight_tensor.bandwidth_shape, 1) |
Diqing Zhong | 09387e2 | 2020-09-28 18:46:22 +0200 | [diff] [blame] | 467 | weight_tensor_element_size = weight_tensor.element_size() |
| 468 | weight_tensor_bandwidth_compression_scale = weight_tensor.bandwidth_compression_scale |
Diqing Zhong | 69aadd0 | 2020-12-08 13:08:48 +0100 | [diff] [blame] | 469 | |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 470 | nn_ops = ( |
Diqing Zhong | 69aadd0 | 2020-12-08 13:08:48 +0100 | [diff] [blame] | 471 | int(ofm_tensor_shape[0]) |
| 472 | * int(ofm_tensor_shape[1]) |
| 473 | * int(ofm_tensor_shape[2]) |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 474 | * int(weight_tensor_shape[0]) |
| 475 | * int(weight_tensor_shape[1]) |
| 476 | * int(weight_tensor_shape[2]) |
| 477 | * int(weight_tensor_shape[3]) |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 478 | ) |
| 479 | else: |
| 480 | weight_tensor_shape = [ |
| 481 | primary_op.attrs["ksize"][1], |
| 482 | primary_op.attrs["ksize"][2], |
| 483 | 1, |
| 484 | ifm_tensor_shape[3], |
| 485 | ] |
| 486 | weight_tensor_bandwidth_shape = weight_tensor_shape |
| 487 | weight_tensor_element_size = 0 |
| 488 | weight_tensor_bandwidth_compression_scale = 0.0 |
| 489 | nn_ops = 0 # pooling doesn't count as NN ops |
| 490 | |
| 491 | kernel_dims = weight_tensor_shape[:2] |
| 492 | |
| 493 | sub_kernel_limits = arch.sub_kernel_limits[npu_block_type] |
| 494 | # count the sub kernels; the IFM block needs to be refetched for each of them |
| 495 | n_sub_kernels_y = numeric_util.round_up_divide(kernel_dims[0], sub_kernel_limits[0]) |
| 496 | n_sub_kernels_x = numeric_util.round_up_divide(kernel_dims[1], sub_kernel_limits[1]) |
| 497 | n_sub_kernels = n_sub_kernels_y * n_sub_kernels_x |
| 498 | |
Diqing Zhong | 69aadd0 | 2020-12-08 13:08:48 +0100 | [diff] [blame] | 499 | n_full_depth_stages = numeric_util.round_up_divide(weight_tensor_bandwidth_shape[3], ofm_block.depth) |
| 500 | if npu_block_type in (NpuBlockType.ConvolutionDepthWise, NpuBlockType.Pooling): |
| 501 | n_full_depth_stages = 1 # force to no reread |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 502 | |
Diqing Zhong | 69aadd0 | 2020-12-08 13:08:48 +0100 | [diff] [blame] | 503 | ifm_read_multiple = n_sub_kernels * n_full_depth_stages |
| 504 | replacement_read_bws[ifm_tensor] = ifm_tensor.bandwidth() * ifm_read_multiple |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 505 | |
Diqing Zhong | 69aadd0 | 2020-12-08 13:08:48 +0100 | [diff] [blame] | 506 | weight_read_multiple = numeric_util.round_up_divide( |
| 507 | ofm_tensor_shape[1], ofm_block.height |
| 508 | ) * numeric_util.round_up_divide(ofm_tensor_shape[2], ofm_block.width) |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 509 | replacement_read_bws[weight_tensor] = ( |
| 510 | batch_size |
| 511 | * shape_num_elements(weight_tensor_bandwidth_shape) |
| 512 | * weight_tensor_element_size |
| 513 | * weight_tensor_bandwidth_compression_scale |
Diqing Zhong | 69aadd0 | 2020-12-08 13:08:48 +0100 | [diff] [blame] | 514 | * weight_read_multiple |
| 515 | ) |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 516 | |
Diqing Zhong | 69aadd0 | 2020-12-08 13:08:48 +0100 | [diff] [blame] | 517 | macs += nn_ops |
Diqing Zhong | 42e833d | 2020-10-02 13:18:42 +0200 | [diff] [blame] | 518 | cycles[PassCycles.Npu] = estimate_conv_pooling_cycles( |
Diqing Zhong | 986e319 | 2020-11-16 16:15:56 +0100 | [diff] [blame] | 519 | arch, |
| 520 | npu_block_type, |
| 521 | primary_op, |
Diqing Zhong | ef0c7fe | 2020-11-24 14:38:20 +0100 | [diff] [blame] | 522 | ifm_block, |
Diqing Zhong | 986e319 | 2020-11-16 16:15:56 +0100 | [diff] [blame] | 523 | ofm_block, |
| 524 | block_traversal, |
| 525 | kernel_dims, |
| 526 | ifm_tensor, |
| 527 | ofm_tensor, |
| 528 | ps.scale_tensor, |
Diqing Zhong | 09387e2 | 2020-09-28 18:46:22 +0200 | [diff] [blame] | 529 | ) |
Diqing Zhong | e8887a3 | 2020-09-24 09:53:48 +0200 | [diff] [blame] | 530 | elif npu_block_type == NpuBlockType.ElementWise: |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 531 | # Work out how many elements we have and calculate performance. |
Diqing Zhong | 42e833d | 2020-10-02 13:18:42 +0200 | [diff] [blame] | 532 | cycles[PassCycles.Npu] = estimate_output_cycles( |
Diqing Zhong | ef0c7fe | 2020-11-24 14:38:20 +0100 | [diff] [blame] | 533 | arch, |
| 534 | npu_block_type, |
| 535 | primary_op, |
| 536 | ofm_tensor.elements(), |
| 537 | ps.ifm_tensor, |
| 538 | ps.ofm_tensor, |
| 539 | None, |
| 540 | ps.ifm2_tensor, |
| 541 | ofm_block, |
Diqing Zhong | 09387e2 | 2020-09-28 18:46:22 +0200 | [diff] [blame] | 542 | ) |
Diqing Zhong | 42e833d | 2020-10-02 13:18:42 +0200 | [diff] [blame] | 543 | |
| 544 | prev_npu_pass = next((npu_ps for npu_ps in ps.dag_predecessors if npu_ps.placement is PassPlacement.Npu), None) |
| 545 | if prev_npu_pass is None: |
| 546 | # cycles for DMA ops in first pass |
| 547 | dma_ops = (op for op in ps.ops if op.type == Op.DMA) |
| 548 | for dma_op in dma_ops: |
| 549 | mem_area = dma_op.attrs["source"] |
| 550 | for tens in dma_op.inputs: |
| 551 | cycles[PassCycles.Npu] += tens.storage_size() / arch.memory_bandwidths_per_cycle[mem_area] |
| 552 | |
Michael McGeagh | 6f72526 | 2020-12-03 15:21:36 +0000 | [diff] [blame] | 553 | if rewrite_list is not None: |
| 554 | # apply the desired rewrites |
| 555 | for rewrite_op, tens, _, _, _, ps_to_rewrite in rewrite_list: |
| 556 | if ps != ps_to_rewrite: |
| 557 | continue |
| 558 | if rewrite_op == SchedulerRewrite.Nop: |
| 559 | pass # these are fine, no bandwidth changes |
| 560 | elif rewrite_op in (SchedulerRewrite.ChangeTensorSubPurpose,): |
Diqing Zhong | 69aadd0 | 2020-12-08 13:08:48 +0100 | [diff] [blame] | 561 | bws[arch.fast_storage_mem_area][tens.purpose][BandwidthDirection.Read] += replacement_read_bws[tens] |
Michael McGeagh | 6f72526 | 2020-12-03 15:21:36 +0000 | [diff] [blame] | 562 | if tens.purpose == TensorPurpose.FeatureMap: |
Diqing Zhong | 69aadd0 | 2020-12-08 13:08:48 +0100 | [diff] [blame] | 563 | scaled_bw = estimate_memory_transfer_efficiency( |
Michael McGeagh | 6f72526 | 2020-12-03 15:21:36 +0000 | [diff] [blame] | 564 | arch, |
| 565 | arch.fast_storage_mem_area, |
| 566 | BandwidthDirection.Read, |
| 567 | tens, |
| 568 | ifm_block, |
| 569 | replacement_read_bws[tens], |
| 570 | ) |
| 571 | else: |
Diqing Zhong | 69aadd0 | 2020-12-08 13:08:48 +0100 | [diff] [blame] | 572 | scaled_bw = replacement_read_bws[tens] |
| 573 | scaled_bws[arch.fast_storage_mem_area][tens.purpose][BandwidthDirection.Read] += scaled_bw |
Michael McGeagh | 6f72526 | 2020-12-03 15:21:36 +0000 | [diff] [blame] | 574 | replacement_read_bws[tens] = 0 |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 575 | |
| 576 | for tens in ps.outputs: |
| 577 | if force_outputs_to_fast_storage: |
Diqing Zhong | 69aadd0 | 2020-12-08 13:08:48 +0100 | [diff] [blame] | 578 | bws[arch.fast_storage_mem_area][tens.purpose][BandwidthDirection.Write] += tens.bandwidth() |
| 579 | scaled_bws[arch.fast_storage_mem_area][tens.purpose][ |
| 580 | BandwidthDirection.Write |
| 581 | ] += estimate_memory_transfer_efficiency( |
Diqing Zhong | e168b96 | 2020-11-05 17:18:47 +0100 | [diff] [blame] | 582 | arch, arch.fast_storage_mem_area, BandwidthDirection.Write, tens, ofm_block |
| 583 | ) |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 584 | else: |
Diqing Zhong | 69aadd0 | 2020-12-08 13:08:48 +0100 | [diff] [blame] | 585 | bws[tens.mem_area][tens.purpose][BandwidthDirection.Write] += tens.bandwidth() |
| 586 | scaled_bws[tens.mem_area][tens.purpose][BandwidthDirection.Write] += estimate_memory_transfer_efficiency( |
Diqing Zhong | e168b96 | 2020-11-05 17:18:47 +0100 | [diff] [blame] | 587 | arch, tens.mem_area, BandwidthDirection.Write, tens, ofm_block |
| 588 | ) |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 589 | |
| 590 | for tens in ps.intermediates: |
| 591 | bws[tens.mem_area][tens.purpose][BandwidthDirection.Write] += tens.bandwidth() |
Diqing Zhong | 69aadd0 | 2020-12-08 13:08:48 +0100 | [diff] [blame] | 592 | scaled_bws[tens.mem_area][tens.purpose][BandwidthDirection.Write] += tens.bandwidth() |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 593 | |
| 594 | if tens in replacement_read_bws: |
| 595 | bw = replacement_read_bws[tens] |
| 596 | else: |
| 597 | bw = tens.bandwidth() |
| 598 | |
| 599 | bws[tens.mem_area][tens.purpose][BandwidthDirection.Read] += bw |
Diqing Zhong | 69aadd0 | 2020-12-08 13:08:48 +0100 | [diff] [blame] | 600 | scaled_bws[tens.mem_area][tens.purpose][BandwidthDirection.Read] += bw |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 601 | |
| 602 | for tens in ps.inputs: |
Diqing Zhong | 69aadd0 | 2020-12-08 13:08:48 +0100 | [diff] [blame] | 603 | if tens in replacement_read_bws: |
| 604 | bw = replacement_read_bws[tens] |
| 605 | else: |
| 606 | bw = tens.bandwidth() |
| 607 | |
| 608 | bws[tens.mem_area][tens.purpose][BandwidthDirection.Read] += bw |
| 609 | scaled_bws[tens.mem_area][tens.purpose][BandwidthDirection.Read] += estimate_memory_transfer_efficiency( |
| 610 | arch, tens.mem_area, BandwidthDirection.Read, tens, ifm_block, bw |
Diqing Zhong | e168b96 | 2020-11-05 17:18:47 +0100 | [diff] [blame] | 611 | ) |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 612 | |
| 613 | # quick build access counts for only current pass, even though these aren't the final numbers |
Diqing Zhong | 69aadd0 | 2020-12-08 13:08:48 +0100 | [diff] [blame] | 614 | update_summary_cycles(arch, scaled_bws, cycles) |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 615 | |
Diqing Zhong | 69aadd0 | 2020-12-08 13:08:48 +0100 | [diff] [blame] | 616 | return bws, macs, cycles, ifm_read_multiple, weight_read_multiple |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 617 | |
| 618 | |
Diqing Zhong | e168b96 | 2020-11-05 17:18:47 +0100 | [diff] [blame] | 619 | def update_summary_cycles(arch, bws, cycles): |
| 620 | cycles[PassCycles.SramAccess] = np.sum(bws[MemArea.Sram]) / arch.memory_bandwidths_per_cycle[MemArea.Sram] |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 621 | cycles[PassCycles.DramAccess] = np.sum(bws[MemArea.Dram]) / arch.memory_bandwidths_per_cycle[MemArea.Dram] |
| 622 | cycles[PassCycles.OnChipFlashAccess] = ( |
| 623 | np.sum(bws[MemArea.OnChipFlash]) / arch.memory_bandwidths_per_cycle[MemArea.OnChipFlash] |
| 624 | ) |
| 625 | cycles[PassCycles.OffChipFlashAccess] = ( |
| 626 | np.sum(bws[MemArea.OffChipFlash]) / arch.memory_bandwidths_per_cycle[MemArea.OffChipFlash] |
| 627 | ) |
| 628 | |
| 629 | cycles[PassCycles.Total] = np.max(cycles[: PassCycles.Total]) |
| 630 | return cycles |
| 631 | |
| 632 | |
| 633 | def collate_stats_for_cascaded_pass(arch, bws, macs, cycles): |
| 634 | return bws, macs, cycles |
| 635 | |
| 636 | |
| 637 | def performance_for_cascaded_pass(arch, cps): |
| 638 | total_bws = make_bandwidth_array() |
Diqing Zhong | 69aadd0 | 2020-12-08 13:08:48 +0100 | [diff] [blame] | 639 | total_macs = 0 |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 640 | total_cycles = make_cycles_array() |
| 641 | |
| 642 | for ps in cps.passes: |
Diqing Zhong | 69aadd0 | 2020-12-08 13:08:48 +0100 | [diff] [blame] | 643 | bws, macs, cycles, _, _ = performance_metrics_for_pass(arch, ps) |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 644 | ps.bandwidths = bws |
| 645 | ps.macs = macs |
| 646 | ps.cycles = cycles |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 647 | total_bws += bws |
| 648 | total_macs += macs |
| 649 | total_cycles += cycles |
| 650 | |
| 651 | bws, macs, cycles = collate_stats_for_cascaded_pass(arch, total_bws, total_macs, total_cycles) |
| 652 | cps.bandwidths = bws |
| 653 | cps.macs = macs |
| 654 | cps.cycles = cycles |
| 655 | return bws, macs, cycles |
| 656 | |
| 657 | |
| 658 | def calc_performance_for_network(nng, arch): |
| 659 | total_bws = make_bandwidth_array() |
Diqing Zhong | 69aadd0 | 2020-12-08 13:08:48 +0100 | [diff] [blame] | 660 | total_macs = 0 |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 661 | total_cycles = np.zeros(PassCycles.Size) |
| 662 | |
| 663 | for sg in nng.subgraphs: |
| 664 | for cps in sg.cascaded_passes: |
| 665 | bws, macs, cycles = performance_for_cascaded_pass(arch, cps) |
| 666 | total_bws += bws |
| 667 | total_macs += macs |
| 668 | total_cycles += cycles |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 669 | |
| 670 | nng.bandwidths = total_bws |
| 671 | nng.macs = total_macs |
| 672 | nng.cycles = total_cycles |