Tim Hall | 1c8f92d | 2024-01-25 10:17:26 +0000 | [diff] [blame] | 1 | # SPDX-FileCopyrightText: Copyright 2020-2024 Arm Limited and/or its affiliates <open-source-office@arm.com> |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 2 | # |
| 3 | # SPDX-License-Identifier: Apache-2.0 |
| 4 | # |
| 5 | # Licensed under the Apache License, Version 2.0 (the License); you may |
| 6 | # not use this file except in compliance with the License. |
| 7 | # You may obtain a copy of the License at |
| 8 | # |
| 9 | # www.apache.org/licenses/LICENSE-2.0 |
| 10 | # |
| 11 | # Unless required by applicable law or agreed to in writing, software |
| 12 | # distributed under the License is distributed on an AS IS BASIS, WITHOUT |
| 13 | # WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 14 | # See the License for the specific language governing permissions and |
| 15 | # limitations under the License. |
Rickard Bolin | bc6ee58 | 2022-11-04 08:24:29 +0000 | [diff] [blame] | 16 | # |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 17 | # Description: |
Tim Hall | c8a7386 | 2020-10-27 12:43:14 +0000 | [diff] [blame] | 18 | # Holds a container for Ethos-U and System architecture parameters. |
Diego Russo | ea6111a | 2020-04-14 18:41:58 +0100 | [diff] [blame] | 19 | import enum |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 20 | from collections import namedtuple |
| 21 | from configparser import ConfigParser |
Diego Russo | ea6111a | 2020-04-14 18:41:58 +0100 | [diff] [blame] | 22 | |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 23 | import numpy as np |
Diego Russo | ea6111a | 2020-04-14 18:41:58 +0100 | [diff] [blame] | 24 | |
Louis Verhaard | aeae567 | 2020-11-02 18:04:27 +0100 | [diff] [blame] | 25 | from .api import NpuAccelerator |
Tim Hall | 1bd531d | 2020-11-01 20:59:36 +0000 | [diff] [blame] | 26 | from .errors import CliOptionError |
| 27 | from .errors import ConfigOptionError |
Dwight Lidman | a9390f7 | 2020-05-13 12:00:08 +0200 | [diff] [blame] | 28 | from .ethos_u55_regs.ethos_u55_regs import resampling_mode |
Louis Verhaard | 69b3176 | 2020-11-17 09:45:20 +0100 | [diff] [blame] | 29 | from .numeric_util import full_shape |
Diego Russo | e8a1045 | 2020-04-21 17:39:10 +0100 | [diff] [blame] | 30 | from .numeric_util import round_up |
| 31 | from .numeric_util import round_up_divide |
erik.andersson@arm.com | 1d6d5c4 | 2021-04-14 13:31:05 +0200 | [diff] [blame] | 32 | from .numeric_util import round_up_to_int |
Tim Hall | 4ed38bc | 2020-10-20 18:54:20 +0100 | [diff] [blame] | 33 | from .operation import Kernel |
Diego Russo | ea6111a | 2020-04-14 18:41:58 +0100 | [diff] [blame] | 34 | from .operation import NpuBlockType |
Tim Hall | 4ed38bc | 2020-10-20 18:54:20 +0100 | [diff] [blame] | 35 | from .operation import PointXYZ |
Diqing Zhong | f842b69 | 2020-12-11 13:07:37 +0100 | [diff] [blame] | 36 | from .tensor import BandwidthDirection |
Diego Russo | e8a1045 | 2020-04-21 17:39:10 +0100 | [diff] [blame] | 37 | from .tensor import MemArea |
Patrik Gustavsson | eca2e95 | 2020-05-27 09:15:11 +0200 | [diff] [blame] | 38 | from .tensor import MemType |
Diego Russo | e8a1045 | 2020-04-21 17:39:10 +0100 | [diff] [blame] | 39 | from .tensor import TensorFormat |
| 40 | from .tensor import TensorPurpose |
Jonas Ohlsson | 45e653d | 2021-07-26 16:13:12 +0200 | [diff] [blame] | 41 | from .tflite_supported_operators import TFLiteSupportedOperators |
Patrik Gustavsson | 8f1f9aa | 2021-06-28 07:41:58 +0200 | [diff] [blame] | 42 | from .tosa_supported_operators import TosaSupportedOperators |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 43 | |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 44 | |
| 45 | class Block: |
Tim Hall | d8339a7 | 2021-05-27 18:49:40 +0100 | [diff] [blame] | 46 | def __init__(self, w=0, h=0, d=0): |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 47 | self.width = w |
| 48 | self.height = h |
| 49 | self.depth = d |
| 50 | |
Tim Hall | d8339a7 | 2021-05-27 18:49:40 +0100 | [diff] [blame] | 51 | def elements(self): |
| 52 | return self.width * self.height * self.depth |
| 53 | |
| 54 | def elements_wh(self): |
| 55 | return self.width * self.height |
| 56 | |
| 57 | def clone(self): |
| 58 | return Block(self.width, self.height, self.depth) |
| 59 | |
| 60 | def as_list(self): |
| 61 | return [self.height, self.width, self.depth] |
| 62 | |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 63 | def __eq__(self, other): |
| 64 | if self.width == other.width and self.height == other.height and self.depth == other.depth: |
| 65 | return True |
| 66 | else: |
| 67 | return False |
| 68 | |
| 69 | def __repr__(self): |
| 70 | return "<Block: {0},{1},{2}>".format(self.width, self.height, self.depth) |
| 71 | |
Tim Hall | d8339a7 | 2021-05-27 18:49:40 +0100 | [diff] [blame] | 72 | def to_hwc(self): |
| 73 | return [self.height, self.width, self.depth] |
| 74 | |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 75 | @classmethod |
| 76 | def from_string(cls, s): |
| 77 | w, h, c = (int(v) for v in s.split("x")) |
| 78 | return cls(w, h, c) |
| 79 | |
Louis Verhaard | 69b3176 | 2020-11-17 09:45:20 +0100 | [diff] [blame] | 80 | @classmethod |
| 81 | def from_shape(cls, shape) -> "Block": |
| 82 | """Converts the shape to a Block""" |
| 83 | shp = full_shape(3, shape, 1) |
| 84 | # Note: index from end, as len(shp) may be > 3 |
| 85 | return Block(shp[-2], shp[-3], shp[-1]) |
| 86 | |
Tim Hall | d8339a7 | 2021-05-27 18:49:40 +0100 | [diff] [blame] | 87 | @classmethod |
| 88 | def min(cls, a, b): |
| 89 | return cls(min(a.width, b.width), min(a.height, b.height), min(a.depth, b.depth)) |
| 90 | |
| 91 | @classmethod |
| 92 | def max(cls, a, b): |
| 93 | return cls(max(a.width, b.width), max(a.height, b.height), max(a.depth, b.depth)) |
| 94 | |
| 95 | @classmethod |
| 96 | def round(cls, a, b): |
| 97 | return cls(round_up(a.width, b.width), round_up(a.height, b.height), round_up(a.depth, b.depth)) |
| 98 | |
| 99 | @classmethod |
| 100 | def div_round_up(cls, a, b): |
| 101 | return cls( |
| 102 | round_up_divide(a.width, b.width), round_up_divide(a.height, b.height), round_up_divide(a.depth, b.depth) |
| 103 | ) |
| 104 | |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 105 | |
| 106 | class Rect: |
| 107 | def __init__(self, x, y, z, x2, y2, z2): |
| 108 | self.x = x |
| 109 | self.y = y |
| 110 | self.z = z |
| 111 | self.x2 = x2 |
| 112 | self.y2 = y2 |
| 113 | self.z2 = z2 |
| 114 | |
| 115 | def start(self): |
| 116 | return PointXYZ(self.x, self.y, self.z) |
| 117 | |
| 118 | def end(self): |
| 119 | return PointXYZ(self.x2, self.y2, self.z2) |
| 120 | |
| 121 | def size(self): |
| 122 | return Block(self.x2 - self.x + 1, self.y2 - self.y + 1, self.z2 - self.z + 1) |
| 123 | |
| 124 | def __repr__(self): |
| 125 | return "<Rect: ({0},{1},{2}) ({3},{4},{5})>".format(self.x, self.y, self.z, self.x2, self.y2, self.z2) |
| 126 | |
| 127 | |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 128 | class SHRAMElements: |
| 129 | IFM8 = 0 |
| 130 | IFM16 = 1 |
| 131 | IFM8_Elementwise = 2 |
| 132 | IFM16_Elementwise = 3 |
Fredrik Svedberg | 597fd3f | 2020-08-13 10:02:53 +0200 | [diff] [blame] | 133 | IFM32 = 4 |
Fredrik Svedberg | a0c3624 | 2020-06-03 15:43:31 +0200 | [diff] [blame] | 134 | Acc16 = 5 |
| 135 | Acc32 = 6 |
| 136 | Acc40 = 7 |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 137 | Last = Acc40 |
Fredrik Svedberg | a0c3624 | 2020-06-03 15:43:31 +0200 | [diff] [blame] | 138 | BitSizes = np.array([8, 16, 8, 16, 32, 16, 32, 40], np.int32) |
Louis Verhaard | f98c674 | 2020-05-12 14:22:38 +0200 | [diff] [blame] | 139 | ByteSizes = BitSizes // 8 |
Fredrik Svedberg | a0c3624 | 2020-06-03 15:43:31 +0200 | [diff] [blame] | 140 | PostAlign = np.array([8, 8, 8, 8, 8, 1, 1, 1], np.int32) |
| 141 | PreAlign = np.array([1, 1, 1, 1, 1, 8, 8, 8], np.int32) |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 142 | |
| 143 | |
| 144 | class SHRAMBlockConfig: |
| 145 | def __init__(self, sizes, banks): |
| 146 | assert len(banks) == SHRAMElements.Last + 1 |
| 147 | self.sizes = sizes |
| 148 | self.banks = banks |
| 149 | |
| 150 | |
Tim Hall | c8a7386 | 2020-10-27 12:43:14 +0000 | [diff] [blame] | 151 | # Area indices must match Ethos-U SHRAM layout spec |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 152 | class SharedBufferArea(enum.IntEnum): |
| 153 | OFM = 0 |
| 154 | Weights = 1 |
| 155 | IFM = 2 |
| 156 | Accumulators = 3 |
| 157 | Size = Accumulators + 1 |
| 158 | |
| 159 | |
Manupa Karunaratne | d83d2e1 | 2020-07-20 12:05:32 +0100 | [diff] [blame] | 160 | class Accelerator(enum.Enum): |
| 161 | Ethos_U55_32 = "ethos-u55-32" |
| 162 | Ethos_U55_64 = "ethos-u55-64" |
| 163 | Ethos_U55_128 = "ethos-u55-128" |
| 164 | Ethos_U55_256 = "ethos-u55-256" |
Tim Hall | c8a7386 | 2020-10-27 12:43:14 +0000 | [diff] [blame] | 165 | Ethos_U65_256 = "ethos-u65-256" |
| 166 | Ethos_U65_512 = "ethos-u65-512" |
Manupa Karunaratne | d83d2e1 | 2020-07-20 12:05:32 +0100 | [diff] [blame] | 167 | |
| 168 | @classmethod |
| 169 | def member_list(cls): |
| 170 | return [e.value for e in cls] |
| 171 | |
Louis Verhaard | aeae567 | 2020-11-02 18:04:27 +0100 | [diff] [blame] | 172 | @classmethod |
| 173 | def from_npu_accelerator(cls, npu_accelerator: NpuAccelerator) -> "Accelerator": |
| 174 | """Converts the given public API object to Accelerator (used internally)""" |
| 175 | accelerator_map = { |
| 176 | NpuAccelerator.Ethos_U55_32: cls.Ethos_U55_32, |
| 177 | NpuAccelerator.Ethos_U55_64: cls.Ethos_U55_64, |
| 178 | NpuAccelerator.Ethos_U55_128: cls.Ethos_U55_128, |
| 179 | NpuAccelerator.Ethos_U55_256: cls.Ethos_U55_256, |
| 180 | NpuAccelerator.Ethos_U65_256: cls.Ethos_U65_256, |
| 181 | NpuAccelerator.Ethos_U65_512: cls.Ethos_U65_512, |
| 182 | } |
| 183 | assert npu_accelerator in accelerator_map, f"Unsupported accelerator {npu_accelerator}" |
| 184 | return accelerator_map[npu_accelerator] |
| 185 | |
Manupa Karunaratne | d83d2e1 | 2020-07-20 12:05:32 +0100 | [diff] [blame] | 186 | |
Tim Hall | 1bd531d | 2020-11-01 20:59:36 +0000 | [diff] [blame] | 187 | @enum.unique |
| 188 | class MemPort(enum.Enum): |
| 189 | Axi0 = enum.auto() |
| 190 | Axi1 = enum.auto() |
| 191 | |
| 192 | |
Tim Hall | d8339a7 | 2021-05-27 18:49:40 +0100 | [diff] [blame] | 193 | SHRAMConfig = namedtuple( |
| 194 | "SHRAMConfig", ["reserved_output_banks", "bank_size_bytes", "total_banks", "reserved_end_banks"] |
| 195 | ) |
| 196 | |
| 197 | |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 198 | class ArchitectureFeatures: |
Tim Hall | c8a7386 | 2020-10-27 12:43:14 +0000 | [diff] [blame] | 199 | """This class is a container for various parameters of the Ethos-U core |
Diqing Zhong | e8887a3 | 2020-09-24 09:53:48 +0200 | [diff] [blame] | 200 | and system configuration that can be tuned, either by command line |
Tim Hall | c8a7386 | 2020-10-27 12:43:14 +0000 | [diff] [blame] | 201 | parameters or by the Ethos-U architects. The class is often passed |
Diqing Zhong | e8887a3 | 2020-09-24 09:53:48 +0200 | [diff] [blame] | 202 | around to passes that need to do architecture-dependent actions. |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 203 | |
Diqing Zhong | e8887a3 | 2020-09-24 09:53:48 +0200 | [diff] [blame] | 204 | Note the difference between ArchitectureFeatures and CompilerOptions |
Tim Hall | c8a7386 | 2020-10-27 12:43:14 +0000 | [diff] [blame] | 205 | - ArchitectureFeatures is for changing the Ethos-U and system architecture |
Diqing Zhong | e8887a3 | 2020-09-24 09:53:48 +0200 | [diff] [blame] | 206 | - CompilerOptions is for changing the behaviour of the compiler |
| 207 | """ |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 208 | |
| 209 | ArchitectureConfig = namedtuple( |
| 210 | "ArchitectureConfig", "macs cores ofm_ublock ifm_ublock shram_banks shram_granules elem_units" |
| 211 | ) |
| 212 | accelerator_configs = { |
Tim Hall | c8a7386 | 2020-10-27 12:43:14 +0000 | [diff] [blame] | 213 | Accelerator.Ethos_U65_512: ArchitectureConfig( |
Fredrik Svedberg | a0c3624 | 2020-06-03 15:43:31 +0200 | [diff] [blame] | 214 | 256, 2, Block(2, 2, 8), Block(2, 2, 8), 48, [8, 8, 8, 8, 16, 8, 16, 20], 8 |
Manupa Karunaratne | d83d2e1 | 2020-07-20 12:05:32 +0100 | [diff] [blame] | 215 | ), |
Tim Hall | c8a7386 | 2020-10-27 12:43:14 +0000 | [diff] [blame] | 216 | Accelerator.Ethos_U65_256: ArchitectureConfig( |
Fredrik Svedberg | a0c3624 | 2020-06-03 15:43:31 +0200 | [diff] [blame] | 217 | 256, 1, Block(2, 2, 8), Block(2, 2, 8), 48, [8, 8, 8, 8, 16, 8, 16, 20], 8 |
Manupa Karunaratne | d83d2e1 | 2020-07-20 12:05:32 +0100 | [diff] [blame] | 218 | ), |
| 219 | Accelerator.Ethos_U55_256: ArchitectureConfig( |
Fredrik Svedberg | a0c3624 | 2020-06-03 15:43:31 +0200 | [diff] [blame] | 220 | 256, 1, Block(2, 2, 8), Block(2, 2, 8), 48, [8, 8, 8, 8, 16, 8, 16, 20], 8 |
Manupa Karunaratne | d83d2e1 | 2020-07-20 12:05:32 +0100 | [diff] [blame] | 221 | ), |
| 222 | Accelerator.Ethos_U55_128: ArchitectureConfig( |
Dwight Lidman | 2f75457 | 2021-04-21 12:00:37 +0200 | [diff] [blame] | 223 | 128, 1, Block(2, 1, 8), Block(2, 1, 8), 24, [4, 4, 4, 4, 8, 4, 8, 12], 4 |
Manupa Karunaratne | d83d2e1 | 2020-07-20 12:05:32 +0100 | [diff] [blame] | 224 | ), |
| 225 | Accelerator.Ethos_U55_64: ArchitectureConfig( |
Fredrik Svedberg | a0c3624 | 2020-06-03 15:43:31 +0200 | [diff] [blame] | 226 | 64, 1, Block(1, 1, 8), Block(1, 1, 8), 16, [2, 2, 2, 2, 4, 4, 4, 8], 2 |
Manupa Karunaratne | d83d2e1 | 2020-07-20 12:05:32 +0100 | [diff] [blame] | 227 | ), |
| 228 | Accelerator.Ethos_U55_32: ArchitectureConfig( |
Fredrik Svedberg | a0c3624 | 2020-06-03 15:43:31 +0200 | [diff] [blame] | 229 | 32, 1, Block(1, 1, 4), Block(1, 1, 8), 16, [2, 2, 2, 2, 4, 4, 4, 4], 1 |
Manupa Karunaratne | d83d2e1 | 2020-07-20 12:05:32 +0100 | [diff] [blame] | 230 | ), |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 231 | } |
| 232 | |
| 233 | OFMSplitDepth = 16 |
Manupa Karunaratne | d83d2e1 | 2020-07-20 12:05:32 +0100 | [diff] [blame] | 234 | SubKernelMax = Block(8, 8, 65536) |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 235 | |
Tim Hall | 1bd531d | 2020-11-01 20:59:36 +0000 | [diff] [blame] | 236 | DEFAULT_CONFIG = "internal-default" |
Louis Verhaard | 1e17018 | 2020-11-26 11:42:04 +0100 | [diff] [blame] | 237 | MAX_BLOCKDEP = 3 |
Tim Hall | 1bd531d | 2020-11-01 20:59:36 +0000 | [diff] [blame] | 238 | |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 239 | def __init__( |
| 240 | self, |
Tim Hall | 1bd531d | 2020-11-01 20:59:36 +0000 | [diff] [blame] | 241 | vela_config_files, |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 242 | accelerator_config, |
| 243 | system_config, |
Tim Hall | 1bd531d | 2020-11-01 20:59:36 +0000 | [diff] [blame] | 244 | memory_mode, |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 245 | max_blockdep, |
Tim Hall | 1bd531d | 2020-11-01 20:59:36 +0000 | [diff] [blame] | 246 | verbose_config, |
Tim Hall | d8339a7 | 2021-05-27 18:49:40 +0100 | [diff] [blame] | 247 | arena_cache_size, |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 248 | ): |
| 249 | accelerator_config = accelerator_config.lower() |
Manupa Karunaratne | d83d2e1 | 2020-07-20 12:05:32 +0100 | [diff] [blame] | 250 | if accelerator_config not in Accelerator.member_list(): |
Tim Hall | 1bd531d | 2020-11-01 20:59:36 +0000 | [diff] [blame] | 251 | raise CliOptionError("--accelerator-config", self.accelerator_config, "Unknown accelerator configuration") |
Manupa Karunaratne | d83d2e1 | 2020-07-20 12:05:32 +0100 | [diff] [blame] | 252 | self.accelerator_config = Accelerator(accelerator_config) |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 253 | accel_config = ArchitectureFeatures.accelerator_configs[self.accelerator_config] |
| 254 | self.config = accel_config |
| 255 | |
Tim Hall | d8339a7 | 2021-05-27 18:49:40 +0100 | [diff] [blame] | 256 | self.accumulator_granules = { |
| 257 | SHRAMElements.Acc16: accel_config.shram_granules[SHRAMElements.Acc16], |
| 258 | SHRAMElements.Acc32: accel_config.shram_granules[SHRAMElements.Acc32], |
| 259 | SHRAMElements.Acc40: accel_config.shram_granules[SHRAMElements.Acc40], |
| 260 | } |
| 261 | |
| 262 | self.ifm_bank_granules = { |
| 263 | 8: accel_config.shram_granules[SHRAMElements.IFM8], |
| 264 | 16: accel_config.shram_granules[SHRAMElements.IFM16], |
| 265 | 32: accel_config.shram_granules[SHRAMElements.IFM32], |
| 266 | } |
| 267 | |
| 268 | self.ifm_ew_bank_granules = { |
| 269 | 8: accel_config.shram_granules[SHRAMElements.IFM8_Elementwise], |
| 270 | 16: accel_config.shram_granules[SHRAMElements.IFM16_Elementwise], |
| 271 | 32: accel_config.shram_granules[SHRAMElements.IFM32], |
| 272 | } |
| 273 | |
| 274 | self.shram = SHRAMConfig(2, 1024, accel_config.shram_banks, 2 if accel_config.shram_banks > 16 else 0) |
| 275 | |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 276 | self.system_config = system_config |
Tim Hall | 1bd531d | 2020-11-01 20:59:36 +0000 | [diff] [blame] | 277 | self.memory_mode = memory_mode |
Tim Hall | c8a7386 | 2020-10-27 12:43:14 +0000 | [diff] [blame] | 278 | self.is_ethos_u65_system = self.accelerator_config in (Accelerator.Ethos_U65_256, Accelerator.Ethos_U65_512) |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 279 | |
Tim Hall | 53c6245 | 2021-08-06 13:51:34 +0100 | [diff] [blame] | 280 | if self.is_ethos_u65_system: |
| 281 | self.max_outstanding_dma = 2 |
| 282 | axi_port_address_width = 40 |
| 283 | axi_port_data_width = 128 |
| 284 | else: |
| 285 | self.max_outstanding_dma = 1 |
| 286 | axi_port_address_width = 32 |
| 287 | axi_port_data_width = 64 |
| 288 | |
Rickard Bolin | 909923a | 2023-10-17 07:08:54 +0000 | [diff] [blame] | 289 | self.max_outstanding_kernels = 2 |
Tim Hall | 289a41d | 2020-08-04 21:40:14 +0100 | [diff] [blame] | 290 | |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 291 | self.ncores = accel_config.cores |
| 292 | self.ofm_ublock = accel_config.ofm_ublock |
| 293 | self.ifm_ublock = accel_config.ifm_ublock |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 294 | self.ofm_block_max = Block(64, 32, 128) |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 295 | |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 296 | self.max_blockdep = max_blockdep |
| 297 | |
| 298 | dpu_min_height = accel_config.ofm_ublock.height |
| 299 | dpu_min_width = accel_config.ofm_ublock.width |
| 300 | dpu_dot_product_width = 8 |
| 301 | dpu_min_ofm_channels = accel_config.ofm_ublock.depth |
| 302 | |
| 303 | self.num_elem_wise_units = accel_config.elem_units |
| 304 | self.num_macs_per_cycle = dpu_min_height * dpu_min_width * dpu_dot_product_width * dpu_min_ofm_channels |
Tim Hall | c1be087 | 2022-03-03 17:50:52 +0000 | [diff] [blame] | 305 | assert self.num_macs_per_cycle == accel_config.macs, f"{self.num_macs_per_cycle} != {accel_config.macs}" |
Louis Verhaard | a208cf8 | 2021-03-30 16:07:24 +0200 | [diff] [blame] | 306 | # Max value in address offsets |
Tim Hall | 53c6245 | 2021-08-06 13:51:34 +0100 | [diff] [blame] | 307 | self.max_address_offset = 1 << axi_port_address_width |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 308 | |
Tim Hall | 1bd531d | 2020-11-01 20:59:36 +0000 | [diff] [blame] | 309 | # Get system configuration and memory mode |
Tim Hall | d8339a7 | 2021-05-27 18:49:40 +0100 | [diff] [blame] | 310 | self._get_vela_config(vela_config_files, verbose_config, arena_cache_size) |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 311 | |
Tim Hall | 53c6245 | 2021-08-06 13:51:34 +0100 | [diff] [blame] | 312 | self.memory_bandwidths_per_cycle = axi_port_data_width * self.memory_clock_scales / 8 |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 313 | |
Tim Hall | 1bd531d | 2020-11-01 20:59:36 +0000 | [diff] [blame] | 314 | self.memory_bandwidths_per_second = self.memory_bandwidths_per_cycle * self.core_clock |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 315 | |
Diqing Zhong | e8887a3 | 2020-09-24 09:53:48 +0200 | [diff] [blame] | 316 | # Get output/activation performance numbers |
| 317 | self._generate_output_perf_tables(self.accelerator_config) |
| 318 | |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 319 | # sizes as N x H x W x C. we need to round up to these when allocating storage |
| 320 | self.storage_rounding_quantums = { |
| 321 | TensorFormat.Unknown: (1, 1, 1, 1), |
| 322 | TensorFormat.WeightsCompressed: (1, 1, 1, 1), |
| 323 | TensorFormat.NHWC: (1, 1, 1, 1), |
| 324 | TensorFormat.NHCWB16: (1, 1, 1, 16), |
| 325 | } |
| 326 | |
| 327 | # brick sizes as N x H x W x C. We have to fetch whole bricks at a time |
| 328 | self.brick_sizes = { |
| 329 | TensorFormat.Unknown: (1, 1, 1, 1), |
| 330 | TensorFormat.WeightsCompressed: (1, 1, 1, 1), |
| 331 | TensorFormat.NHWC: (1, 1, 1, 1), |
| 332 | TensorFormat.NHCWB16: (1, 1, 1, 16), |
| 333 | } |
| 334 | |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 335 | self.default_weight_format = TensorFormat.WeightsCompressed |
| 336 | self.default_feature_map_format = TensorFormat.NHWC |
| 337 | |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 338 | self.tensor_storage_mem_area = { |
| 339 | # permanent mem_area |
Tim Hall | 465582c | 2020-05-26 09:33:14 +0100 | [diff] [blame] | 340 | TensorPurpose.Unknown: MemArea.Unknown, |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 341 | TensorPurpose.Weights: self.permanent_storage_mem_area, |
| 342 | TensorPurpose.FeatureMap: self.feature_map_storage_mem_area, |
Fredrik Svedberg | a0c3624 | 2020-06-03 15:43:31 +0200 | [diff] [blame] | 343 | TensorPurpose.LUT: self.permanent_storage_mem_area, |
Fredrik Svedberg | e22ba8c | 2021-01-27 16:53:41 +0100 | [diff] [blame] | 344 | TensorPurpose.Scratch: self.feature_map_storage_mem_area, |
| 345 | TensorPurpose.ScratchFast: self.fast_storage_mem_area, |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 346 | } |
| 347 | |
Patrik Gustavsson | eca2e95 | 2020-05-27 09:15:11 +0200 | [diff] [blame] | 348 | self.tensor_storage_mem_type = { |
Dwight Lidman | 1a9d20e | 2020-08-11 12:10:36 +0200 | [diff] [blame] | 349 | TensorPurpose.Unknown: MemType.Unknown, |
Patrik Gustavsson | eca2e95 | 2020-05-27 09:15:11 +0200 | [diff] [blame] | 350 | TensorPurpose.Weights: MemType.Permanent_NPU, |
| 351 | TensorPurpose.FeatureMap: MemType.Scratch, |
Fredrik Svedberg | a0c3624 | 2020-06-03 15:43:31 +0200 | [diff] [blame] | 352 | TensorPurpose.LUT: MemType.Scratch, |
Fredrik Svedberg | e22ba8c | 2021-01-27 16:53:41 +0100 | [diff] [blame] | 353 | TensorPurpose.Scratch: MemType.Scratch, |
| 354 | TensorPurpose.ScratchFast: MemType.Scratch_fast, |
Patrik Gustavsson | eca2e95 | 2020-05-27 09:15:11 +0200 | [diff] [blame] | 355 | } |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 356 | |
| 357 | self.min_block_sizes = { |
| 358 | NpuBlockType.Default: (dpu_min_height, dpu_min_width), |
| 359 | NpuBlockType.VectorProduct: (1, 1), |
| 360 | NpuBlockType.ConvolutionMxN: (dpu_min_height, dpu_min_width), |
| 361 | NpuBlockType.Pooling: (dpu_min_height, dpu_min_width), |
| 362 | NpuBlockType.ConvolutionDepthWise: (dpu_min_height, dpu_min_width), |
| 363 | NpuBlockType.ElementWise: (1, 1), |
Fredrik Svedberg | a0c3624 | 2020-06-03 15:43:31 +0200 | [diff] [blame] | 364 | NpuBlockType.ReduceSum: (dpu_min_height, dpu_min_width), |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 365 | } |
| 366 | |
| 367 | self.sub_kernel_limits = { |
| 368 | NpuBlockType.Default: (8, 8), |
| 369 | NpuBlockType.VectorProduct: (1, 1), |
| 370 | NpuBlockType.ConvolutionMxN: (8, 8), |
| 371 | NpuBlockType.Pooling: (8, 8), |
| 372 | NpuBlockType.ConvolutionDepthWise: (8, 8), |
| 373 | NpuBlockType.ElementWise: (1, 1), |
Fredrik Svedberg | a0c3624 | 2020-06-03 15:43:31 +0200 | [diff] [blame] | 374 | NpuBlockType.ReduceSum: (8, 8), |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 375 | } |
| 376 | |
| 377 | # weights for scheduler search |
| 378 | from .npu_performance import make_bandwidth_array |
| 379 | |
| 380 | self.bandwidth_weights = make_bandwidth_array() |
| 381 | self.bandwidth_weights[MemArea.Sram] = 1.0 |
| 382 | self.bandwidth_weights[MemArea.Dram] = 10.0 |
| 383 | self.bandwidth_weights[MemArea.OnChipFlash] = 2.0 |
| 384 | self.bandwidth_weights[MemArea.OffChipFlash] = 20.0 |
| 385 | self.cycles_weight = 40 |
| 386 | self.max_sram_used_weight = 1000 |
| 387 | |
Tim Hall | 1bd531d | 2020-11-01 20:59:36 +0000 | [diff] [blame] | 388 | if self.is_spilling_enabled(): |
Patrik Gustavsson | 3ab9452 | 2020-06-29 17:36:55 +0200 | [diff] [blame] | 389 | self.max_sram_used_weight = 0 |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 390 | |
| 391 | # Shared Buffer Block allocations |
| 392 | self.shram_bank_size = 1024 # bytes |
| 393 | self.shram_size_bytes = accel_config.shram_banks * self.shram_bank_size |
| 394 | self.shram_reserved_output_banks = 2 |
| 395 | self.shram_reserved_weight_banks = 0 |
| 396 | self.shram_reserved_unused_banks = 2 if accel_config.shram_banks > 16 else 0 |
| 397 | self.shram_total_banks = accel_config.shram_banks - self.shram_reserved_unused_banks |
| 398 | self.shram_bank_granules = np.array(accel_config.shram_granules, np.int32) |
Louis Verhaard | 0b8268a | 2020-08-05 16:11:29 +0200 | [diff] [blame] | 399 | self.shram_lut_size = 2048 |
Johan Alfven | 55d90dd | 2024-04-02 16:32:54 +0200 | [diff] [blame] | 400 | self.shram_lut_slot_size = 256 |
Louis Verhaard | 0b8268a | 2020-08-05 16:11:29 +0200 | [diff] [blame] | 401 | # SHRAM base address of the activation lookup table |
| 402 | self.shram_lut_address = self.shram_bank_size * self.available_shram_banks(True) |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 403 | |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 404 | # Setup supported operators and restriction checkers class |
Jonas Ohlsson | 45e653d | 2021-07-26 16:13:12 +0200 | [diff] [blame] | 405 | self.tflite_supported_operators = TFLiteSupportedOperators() |
Patrik Gustavsson | 8f1f9aa | 2021-06-28 07:41:58 +0200 | [diff] [blame] | 406 | self.tosa_supported_operators = TosaSupportedOperators() |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 407 | |
Louis Verhaard | 0b8268a | 2020-08-05 16:11:29 +0200 | [diff] [blame] | 408 | # Returns available number of SHRAM banks depending on activation lookup table |
| 409 | # being used or not |
| 410 | def available_shram_banks(self, uses_activation_lut): |
| 411 | banks = self.shram_total_banks |
| 412 | if uses_activation_lut and self.shram_reserved_unused_banks == 0: |
| 413 | banks -= 2 |
| 414 | return banks |
| 415 | |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 416 | # Calculate block configuration for ALL known IFM operations and |
| 417 | # accumulator sizes. Consumers will need to select their preferred |
| 418 | # operation and bit-width at read-time. |
| 419 | def generate_block_config(self, width, height, depth): |
Louis Verhaard | f98c674 | 2020-05-12 14:22:38 +0200 | [diff] [blame] | 420 | # Number of bytes required for any SHRAM element for a FM of given dimensions. |
| 421 | # For IFM: size = H*W*Align(D*BYTE_WIDTH, 8) |
| 422 | # For ACC: size = H*W*Align(D,8)*BYTE_WIDTH |
| 423 | d1 = round_up(depth, SHRAMElements.PreAlign) |
| 424 | d2 = round_up(d1 * SHRAMElements.ByteSizes, SHRAMElements.PostAlign) |
| 425 | size_bytes = (height * width) * d2 |
| 426 | |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 427 | # Convert byte size (rounded) to size in banks |
| 428 | size_banks = round_up_divide(size_bytes, self.shram_bank_size) |
| 429 | size_banks *= 2 # Double buffer the IFM/Acc (need twice as many banks) |
| 430 | # Round bank requirement to bank granularity |
| 431 | required_banks = round_up(size_banks, self.shram_bank_granules) |
| 432 | return SHRAMBlockConfig(size_bytes, required_banks) |
| 433 | |
Diqing Zhong | e8887a3 | 2020-09-24 09:53:48 +0200 | [diff] [blame] | 434 | def _generate_output_perf_tables(self, accel_config): |
| 435 | if accel_config == Accelerator.Ethos_U55_32: |
| 436 | self.output_cycles_per_elem = (2.0, 3.0, 3.0, 3.0, 4.0, 6.0, 1.0, 2.0) |
| 437 | self.activation_cycles_per_elem = (1.0, 1.0, 0.0) |
| 438 | elif accel_config == Accelerator.Ethos_U55_64: |
| 439 | self.output_cycles_per_elem = (1.0, 1.5, 1.5, 1.5, 2.0, 3.0, 0.5, 1.0) |
| 440 | self.activation_cycles_per_elem = (1.0, 1.0, 0.0) |
| 441 | elif accel_config == Accelerator.Ethos_U55_128: |
| 442 | self.output_cycles_per_elem = (0.75, 1.25, 0.75, 0.75, 1.0, 1.5, 0.25, 0.5) |
| 443 | self.activation_cycles_per_elem = (1.0, 0.5, 0.0) |
Tim Hall | c8a7386 | 2020-10-27 12:43:14 +0000 | [diff] [blame] | 444 | elif accel_config in (Accelerator.Ethos_U55_256, Accelerator.Ethos_U65_256): |
Diqing Zhong | e8887a3 | 2020-09-24 09:53:48 +0200 | [diff] [blame] | 445 | self.output_cycles_per_elem = (0.625, 1.125, 0.5, 0.375, 0.5, 0.75, 0.125, 0.25) |
| 446 | self.activation_cycles_per_elem = (1.0, 0.25, 0.0) |
| 447 | else: |
Tim Hall | c8a7386 | 2020-10-27 12:43:14 +0000 | [diff] [blame] | 448 | assert accel_config == Accelerator.Ethos_U65_512 |
Diqing Zhong | e8887a3 | 2020-09-24 09:53:48 +0200 | [diff] [blame] | 449 | self.output_cycles_per_elem = (0.3125, 0.5625, 0.25, 0.1875, 0.25, 0.375, 0.0625, 0.125) |
| 450 | self.activation_cycles_per_elem = (0.5, 0.125, 0.0) |
| 451 | |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 452 | def calc_ifm_block_depth(self, ifm_depth, ifm_bits): |
Fredrik Svedberg | a0c3624 | 2020-06-03 15:43:31 +0200 | [diff] [blame] | 453 | assert ifm_bits in (8, 16, 32) |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 454 | assert ifm_depth > 0 |
| 455 | ifm_depth = round_up(ifm_depth, self.ifm_ublock.depth) |
Fredrik Svedberg | a0c3624 | 2020-06-03 15:43:31 +0200 | [diff] [blame] | 456 | max_block_depth = 8 * 32 // ifm_bits |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 457 | return min(max_block_depth, ifm_depth) |
| 458 | |
| 459 | # Calculate the size of the IFM block given a depth, target OFM block and a kernel |
Tim Hall | c30f495 | 2020-06-15 20:47:35 +0100 | [diff] [blame] | 460 | def get_ifm_block_size( |
| 461 | self, |
| 462 | ifm_block_depth, |
| 463 | ofm_block: Block, |
| 464 | kernel: Kernel, |
| 465 | subkernel: Block = Block(8, 8, 65536), |
| 466 | ifm_resampling_mode=resampling_mode.NONE, |
| 467 | ): |
Dwight Lidman | a9390f7 | 2020-05-13 12:00:08 +0200 | [diff] [blame] | 468 | upscaling = 1 if ifm_resampling_mode == resampling_mode.NONE else 2 |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 469 | |
erik.andersson@arm.com | 1d6d5c4 | 2021-04-14 13:31:05 +0200 | [diff] [blame] | 470 | # Height |
| 471 | dilated_kernel_height = ((kernel.height - 1) * kernel.dilation.y) + 1 |
| 472 | ifm_block_height = round_up_to_int( |
| 473 | ((ofm_block.height - 1) * kernel.stride.y + min(subkernel.height, dilated_kernel_height)) / upscaling |
| 474 | ) |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 475 | |
Dwight Lidman | 2f75457 | 2021-04-21 12:00:37 +0200 | [diff] [blame] | 476 | ifm_block_height = round_up(ifm_block_height, self.ifm_ublock.height) |
| 477 | |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 478 | # Width |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 479 | dilated_kernel_width = ((kernel.width - 1) * kernel.dilation.x) + 1 |
erik.andersson@arm.com | 1d6d5c4 | 2021-04-14 13:31:05 +0200 | [diff] [blame] | 480 | ifm_block_width = round_up_to_int( |
| 481 | ((ofm_block.width - 1) * kernel.stride.x + min(subkernel.width, dilated_kernel_width)) / upscaling |
| 482 | ) |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 483 | |
Dwight Lidman | 2f75457 | 2021-04-21 12:00:37 +0200 | [diff] [blame] | 484 | ifm_block_width = round_up(ifm_block_width, self.ifm_ublock.width) |
| 485 | |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 486 | return Block(ifm_block_width, ifm_block_height, ifm_block_depth) |
| 487 | |
Tim Hall | 1bd531d | 2020-11-01 20:59:36 +0000 | [diff] [blame] | 488 | def is_spilling_enabled(self): |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 489 | """ |
Tim Hall | 1bd531d | 2020-11-01 20:59:36 +0000 | [diff] [blame] | 490 | Spilling is a feature that allows the Ethos-U to use a dedicated SRAM as a cache for various types of data |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 491 | """ |
Tim Hall | 1bd531d | 2020-11-01 20:59:36 +0000 | [diff] [blame] | 492 | return ( |
| 493 | self._mem_port_mapping(self.cache_mem_area) == MemArea.Sram and self.cache_mem_area != self.arena_mem_area |
| 494 | ) |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 495 | |
Louis Verhaard | 024c355 | 2021-03-17 14:26:34 +0100 | [diff] [blame] | 496 | def mem_type_size(self, mem_type: MemType) -> int: |
patrik.gustavsson | 6f23da6 | 2021-08-19 11:51:45 +0000 | [diff] [blame] | 497 | """Returns size in bytes available for the given memory type. This is a hard limit.""" |
| 498 | if mem_type == MemType.Scratch_fast and self.is_spilling_enabled(): |
| 499 | # when accessing the scratch fast memory type with memory spilling enabled the arena_cache_size refers to |
| 500 | # the cache memory area which is a hard limit |
Tim Hall | d8339a7 | 2021-05-27 18:49:40 +0100 | [diff] [blame] | 501 | return self.arena_cache_size |
Tim Hall | 53c6245 | 2021-08-06 13:51:34 +0100 | [diff] [blame] | 502 | else: |
patrik.gustavsson | 6f23da6 | 2021-08-19 11:51:45 +0000 | [diff] [blame] | 503 | # for all other memory types and modes the hard limit is the maximum possible address offset |
Tim Hall | 53c6245 | 2021-08-06 13:51:34 +0100 | [diff] [blame] | 504 | return self.max_address_offset |
Louis Verhaard | 024c355 | 2021-03-17 14:26:34 +0100 | [diff] [blame] | 505 | |
Tim Hall | 1bd531d | 2020-11-01 20:59:36 +0000 | [diff] [blame] | 506 | def _mem_port_mapping(self, mem_port): |
| 507 | mem_port_mapping = {MemPort.Axi0: self.axi0_port, MemPort.Axi1: self.axi1_port} |
| 508 | return mem_port_mapping[mem_port] |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 509 | |
Tim Hall | 1bd531d | 2020-11-01 20:59:36 +0000 | [diff] [blame] | 510 | def _set_default_sys_config(self): |
Tim Hall | 1bd531d | 2020-11-01 20:59:36 +0000 | [diff] [blame] | 511 | # ArchitectureFeatures.DEFAULT_CONFIG values |
| 512 | if self.is_ethos_u65_system: |
| 513 | # Default Ethos-U65 system configuration |
| 514 | # Ethos-U65 Client-Server: SRAM (16 GB/s) and DRAM (12 GB/s) |
| 515 | self.core_clock = 1e9 |
| 516 | self.axi0_port = MemArea.Sram |
| 517 | self.axi1_port = MemArea.Dram |
| 518 | self.memory_clock_scales[MemArea.Sram] = 1.0 |
| 519 | self.memory_clock_scales[MemArea.Dram] = 0.75 # 3 / 4 |
Diqing Zhong | f842b69 | 2020-12-11 13:07:37 +0100 | [diff] [blame] | 520 | self.memory_burst_length[MemArea.Sram] = 32 |
| 521 | self.memory_burst_length[MemArea.Dram] = 128 |
| 522 | self.memory_latency[MemArea.Sram][BandwidthDirection.Read] = 32 |
| 523 | self.memory_latency[MemArea.Sram][BandwidthDirection.Write] = 32 |
| 524 | self.memory_latency[MemArea.Dram][BandwidthDirection.Read] = 500 |
| 525 | self.memory_latency[MemArea.Dram][BandwidthDirection.Write] = 250 |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 526 | else: |
Tim Hall | 1bd531d | 2020-11-01 20:59:36 +0000 | [diff] [blame] | 527 | # Default Ethos-U55 system configuration |
| 528 | # Ethos-U55 High-End Embedded: SRAM (4 GB/s) and Flash (0.5 GB/s) |
| 529 | self.core_clock = 500e6 |
| 530 | self.axi0_port = MemArea.Sram |
| 531 | self.axi1_port = MemArea.OffChipFlash |
| 532 | self.memory_clock_scales[MemArea.Sram] = 1.0 |
| 533 | self.memory_clock_scales[MemArea.OffChipFlash] = 0.125 # 1 / 8 |
Diqing Zhong | f842b69 | 2020-12-11 13:07:37 +0100 | [diff] [blame] | 534 | self.memory_burst_length[MemArea.Sram] = 32 |
| 535 | self.memory_burst_length[MemArea.OffChipFlash] = 128 |
| 536 | self.memory_latency[MemArea.Sram][BandwidthDirection.Read] = 32 |
| 537 | self.memory_latency[MemArea.Sram][BandwidthDirection.Write] = 32 |
| 538 | self.memory_latency[MemArea.OffChipFlash][BandwidthDirection.Read] = 64 |
| 539 | self.memory_latency[MemArea.OffChipFlash][BandwidthDirection.Write] = 64 |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 540 | |
Tim Hall | 1bd531d | 2020-11-01 20:59:36 +0000 | [diff] [blame] | 541 | def _set_default_mem_mode(self): |
Tim Hall | 1bd531d | 2020-11-01 20:59:36 +0000 | [diff] [blame] | 542 | # ArchitectureFeatures.DEFAULT_CONFIG values |
| 543 | if self.is_ethos_u65_system: |
| 544 | # Default Ethos-U65 memory mode |
Tim Hall | 70b71a5 | 2020-12-22 11:47:54 +0000 | [diff] [blame] | 545 | # Dedicated SRAM: the SRAM is only for use by the Ethos-U |
| 546 | # The non-SRAM memory is assumed to be read-writeable |
Tim Hall | 1bd531d | 2020-11-01 20:59:36 +0000 | [diff] [blame] | 547 | self.const_mem_area = MemPort.Axi1 |
| 548 | self.arena_mem_area = MemPort.Axi1 |
| 549 | self.cache_mem_area = MemPort.Axi0 |
Tim Hall | d8339a7 | 2021-05-27 18:49:40 +0100 | [diff] [blame] | 550 | self.arena_cache_size = 384 * 1024 |
Tim Hall | 1bd531d | 2020-11-01 20:59:36 +0000 | [diff] [blame] | 551 | else: |
Tim Hall | 70b71a5 | 2020-12-22 11:47:54 +0000 | [diff] [blame] | 552 | # Default Ethos-U55 memory mode |
| 553 | # Shared SRAM: the SRAM is shared between the Ethos-U and the Cortex-M software |
| 554 | # The non-SRAM memory is assumed to be read-only |
Tim Hall | 1bd531d | 2020-11-01 20:59:36 +0000 | [diff] [blame] | 555 | self.const_mem_area = MemPort.Axi1 |
| 556 | self.arena_mem_area = MemPort.Axi0 |
| 557 | self.cache_mem_area = MemPort.Axi0 |
Tim Hall | d8339a7 | 2021-05-27 18:49:40 +0100 | [diff] [blame] | 558 | self.arena_cache_size = self.max_address_offset |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 559 | |
Tim Hall | d8339a7 | 2021-05-27 18:49:40 +0100 | [diff] [blame] | 560 | def _get_vela_config(self, vela_config_files, verbose_config, arena_cache_size_from_cli): |
Tim Hall | 1bd531d | 2020-11-01 20:59:36 +0000 | [diff] [blame] | 561 | """ |
| 562 | Gets the system configuration and memory modes from one or more Vela configuration file(s) or uses some |
| 563 | defaults. |
| 564 | """ |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 565 | |
Tim Hall | 1bd531d | 2020-11-01 20:59:36 +0000 | [diff] [blame] | 566 | # all properties are optional and are initialised to a value of 1 (or the equivalent) |
| 567 | self.core_clock = 1 |
| 568 | self.axi0_port = MemArea(1) |
| 569 | self.axi1_port = MemArea(1) |
| 570 | self.memory_clock_scales = np.ones(MemArea.Size) |
Rickard Bolin | 5fdcf17 | 2022-12-19 12:56:17 +0000 | [diff] [blame] | 571 | self.memory_burst_length = np.ones(MemArea.Size, int) |
| 572 | self.memory_latency = np.zeros((MemArea.Size, BandwidthDirection.Size), int) |
Tim Hall | 1bd531d | 2020-11-01 20:59:36 +0000 | [diff] [blame] | 573 | self.const_mem_area = MemPort(1) |
| 574 | self.arena_mem_area = MemPort(1) |
| 575 | self.cache_mem_area = MemPort(1) |
Tim Hall | d8339a7 | 2021-05-27 18:49:40 +0100 | [diff] [blame] | 576 | self.arena_cache_size = self.max_address_offset |
| 577 | arena_cache_size_loc_text = "Default" |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 578 | |
Tim Hall | 1bd531d | 2020-11-01 20:59:36 +0000 | [diff] [blame] | 579 | # read configuration file(s) |
| 580 | self.vela_config = None |
| 581 | |
| 582 | if vela_config_files is not None: |
| 583 | self.vela_config = ConfigParser() |
| 584 | self.vela_config.read(vela_config_files) |
| 585 | |
| 586 | # read system configuration |
| 587 | sys_cfg_section = "System_Config." + self.system_config |
| 588 | |
| 589 | if self.vela_config is not None and self.vela_config.has_section(sys_cfg_section): |
| 590 | self.core_clock = float(self._read_config(sys_cfg_section, "core_clock", self.core_clock)) |
| 591 | self.axi0_port = MemArea[self._read_config(sys_cfg_section, "axi0_port", self.axi0_port)] |
| 592 | self.axi1_port = MemArea[self._read_config(sys_cfg_section, "axi1_port", self.axi1_port)] |
| 593 | |
| 594 | for mem_area in (self.axi0_port, self.axi1_port): |
| 595 | self.memory_clock_scales[mem_area] = float( |
| 596 | self._read_config( |
| 597 | sys_cfg_section, mem_area.name + "_clock_scale", self.memory_clock_scales[mem_area] |
| 598 | ) |
| 599 | ) |
Diqing Zhong | f842b69 | 2020-12-11 13:07:37 +0100 | [diff] [blame] | 600 | self.memory_burst_length[mem_area] = int( |
| 601 | self._read_config( |
| 602 | sys_cfg_section, mem_area.name + "_burst_length", self.memory_burst_length[mem_area] |
| 603 | ) |
| 604 | ) |
| 605 | self.memory_latency[mem_area][BandwidthDirection.Read] = int( |
| 606 | self._read_config( |
| 607 | sys_cfg_section, |
| 608 | mem_area.name + "_read_latency", |
| 609 | self.memory_latency[mem_area][BandwidthDirection.Read], |
| 610 | ) |
| 611 | ) |
| 612 | self.memory_latency[mem_area][BandwidthDirection.Write] = int( |
| 613 | self._read_config( |
| 614 | sys_cfg_section, |
| 615 | mem_area.name + "_write_latency", |
| 616 | self.memory_latency[mem_area][BandwidthDirection.Write], |
| 617 | ) |
| 618 | ) |
Tim Hall | 1bd531d | 2020-11-01 20:59:36 +0000 | [diff] [blame] | 619 | elif self.system_config == ArchitectureFeatures.DEFAULT_CONFIG: |
| 620 | self._set_default_sys_config() |
| 621 | |
| 622 | elif vela_config_files is None: |
Michael McGeagh | 7a6f843 | 2020-12-02 15:29:22 +0000 | [diff] [blame] | 623 | raise CliOptionError("--config", vela_config_files, "Vela config file not specified") |
Tim Hall | 1bd531d | 2020-11-01 20:59:36 +0000 | [diff] [blame] | 624 | |
| 625 | else: |
| 626 | raise CliOptionError( |
Jonas Ohlsson | d857507 | 2022-03-30 10:30:25 +0200 | [diff] [blame] | 627 | "--system-config", |
| 628 | self.system_config, |
| 629 | f"Section {sys_cfg_section} not found in Vela config file", |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 630 | ) |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 631 | |
Tim Hall | 1bd531d | 2020-11-01 20:59:36 +0000 | [diff] [blame] | 632 | # read the memory mode |
| 633 | mem_mode_section = "Memory_Mode." + self.memory_mode |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 634 | |
Tim Hall | 1bd531d | 2020-11-01 20:59:36 +0000 | [diff] [blame] | 635 | if self.vela_config is not None and self.vela_config.has_section(mem_mode_section): |
| 636 | self.const_mem_area = MemPort[ |
| 637 | self._read_config(mem_mode_section, "const_mem_area", self.const_mem_area.name) |
| 638 | ] |
| 639 | self.arena_mem_area = MemPort[ |
| 640 | self._read_config(mem_mode_section, "arena_mem_area", self.arena_mem_area.name) |
| 641 | ] |
| 642 | self.cache_mem_area = MemPort[ |
| 643 | self._read_config(mem_mode_section, "cache_mem_area", self.cache_mem_area.name) |
| 644 | ] |
Tim Hall | d8339a7 | 2021-05-27 18:49:40 +0100 | [diff] [blame] | 645 | found = [] |
| 646 | self.arena_cache_size = int( |
| 647 | self._read_config(mem_mode_section, "arena_cache_size", self.arena_cache_size, found) |
| 648 | ) |
| 649 | if found[-1]: |
| 650 | arena_cache_size_loc_text = "Configuration file" |
Patrik Gustavsson | eca2e95 | 2020-05-27 09:15:11 +0200 | [diff] [blame] | 651 | |
Tim Hall | 1bd531d | 2020-11-01 20:59:36 +0000 | [diff] [blame] | 652 | elif self.memory_mode == ArchitectureFeatures.DEFAULT_CONFIG: |
| 653 | self._set_default_mem_mode() |
Patrik Gustavsson | 5f47c05 | 2020-06-25 12:56:04 +0200 | [diff] [blame] | 654 | |
Tim Hall | 1bd531d | 2020-11-01 20:59:36 +0000 | [diff] [blame] | 655 | elif vela_config_files is None: |
Michael McGeagh | 7a6f843 | 2020-12-02 15:29:22 +0000 | [diff] [blame] | 656 | raise CliOptionError("--config", vela_config_files, "Vela config file not specified") |
Patrik Gustavsson | eca2e95 | 2020-05-27 09:15:11 +0200 | [diff] [blame] | 657 | |
Tim Hall | 1bd531d | 2020-11-01 20:59:36 +0000 | [diff] [blame] | 658 | else: |
| 659 | raise CliOptionError( |
Jonas Ohlsson | d857507 | 2022-03-30 10:30:25 +0200 | [diff] [blame] | 660 | "--memory-mode", |
| 661 | self.memory_mode, |
| 662 | f"Section {mem_mode_section} not found in Vela config file", |
Tim Hall | 1bd531d | 2020-11-01 20:59:36 +0000 | [diff] [blame] | 663 | ) |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 664 | |
Tim Hall | 1bd531d | 2020-11-01 20:59:36 +0000 | [diff] [blame] | 665 | # override sram to onchipflash |
| 666 | if self._mem_port_mapping(self.const_mem_area) == MemArea.Sram: |
| 667 | if self.const_mem_area == self.arena_mem_area == self.cache_mem_area: |
| 668 | print( |
| 669 | "Info: Changing const_mem_area from Sram to OnChipFlash. This will use the same characteristics as" |
| 670 | " Sram." |
| 671 | ) |
| 672 | if self.const_mem_area == MemPort.Axi0: |
| 673 | self.const_mem_area = MemPort.Axi1 |
| 674 | self.axi1_port = MemArea.OnChipFlash |
| 675 | else: |
| 676 | self.const_mem_area = MemPort.Axi0 |
| 677 | self.axi0_port = MemArea.OnChipFlash |
| 678 | self.memory_clock_scales[MemArea.OnChipFlash] = self.memory_clock_scales[MemArea.Sram] |
Diqing Zhong | f842b69 | 2020-12-11 13:07:37 +0100 | [diff] [blame] | 679 | self.memory_burst_length[MemArea.OnChipFlash] = self.memory_burst_length[MemArea.Sram] |
| 680 | self.memory_latency[MemArea.OnChipFlash] = self.memory_latency[MemArea.Sram] |
Tim Hall | 1bd531d | 2020-11-01 20:59:36 +0000 | [diff] [blame] | 681 | |
Tim Hall | d8339a7 | 2021-05-27 18:49:40 +0100 | [diff] [blame] | 682 | # override sram usage |
| 683 | if arena_cache_size_from_cli is not None: |
| 684 | self.arena_cache_size = arena_cache_size_from_cli |
| 685 | arena_cache_size_loc_text = "CLI option" |
| 686 | |
Tim Hall | 1bd531d | 2020-11-01 20:59:36 +0000 | [diff] [blame] | 687 | # check configuration |
Tim Hall | 70b71a5 | 2020-12-22 11:47:54 +0000 | [diff] [blame] | 688 | if self._mem_port_mapping(self.const_mem_area) not in ( |
| 689 | MemArea.Dram, |
| 690 | MemArea.OnChipFlash, |
| 691 | MemArea.OffChipFlash, |
| 692 | ): |
| 693 | raise ConfigOptionError( |
| 694 | "const_mem_area", |
| 695 | self._mem_port_mapping(self.const_mem_area).name, |
| 696 | "Dram or OnChipFlash or OffChipFlash", |
| 697 | ) |
| 698 | |
| 699 | if self._mem_port_mapping(self.arena_mem_area) not in (MemArea.Sram, MemArea.Dram): |
| 700 | raise ConfigOptionError("arena_mem_area", self._mem_port_mapping(self.arena_mem_area).name, "Sram or Dram") |
| 701 | |
Tim Hall | 1bd531d | 2020-11-01 20:59:36 +0000 | [diff] [blame] | 702 | if self._mem_port_mapping(self.cache_mem_area) != MemArea.Sram: |
| 703 | raise ConfigOptionError("cache_mem_area", self._mem_port_mapping(self.cache_mem_area).name, "Sram") |
| 704 | |
Tim Hall | d8339a7 | 2021-05-27 18:49:40 +0100 | [diff] [blame] | 705 | if self.arena_cache_size < 0: |
| 706 | raise ConfigOptionError("arena_cache_size", self.arena_cache_size, ">= 0") |
| 707 | if self.arena_cache_size > self.max_address_offset: |
| 708 | raise ConfigOptionError( |
| 709 | "arena_cache_size", |
| 710 | f"{self.arena_cache_size}. Size is out of bounds, maximum is: {self.max_address_offset}", |
| 711 | ) |
| 712 | |
Tim Hall | 1bd531d | 2020-11-01 20:59:36 +0000 | [diff] [blame] | 713 | # assign existing memory areas |
| 714 | self.permanent_storage_mem_area = self._mem_port_mapping(self.const_mem_area) |
| 715 | self.feature_map_storage_mem_area = self._mem_port_mapping(self.arena_mem_area) |
| 716 | self.fast_storage_mem_area = self._mem_port_mapping(self.cache_mem_area) |
| 717 | |
Tim Hall | 1bd531d | 2020-11-01 20:59:36 +0000 | [diff] [blame] | 718 | # display the system configuration and memory mode |
| 719 | if verbose_config: |
Rickard Bolin | 7ce6b32 | 2022-06-02 09:30:33 +0000 | [diff] [blame] | 720 | print("Configuration files:") |
| 721 | print(f" {vela_config_files}") |
Tim Hall | 1bd531d | 2020-11-01 20:59:36 +0000 | [diff] [blame] | 722 | print(f"System Configuration ({self.system_config}):") |
| 723 | print(f" core_clock = {self.core_clock}") |
| 724 | print(f" axi0_port = {self.axi0_port.name}") |
| 725 | print(f" axi1_port = {self.axi1_port.name}") |
| 726 | for mem in (MemArea.Sram, MemArea.Dram, MemArea.OnChipFlash, MemArea.OffChipFlash): |
| 727 | print(f" {mem.name}_clock_scales = {self.memory_clock_scales[mem]}") |
Diqing Zhong | f842b69 | 2020-12-11 13:07:37 +0100 | [diff] [blame] | 728 | print(f" {mem.name}_burst_length = {self.memory_burst_length[mem]}") |
| 729 | print(f" {mem.name}_read_latency = {self.memory_latency[mem][BandwidthDirection.Read]}") |
| 730 | print(f" {mem.name}_write_latency = {self.memory_latency[mem][BandwidthDirection.Write]}") |
Tim Hall | 1bd531d | 2020-11-01 20:59:36 +0000 | [diff] [blame] | 731 | |
| 732 | print(f"Memory Mode ({self.memory_mode}):") |
| 733 | print(f" const_mem_area = {self.const_mem_area.name}") |
| 734 | print(f" arena_mem_area = {self.arena_mem_area.name}") |
| 735 | print(f" cache_mem_area = {self.cache_mem_area.name}") |
Tim Hall | d8339a7 | 2021-05-27 18:49:40 +0100 | [diff] [blame] | 736 | print(f" arena_cache_size = {self.arena_cache_size} from {arena_cache_size_loc_text}") |
Tim Hall | 1bd531d | 2020-11-01 20:59:36 +0000 | [diff] [blame] | 737 | |
| 738 | print("Architecture Settings:") |
| 739 | print(f" permanent_storage_mem_area = {self.permanent_storage_mem_area.name}") |
| 740 | print(f" feature_map_storage_mem_area = {self.feature_map_storage_mem_area.name}") |
| 741 | print(f" fast_storage_mem_area = {self.fast_storage_mem_area.name}") |
Tim Hall | 1bd531d | 2020-11-01 20:59:36 +0000 | [diff] [blame] | 742 | |
Tim Hall | d8339a7 | 2021-05-27 18:49:40 +0100 | [diff] [blame] | 743 | def _read_config(self, section, key, current_value, found=None): |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 744 | """ |
Tim Hall | 1bd531d | 2020-11-01 20:59:36 +0000 | [diff] [blame] | 745 | Reads a given key from a particular section in the Vela config file. If the section contains the 'inherit' |
| 746 | option then we recurse into the section specified. If inherited sections result in multiple keys for a |
Tim Hall | d8339a7 | 2021-05-27 18:49:40 +0100 | [diff] [blame] | 747 | particular option then the key from the parent section is used, regardless of the parsing order. if specified |
| 748 | found should be an empty list that this function will append a True or False to the end of the list indicating |
| 749 | whether the key was found or not. |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 750 | """ |
Tim Hall | 1bd531d | 2020-11-01 20:59:36 +0000 | [diff] [blame] | 751 | if not self.vela_config.has_section(section): |
Michael McGeagh | 7a6f843 | 2020-12-02 15:29:22 +0000 | [diff] [blame] | 752 | raise ConfigOptionError("section", f"{section}. The section was not found in the Vela config file(s)") |
Tim Hall | 1bd531d | 2020-11-01 20:59:36 +0000 | [diff] [blame] | 753 | |
Tim Hall | d8339a7 | 2021-05-27 18:49:40 +0100 | [diff] [blame] | 754 | result = str(current_value) if current_value is not None else None |
| 755 | if found is not None: |
| 756 | found.append(False) |
| 757 | |
Tim Hall | 1bd531d | 2020-11-01 20:59:36 +0000 | [diff] [blame] | 758 | if self.vela_config.has_option(section, "inherit"): |
| 759 | inheritance_section = self.vela_config.get(section, "inherit") |
| 760 | # check for recursion loop |
| 761 | if inheritance_section == section: |
| 762 | raise ConfigOptionError( |
Jonas Ohlsson | d857507 | 2022-03-30 10:30:25 +0200 | [diff] [blame] | 763 | "inherit", |
| 764 | f"{inheritance_section}. This references its own section and recursion is not allowed", |
Tim Hall | 1bd531d | 2020-11-01 20:59:36 +0000 | [diff] [blame] | 765 | ) |
Tim Hall | d8339a7 | 2021-05-27 18:49:40 +0100 | [diff] [blame] | 766 | result = self._read_config(inheritance_section, key, result, found) |
Tim Hall | 1bd531d | 2020-11-01 20:59:36 +0000 | [diff] [blame] | 767 | |
| 768 | if self.vela_config.has_option(section, key): |
| 769 | result = self.vela_config.get(section, key) |
Tim Hall | d8339a7 | 2021-05-27 18:49:40 +0100 | [diff] [blame] | 770 | if found is not None: |
| 771 | found.append(True) |
Tim Hall | 1bd531d | 2020-11-01 20:59:36 +0000 | [diff] [blame] | 772 | |
Tim Hall | 79d07d2 | 2020-04-27 18:20:16 +0100 | [diff] [blame] | 773 | return result |
Louis Verhaard | 5207830 | 2020-11-18 13:35:06 +0100 | [diff] [blame] | 774 | |
| 775 | |
Louis Verhaard | 061eeb4 | 2020-11-27 08:24:03 +0100 | [diff] [blame] | 776 | # Cache for default arch instances, as these are expensive to create |
| 777 | default_arch_cache = dict() |
| 778 | |
| 779 | |
Louis Verhaard | 5207830 | 2020-11-18 13:35:06 +0100 | [diff] [blame] | 780 | def create_default_arch(accelerator: Accelerator) -> ArchitectureFeatures: |
| 781 | """Creates architecture features object using default settings""" |
Louis Verhaard | 061eeb4 | 2020-11-27 08:24:03 +0100 | [diff] [blame] | 782 | if accelerator not in default_arch_cache: |
| 783 | default_arch_cache[accelerator] = ArchitectureFeatures( |
| 784 | vela_config_files=None, |
| 785 | accelerator_config=accelerator.value, |
| 786 | system_config=ArchitectureFeatures.DEFAULT_CONFIG, |
| 787 | memory_mode=ArchitectureFeatures.DEFAULT_CONFIG, |
Louis Verhaard | 061eeb4 | 2020-11-27 08:24:03 +0100 | [diff] [blame] | 788 | max_blockdep=ArchitectureFeatures.MAX_BLOCKDEP, |
Louis Verhaard | 061eeb4 | 2020-11-27 08:24:03 +0100 | [diff] [blame] | 789 | verbose_config=False, |
Tim Hall | d8339a7 | 2021-05-27 18:49:40 +0100 | [diff] [blame] | 790 | arena_cache_size=None, |
Louis Verhaard | 061eeb4 | 2020-11-27 08:24:03 +0100 | [diff] [blame] | 791 | ) |
| 792 | return default_arch_cache[accelerator] |