diff --git a/CMakeLists.txt b/CMakeLists.txt
index 7453176..1b60396 100644
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@@ -85,7 +85,7 @@
 endif()
 
 project(arm_ml_embedded_evaluation_kit
-        VERSION     22.05.0
+        VERSION     22.08.0
         DESCRIPTION "ARM ML Embedded Evaluation Kit"
         LANGUAGES   C CXX ASM)
 
diff --git a/Readme.md b/Readme.md
index fd3a67c..685b004 100644
--- a/Readme.md
+++ b/Readme.md
@@ -7,10 +7,10 @@
 
 - an [MPS3 board](https://developer.arm.com/tools-and-software/development-boards/fpga-prototyping-boards/mps3) with
   [Arm® Corstone-300](https://developer.arm.com/Processors/Corstone-300) or [Arm® Corstone-310](https://developer.arm.com/Processors/Corstone-310) implementations.
-  - Arm® Corstone-300 runs a combination of
+  - Arm® Corstone™-300 runs a combination of
   the [Arm® Cortex™-M55 processor](https://www.arm.com/products/silicon-ip-cpu/cortex-m/cortex-m55) and the
   [Arm® Ethos™-U55 NPU](https://www.arm.com/products/silicon-ip-cpu/ethos/ethos-u55).
-  - Arm® Corstone-310 runs a combination of
+  - Arm® Corstone™-310 runs a combination of
       the [Arm® Cortex™-M85 processor](https://www.arm.com/products/silicon-ip-cpu/cortex-m/cortex-m85) and the
       [Arm® Ethos™-U55 NPU](https://www.arm.com/products/silicon-ip-cpu/ethos/ethos-u55).
 
@@ -19,7 +19,9 @@
   or [Arm® Ethos™-U65 NPU](https://www.arm.com/products/silicon-ip-cpu/ethos/ethos-u65) software fast model in combination of
   the new [Arm® Cortex™-M55 processor](https://www.arm.com/products/silicon-ip-cpu/cortex-m/cortex-m55). You can also take advantage of
   [Arm Virtual Hardware](https://www.arm.com/products/development-tools/simulation/virtual-hardware) (AVH) and [run the Fixed Virtual Platform
-  in the cloud](./docs/sections/arm_virtual_hardware.md). An FVP implementation of Arm® Corstone-310 is also available via AVH.
+  in the cloud](./docs/sections/arm_virtual_hardware.md).
+  > **NOTE**: While Arm® Corstone™-300 is available as an [Ecosystem FVP](https://developer.arm.com/tools-and-software/open-source-software/arm-platforms-software/arm-ecosystem-fvps)
+  > and AVH, Arm® Corstone™-310 is available (for both Arm® Ethos™-U55 and Ethos™-U55 NPUs) only as AVH implementations.
 
 ## Overview of the evaluation kit
 
@@ -68,7 +70,7 @@
 and delegates execution of certain operators to the NPU or, if the neural network model operators are not supported on
 NPU, to the CPU. If the operator is supported, [CMSIS-NN](https://github.com/ARM-software/CMSIS_5) is used to optimise
 CPU workload execution with int8 data type. Else, TensorFlow™ Lite for Microcontrollers' reference kernels are used as
-a final fall-back. 
+a final fall-back.
 Common ML application functions will help you to focus on implementing logic of your custom ML use case: you can modify
 only the use case code and leave all other components unchanged. Supplied build system will discover new ML application
 code and automatically include it into compilation flow.
diff --git a/docs/sections/arm_virtual_hardware.md b/docs/sections/arm_virtual_hardware.md
index 01c4c99..7982b73 100644
--- a/docs/sections/arm_virtual_hardware.md
+++ b/docs/sections/arm_virtual_hardware.md
@@ -6,11 +6,12 @@
 
 ## Overview
 
-Arm® Virtual Hardware is an accurate representation of a physical System on Chip and runs as a simple application in a
-Linux environment for easy scalability in the cloud and removes dependency from silicon availability.
-Powered by Amazon Web Services (AWS), developers can launch Amazon Machine Image
-(AMI) running as a virtual server in the cloud. The Arm Virtual Hardware is configured with the Corstone™-300 MPS3
-based Fixed Virtual Platform (FVP), compiler and other tools.
+Arm® Virtual Hardware (AVH) is an evolution of Arm’s modelling technology delivering models of Arm-based processors,
+systems, third party hardware for application developers and SoC designers to build and test software before silicon
+and hardware availability. It is an accurate representation of a physical System on Chip and runs as a simple
+application in a Linux environment for easy scalability in the cloud. Powered by Amazon Web Services (AWS), developers
+can launch Amazon Machine Image (AMI) running as a virtual server in the cloud. The Arm Virtual Hardware is configured
+with the Arm® Corstone™-300 and Corstone™-310 MPS3 based Fixed Virtual Platform (FVP), compiler and other tools.
 
 ### Getting started
 
@@ -23,7 +24,7 @@
 
  To access the Arm Virtual Hardware AWS instance via ssh, accept the prompt  to generate a *.pem* key
  while creating the instance or add it later.
- You can then access the AWS instance over ssh: `$ ssh -i <mykey.pem> ubuntu@<ec2-ip-address>`.
+ You can then access the AWS instance over ssh: `$ ssh -i <mykey.pem> ubuntu@<ec2-ip-address>`.
  It may be necessary to change the permissions for mykey.pem with `$ chmod 400 mykey.pem`.
 
 ### Useful Links
@@ -42,3 +43,5 @@
 
 In order to view the FVP window when launching on the AWS instance a VNC is required.
 See relevant section [here](https://aws.amazon.com/premiumsupport/knowledge-center/ec2-linux-2-install-gui/).
+Alternatively, the FVPs can be given certain command line arguments to make them execute without the front-end. See
+[Running the FVP without the UI](./deployment.md#running-the-fvp-without-the-ui).
diff --git a/docs/sections/building.md b/docs/sections/building.md
index f6b71a8..4750e3e 100644
--- a/docs/sections/building.md
+++ b/docs/sections/building.md
@@ -253,6 +253,9 @@
 
 - `ETHOS_U_NPU_TIMING_ADAPTER_ENABLED`: Specifies if the *Ethos-U* timing adapter is enabled.
 
+  > **NOTE**: This setting is set to ON for all platforms if `ETHOS_U_NPU_ENABLED` is set. However, it is overridden
+  > to OFF for Arm® Corstone-310 implementation.
+
 - `TA_CONFIG_FILE`: The path to the CMake configuration file that contains the timing adapter parameters. Used only if
   the timing adapter build is enabled. Default for Ethos-U55 NPU is
   [ta_config_u55_high_end.cmake](../../scripts/timing_adapter/ta_config_u55_high_end.cmake),
diff --git a/docs/sections/timing_adapters.md b/docs/sections/timing_adapters.md
index ab05490..7ca7076 100644
--- a/docs/sections/timing_adapters.md
+++ b/docs/sections/timing_adapters.md
@@ -1,18 +1,23 @@
 # Building timing adapter with custom options
 
 The sources contain the configuration for a timing adapter utility for the *Arm® Ethos™-U* NPU driver. The timing
-adapter allows the platform to simulate user provided memory bandwidth and latency constraints.
+adapter allows the platform to simulate user provided memory bandwidth and latency constraints on platforms that
+support it. The timing adapter driver aims to control the behavior of two AXI buses used by *Ethos-U* NPU. One is for
+SRAM memory region, and the other is for flash or DRAM.
 
-The timing adapter driver aims to control the behavior of two AXI buses used by *Ethos-U* NPU. One is for SRAM memory
-region, and the other is for flash or DRAM.
+The SRAM is where intermediate buffers are expected to be allocated and therefore, this region can serve frequent read
+and write traffic generated by computation operations while executing a neural network inference. The flash or DDR is
+where we expect to store the model weights and therefore, this bus would only usually be used for RO traffic.
 
-The SRAM is where intermediate buffers are expected to be allocated and therefore, this region can serve frequent Read
-and Write traffic generated by computation operations while executing a neural network inference.
+It is used for MPS3 FPGA and for Fast Model environment (or [AVH](./arm_virtual_hardware.md)).
 
-The flash or DDR is where we expect to store the model weights and therefore, this bus would only usually be used for RO
-traffic.
-
-It is used for MPS3 FPGA and for Fast Model environment.
+> **NOTE**: All Arm® Corstone™-300 based platform implementations fully support the use of `timing adapter` to perform
+> bandwidth/latency sweeps for performance estimation of the Arm® Ethos™-U NPUs. However, Arm® Corstone™-310's
+> implementation of timing adapter is, different and, unsuitable for such benchmarking. See
+> [differences between timing adapter implementations](#differences-between-timing-adapter-implementations-in-arm-corstone_300-and-arm-corstone_310) for more details. Therefore, for Arm® Corstone™-310 targets, the
+> CMake configuration is set up to ignore the timing adapters, if any, entirely. If you want to do any NPU performance
+> benchmarking for different bandwidth and latency conditions, we recommend using the Arm® Corstone™-300
+> implementations.
 
 The CMake build framework allows the parameters to control the behavior of each bus with following parameters:
 
@@ -128,7 +133,7 @@
 ```commandline
 cmake .. -DTA_CONFIG_FILE=scripts/cmake/timing_adapter/my_ta_config.cmake
 ```
-## Differences between timing adapter implementations in Arm® Corstone™-300 and Arm® Corstone™-310
+## Differences between timing adapter implementations in Arm Corstone-300 and Arm Corstone-310
 
 Corstone-300 FVP and FPGA implements timing adapters that are tied to AXI masters M0 and M1 on the Ethos-U NPU.
 
diff --git a/release_notes.txt b/release_notes.txt
index f2ab3af..6e09f01 100644
--- a/release_notes.txt
+++ b/release_notes.txt
@@ -1,3 +1,10 @@
+Changes in 22.08
+    * Formal support for Arm® Corstone-310 Arm Virtual Hardware and FPGA implementations.
+    * Added CMake presets.
+    * Bug fix for Arm® Ethos-U65 NPU's default AXI burst length.
+    * Provision to allow platform-agnostic use case API to be packaged as CMSIS pack.
+    * Documentation updates.
+
 Changes in 22.05
     * Support for 22.05 Ethos-U component and dependencies (core-driver, core-platform, Vela 3.4.0, CMSIS, TensorFlow Lite Micro).
     * Restructuring of repository sources to allow generation of CMSIS packs.
diff --git a/scripts/cmake/platforms/mps3/build_configuration.cmake b/scripts/cmake/platforms/mps3/build_configuration.cmake
index 749b1e1..6f91f8c 100644
--- a/scripts/cmake/platforms/mps3/build_configuration.cmake
+++ b/scripts/cmake/platforms/mps3/build_configuration.cmake
@@ -31,8 +31,12 @@
                 CACHE FILEPATH "Toolchain file")
     endif()
 
-    if ((ETHOS_U_NPU_ID STREQUAL U65) AND (TARGET_SUBSYSTEM STREQUAL sse-310))
-        message(FATAL_ERROR "Non compatible Ethos-U NPU processor ${ETHOS_U_NPU_ID} and target subsystem ${TARGET_SUBSYSTEM}")
+    # Arm Corstone-310's timing adapter behaviour is very different to Arm Corstone-300 and cannot
+    # be used for bandwidth/latency related performance sweeps for the Arm Ethos-U NPU. Read
+    # docs/sections/timing_adapters.md for more details.
+    if ((TARGET_SUBSYSTEM STREQUAL sse-310) AND ${ETHOS_U_NPU_TIMING_ADAPTER_ENABLED})
+        message(STATUS "Timing adapter will NOT be used for target subsystem ${TARGET_SUBSYSTEM}")
+        set(ETHOS_U_NPU_TIMING_ADAPTER_ENABLED OFF CACHE BOOL "Use of TA" FORCE)
     endif()
 
     set(LINKER_SCRIPT_NAME "mps3-${TARGET_SUBSYSTEM}" PARENT_SCOPE)
diff --git a/source/hal/source/platform/mps3/CMakeLists.txt b/source/hal/source/platform/mps3/CMakeLists.txt
index 57394f4..c51062f 100644
--- a/source/hal/source/platform/mps3/CMakeLists.txt
+++ b/source/hal/source/platform/mps3/CMakeLists.txt
@@ -59,8 +59,7 @@
     set(ETHOS_U_PRIV_ENABLED "1"            CACHE STRING "Ethos-U NPU Privilege enable")
 
     if (ETHOS_U_NPU_TIMING_ADAPTER_ENABLED)
-        set(TA0_BASE         "0x58103000"   CACHE STRING "Ethos-U NPU timing adapter 0")
-        set(TA1_BASE         "0x58103200"   CACHE STRING "Ethos-U NPU timing adapter 1")
+        message(FATAL_ERROR "Timing adapter support should be disabled for ${TARGET_SUBSYSTEM}")
     endif()
 endif()