diff --git a/source/application/hal/platforms/bare-metal/bsp/bsp-packs/mps3/device_mps3.c b/source/application/hal/platforms/bare-metal/bsp/bsp-packs/mps3/device_mps3.c
index 7040cf3..9a923c7 100644
--- a/source/application/hal/platforms/bare-metal/bsp/bsp-packs/mps3/device_mps3.c
+++ b/source/application/hal/platforms/bare-metal/bsp/bsp-packs/mps3/device_mps3.c
@@ -21,11 +21,16 @@
 
 #include <inttypes.h>
 
+extern uint32_t GetSystemCoreClock(void);
+
 uint32_t GetMPS3CoreClock(void)
 {
-    const uint32_t default_clock = 32000000;
+    const uint32_t default_clock = GetSystemCoreClock();
     static int warned_once = 0;
     if (0 != MPS3_SCC->CFG_ACLK) {
+        if (default_clock != MPS3_SCC->CFG_ACLK) {
+            warn("System clock is different to the MPS3 config set clock.\n");
+        }
         return MPS3_SCC->CFG_ACLK;
     }
 
diff --git a/source/application/hal/platforms/bare-metal/bsp/bsp-packs/mps3/include/device_mps3.h b/source/application/hal/platforms/bare-metal/bsp/bsp-packs/mps3/include/device_mps3.h
index f0bab79..e0dea1b 100644
--- a/source/application/hal/platforms/bare-metal/bsp/bsp-packs/mps3/include/device_mps3.h
+++ b/source/application/hal/platforms/bare-metal/bsp/bsp-packs/mps3/include/device_mps3.h
@@ -26,6 +26,8 @@
 
 #include <stdio.h>
 
+#define PERIF_CLK               (25000000) /* Clock source for APB peripherals */
+
 typedef struct _CMSDK_UART_TypeDef_
 {
     __IO uint32_t  DATA;        /* Offset: 0x000 (R/W) Data Register.    */
diff --git a/source/application/hal/platforms/bare-metal/bsp/bsp-packs/mps3/uart_stdout.c b/source/application/hal/platforms/bare-metal/bsp/bsp-packs/mps3/uart_stdout.c
index 3211c4d..35d4160 100644
--- a/source/application/hal/platforms/bare-metal/bsp/bsp-packs/mps3/uart_stdout.c
+++ b/source/application/hal/platforms/bare-metal/bsp/bsp-packs/mps3/uart_stdout.c
@@ -30,8 +30,7 @@
 
 void UartStdOutInit(void)
 {
-    /* NOTE: SystemCoreClock should have been set before initialising UART. */
-    CMSDK_UART0->BAUDDIV = SystemCoreClock / 115200;   /* => (25 or 32 MHz) / (115200 bps). */
+    CMSDK_UART0->BAUDDIV = PERIF_CLK / 115200;   /* => (25 or 32 MHz) / (115200 bps). */
     CMSDK_UART0->CTRL    = ((1ul <<  0) |              /* TX enable. */
                             (1ul <<  1) );             /* RX enable. */
     return;
diff --git a/source/application/hal/platforms/bare-metal/bsp/cmsis-device/cmsis.c b/source/application/hal/platforms/bare-metal/bsp/cmsis-device/cmsis.c
index b7f318c..9cf6213 100644
--- a/source/application/hal/platforms/bare-metal/bsp/cmsis-device/cmsis.c
+++ b/source/application/hal/platforms/bare-metal/bsp/cmsis-device/cmsis.c
@@ -21,7 +21,7 @@
 /*----------------------------------------------------------------------------*\
  *                        Define clocks (uses OSC1 ACLK)                      *
 \*----------------------------------------------------------------------------*/
-#define __XTAL            (25000000)      /* Oscillator frequency             */
+#define __XTAL            (32000000)      /* Oscillator frequency             */
 #define __SYSTEM_CLOCK    (__XTAL)
 
 #if defined(CPU_CORTEX_M55)