tree d5aa1103a0e8e724415bcda2bb15d60f692a7c45
parent 414b1b9534fcf5d7998035a0de9cf2589a1826c8
author Kshitij Sisodia <kshitij.sisodia@arm.com> 1633354285 +0100
committer Kshitij Sisodia <kshitij.sisodia@arm.com> 1633354285 +0100

MLECO-2407: Correction for Cortex-M55 core clock

AN547 sets the core clock for both M55 and U55 to 32MHz, while the
blocks on APB use a different clock of 25MHz.

Note: this will have not change any of the MPS3 FPGA profiling
numbers (cycle counts and elapsed time in milliseconds) for
Cortex-M55 as this was already using the correct counters under
MPS3. The only difference would be that the system tick interrupt
will fire every 10ms as intended instead of every 7.8125 ms as it
is doing with current software.

Change-Id: I77cd269c7c02f5d6e65328eb285185bae74e4e36