diff --git a/scripts/cmake/bare-metal-sources.cmake b/scripts/cmake/bare-metal-sources.cmake
index d3dad41..3fe9b1b 100644
--- a/scripts/cmake/bare-metal-sources.cmake
+++ b/scripts/cmake/bare-metal-sources.cmake
@@ -39,7 +39,52 @@
 set(ETHOS_U_NPU_FLAG                           "-DARM_NPU=1")
 
 if (ETHOS_U_NPU_ENABLED)
-    set(OPTIONAL_FLAGS      "${OPTIONAL_FLAGS} ${ETHOS_U_NPU_FLAG}")
+
+    USER_OPTION(ETHOS_U_NPU_ID "Arm Ethos-U NPU IP (U55 or U65)"
+        "U55"
+        STRING)
+
+    if ((ETHOS_U_NPU_ID STREQUAL U55) OR (ETHOS_U_NPU_ID STREQUAL U65))
+        if (ETHOS_U_NPU_ID STREQUAL U55)
+            set(DEFAULT_NPU_MEM_MODE    "Shared_Sram")
+            set(DEFAULT_NPU_CONFIG_ID     "H128")
+        elseif(ETHOS_U_NPU_ID STREQUAL U65)
+            set(DEFAULT_NPU_MEM_MODE    "Dedicated_Sram")
+            set(DEFAULT_NPU_CONFIG_ID     "Y256")
+        endif()
+    else ()
+        message(FATAL_ERROR "Non compatible Ethos-U NPU processor ${ETHOS_U_NPU_ID}")
+    endif ()
+
+    USER_OPTION(ETHOS_U_NPU_MEMORY_MODE "Specifies the memory mode used in the Vela command."
+        "${DEFAULT_NPU_MEM_MODE}"
+        STRING)
+
+    if (ETHOS_U_NPU_MEMORY_MODE STREQUAL Sram_Only)
+
+        if (ETHOS_U_NPU_ID STREQUAL U55)
+            set(ETHOS_U_NPU_MEMORY_MODE_FLAG "-DETHOS_U_NPU_MEMORY_MODE=ETHOS_U_NPU_MEM_MODE_SRAM_ONLY")
+        else ()
+            message(FATAL_ERROR "Non compatible Ethos-U NPU memory mode and processor ${ETHOS_U_NPU_MEMORY_MODE} - ${ETHOS_U_NPU_ID}. `sram_only` can be used only for Ethos-U55.")
+        endif ()
+
+    elseif (ETHOS_U_NPU_MEMORY_MODE STREQUAL Shared_Sram)
+        # Shared Sram can be used for Ethos-U55 and Ethos-U65
+        set(ETHOS_U_NPU_MEMORY_MODE_FLAG "-DETHOS_U_NPU_MEMORY_MODE=ETHOS_U_NPU_MEMORY_MODE_SHARED_SRAM")
+
+    elseif (ETHOS_U_NPU_MEMORY_MODE STREQUAL Dedicated_Sram)
+        # Dedicated Sram is used only for Ethos-U65
+        if (ETHOS_U_NPU_ID STREQUAL U65)
+            set(ETHOS_U_NPU_MEMORY_MODE_FLAG  "-DETHOS_U_NPU_MEMORY_MODE=ETHOS_U_NPU_MEMORY_MODE_DEDICATED_SRAM")
+        else ()
+            message(FATAL_ERROR "Non compatible Ethos-U NPU memory mode and processor ${ETHOS_U_NPU_MEMORY_MODE} - ${ETHOS_U_NPU_ID}. `dedicated_sram` can be used only for Ethos-U65.")
+        endif ()
+
+    else ()
+        message(FATAL_ERROR "Non compatible Ethos-U NPU memory mode ${ETHOS_U_NPU_MEMORY_MODE}")
+    endif ()
+
+    set(OPTIONAL_FLAGS      "${OPTIONAL_FLAGS} ${ETHOS_U_NPU_FLAG} ${ETHOS_U_NPU_MEMORY_MODE_FLAG}")
 endif ()
 
 # Set specific flags depending on target platform and subsystem
@@ -86,8 +131,13 @@
 add_linker_script(${LINKER_SCRIPT_DIR} ${LINKER_SCRIPT_NAME})
 
 if (ETHOS_U_NPU_ENABLED)
+    if (ETHOS_U_NPU_ID STREQUAL U55)
+        set(DEFAULT_TA_CONFIG_FILE_PATH "${CMAKE_SCRIPTS_DIR}/timing_adapter/ta_config_u55_high_end.cmake")
+    else ()
+        set(DEFAULT_TA_CONFIG_FILE_PATH "${CMAKE_SCRIPTS_DIR}/timing_adapter/ta_config_u65_high_end.cmake")
+    endif ()
     USER_OPTION(TA_CONFIG_FILE "Path to the timing adapter configuration file"
-            "${CMAKE_SCRIPTS_DIR}/timing_adapter/ta_config_u55_high_end.cmake"
+            ${DEFAULT_TA_CONFIG_FILE_PATH}
             FILEPATH)
 
     # must be included after target subsystem CMake file
diff --git a/scripts/cmake/timing_adapter/ta_config_u55_high_end.cmake b/scripts/cmake/timing_adapter/ta_config_u55_high_end.cmake
index 30e1516..c822dc0 100644
--- a/scripts/cmake/timing_adapter/ta_config_u55_high_end.cmake
+++ b/scripts/cmake/timing_adapter/ta_config_u55_high_end.cmake
@@ -45,20 +45,41 @@
 set(TA0_HISTCNT     "0"        CACHE STRING "32-bit field. Read/write the selected histogram bin.")
 
 # Timing adapter settings for AXI1
-set(TA1_MAXR        "2"       CACHE STRING "6-bit field. Max no. of pending reads. 0=infinite")
-set(TA1_MAXW        "0"       CACHE STRING "6-bit field. Max no. of pending writes. 0=infinite")
-set(TA1_MAXRW       "0"       CACHE STRING "6-bit field. Max no. of pending reads+writes. 0=infinite")
-set(TA1_RLATENCY    "64"      CACHE STRING "12-bit field. Minimum latency (clock cycles) from AVALID to RVALID.")
-set(TA1_WLATENCY    "0"       CACHE STRING "12-bit field. Minimum latency (clock cycles) from WVALID&WLAST to BVALID.")
-set(TA1_PULSE_ON    "320"     CACHE STRING "No. of cycles addresses let through (0-65535).")
-set(TA1_PULSE_OFF   "80"      CACHE STRING "No. of cycles addresses blocked (0-65535).")
-set(TA1_BWCAP       "50"      CACHE STRING "16-bit field. Max no. of 64-bit words transfered per pulse cycle 0=infinite")
-set(TA1_PERFCTRL    "0"       CACHE STRING "6-bit field selecting an event for event counter 0=default")
-set(TA1_PERFCNT     "0"       CACHE STRING "32-bit event counter")
-set(TA1_MODE        "1"       CACHE STRING "Bit 0: 1=enable dynamic clocking to avoid underrun;
-                                            Bit 1: 1=enable random AR reordering (0=default);
-                                            Bit 2: 1=enable random R reordering (0=default);
-                                            Bit 3: 1=enable random B reordering (0=default);
-                                            Bit 11-4: Frequency scale 0=full speed, 255=(1/256) speed")
-set(TA1_HISTBIN     "0"       CACHE STRING "Controls which histogram bin (0-15) that should be accessed by HISTCNT.")
-set(TA1_HISTCNT     "0"       CACHE STRING "32-bit field. Read/write the selected histogram bin.")
+# If Memory mode is Sram_Only Timing adapter settings for AXI1 need to match the same as AXI0
+if (ETHOS_U_NPU_MEMORY_MODE STREQUAL Sram_Only)
+    set(TA1_MAXR        ${TA0_MAXR}         CACHE STRING "6-bit field. Max no. of pending reads. 0=infinite")
+    set(TA1_MAXW        ${TA0_MAXW}         CACHE STRING "6-bit field. Max no. of pending writes. 0=infinite")
+    set(TA1_MAXRW       ${TA0_MAXRW}        CACHE STRING "6-bit field. Max no. of pending reads+writes. 0=infinite")
+    set(TA1_RLATENCY    ${TA0_RLATENCY}     CACHE STRING "12-bit field. Minimum latency (clock cycles) from AVALID to RVALID.")
+    set(TA1_WLATENCY    ${TA0_WLATENCY}     CACHE STRING "12-bit field. Minimum latency (clock cycles) from WVALID&WLAST to BVALID.")
+    set(TA1_PULSE_ON    ${TA0_PULSE_ON}     CACHE STRING "No. of cycles addresses let through (0-65535).")
+    set(TA1_PULSE_OFF   ${TA0_PULSE_OFF}    CACHE STRING "No. of cycles addresses blocked (0-65535).")
+    set(TA1_BWCAP       ${TA0_BWCAP}        CACHE STRING "16-bit field. Max no. of 64-bit words transfered per pulse cycle 0=infinite")
+    set(TA1_PERFCTRL    ${TA0_PERFCTRL}     CACHE STRING "6-bit field selecting an event for event counter 0=default")
+    set(TA1_PERFCNT     ${TA0_PERFCNT}      CACHE STRING "32-bit event counter")
+    set(TA1_MODE        ${TA0_MODE}         CACHE STRING "Bit 0: 1=enable dynamic clocking to avoid underrun;
+                                                          Bit 1: 1=enable random AR reordering (0=default);
+                                                          Bit 2: 1=enable random R reordering (0=default);
+                                                          Bit 3: 1=enable random B reordering (0=default);
+                                                          Bit 11-4: Frequency scale 0=full speed, 255=(1/256) speed")
+    set(TA1_HISTBIN     ${TA0_HISTBIN}      CACHE STRING "Controls which histogram bin (0-15) that should be accessed by HISTCNT.")
+    set(TA1_HISTCNT     ${TA0_HISTCNT}      CACHE STRING "32-bit field. Read/write the selected histogram bin.")
+else ()
+    set(TA1_MAXR        "2"       CACHE STRING "6-bit field. Max no. of pending reads. 0=infinite")
+    set(TA1_MAXW        "0"       CACHE STRING "6-bit field. Max no. of pending writes. 0=infinite")
+    set(TA1_MAXRW       "0"       CACHE STRING "6-bit field. Max no. of pending reads+writes. 0=infinite")
+    set(TA1_RLATENCY    "64"      CACHE STRING "12-bit field. Minimum latency (clock cycles) from AVALID to RVALID.")
+    set(TA1_WLATENCY    "0"       CACHE STRING "12-bit field. Minimum latency (clock cycles) from WVALID&WLAST to BVALID.")
+    set(TA1_PULSE_ON    "320"     CACHE STRING "No. of cycles addresses let through (0-65535).")
+    set(TA1_PULSE_OFF   "80"      CACHE STRING "No. of cycles addresses blocked (0-65535).")
+    set(TA1_BWCAP       "50"      CACHE STRING "16-bit field. Max no. of 64-bit words transfered per pulse cycle 0=infinite")
+    set(TA1_PERFCTRL    "0"       CACHE STRING "6-bit field selecting an event for event counter 0=default")
+    set(TA1_PERFCNT     "0"       CACHE STRING "32-bit event counter")
+    set(TA1_MODE        "1"       CACHE STRING "Bit 0: 1=enable dynamic clocking to avoid underrun;
+                                                Bit 1: 1=enable random AR reordering (0=default);
+                                                Bit 2: 1=enable random R reordering (0=default);
+                                                Bit 3: 1=enable random B reordering (0=default);
+                                                Bit 11-4: Frequency scale 0=full speed, 255=(1/256) speed")
+    set(TA1_HISTBIN     "0"       CACHE STRING "Controls which histogram bin (0-15) that should be accessed by HISTCNT.")
+    set(TA1_HISTCNT     "0"       CACHE STRING "32-bit field. Read/write the selected histogram bin.")
+endif ()
\ No newline at end of file
diff --git a/scripts/vela/default_vela.ini b/scripts/vela/default_vela.ini
index 884b057..30de99d 100644
--- a/scripts/vela/default_vela.ini
+++ b/scripts/vela/default_vela.ini
@@ -34,6 +34,7 @@
 OffChipFlash_burst_length=128
 OffChipFlash_read_latency=64
 OffChipFlash_write_latency=64
+
 ; Ethos-U65 High-End: SRAM (16 GB/s) and DRAM (3.75 GB/s)
 [System_Config.Ethos_U65_High_End]
 core_clock=1e9
@@ -56,4 +57,12 @@
 const_mem_area=Axi1
 arena_mem_area=Axi0
 cache_mem_area=Axi0
-arena_cache_size=4194304
\ No newline at end of file
+arena_cache_size=4194304
+
+; Dedicated SRAM: the SRAM (384KB) is only for use by the Ethos-U
+; The non-SRAM memory is assumed to be read-writeable
+[Memory_Mode.Dedicated_Sram]
+const_mem_area=Axi1
+arena_mem_area=Axi1
+cache_mem_area=Axi0
+arena_cache_size=393216
\ No newline at end of file