MLECO-2395: Allow users to select Ethos-U memory mode
Change-Id: Icf09410f12072e8d7850dd1e540c3243af24ed09
diff --git a/source/application/hal/platforms/bare-metal/bsp/mem_layout/mps3-sse-300.ld b/source/application/hal/platforms/bare-metal/bsp/mem_layout/mps3-sse-300.ld
index e5c2a14..bcbc81f 100644
--- a/source/application/hal/platforms/bare-metal/bsp/mem_layout/mps3-sse-300.ld
+++ b/source/application/hal/platforms/bare-metal/bsp/mem_layout/mps3-sse-300.ld
@@ -144,7 +144,11 @@
.sram :
{
. = ALIGN(16);
- *(.bss.NoInit.activation_buf)
+ /* Cache area (if used) */
+ *(.bss.NoInit.ethos_u_cache)
+ . = ALIGN (16);
+ /* activation buffers a.k.a tensor arena when memory mode sram only or shared sram */
+ *(.bss.NoInit.activation_buf_sram)
. = ALIGN(16);
} > SRAM AT > SRAM
@@ -177,13 +181,17 @@
/* __attribute__((aligned(16))) is not handled by the CMSIS startup code.
* Force the alignment here as a workaround */
. = ALIGN(16);
+ /* nn model's baked in input matrices */
*(ifm)
. = ALIGN(16);
+ /* nn model's default space */
*(nn_model)
. = ALIGN (16);
+ /* labels */
*(labels)
. = ALIGN (16);
- *(activation_buf)
+ /* activation buffers a.k.a tensor arena when memory mode dedicated sram */
+ *(activation_buf_dram)
. = ALIGN (16);
} > DDR AT > DDR
diff --git a/source/application/hal/platforms/bare-metal/bsp/mem_layout/mps3-sse-300.sct b/source/application/hal/platforms/bare-metal/bsp/mem_layout/mps3-sse-300.sct
index 4760875..62dbbe5 100644
--- a/source/application/hal/platforms/bare-metal/bsp/mem_layout/mps3-sse-300.sct
+++ b/source/application/hal/platforms/bare-metal/bsp/mem_layout/mps3-sse-300.sct
@@ -67,8 +67,11 @@
;-----------------------------------------------------
isram.bin 0x31000000 UNINIT ALIGN 16 0x00400000
{
- ; activation buffers a.k.a tensor arena
- *.o (.bss.NoInit.activation_buf)
+ ; Cache area (if used)
+ *.o (.bss.NoInit.ethos_u_cache)
+
+ ; activation buffers a.k.a tensor arena when memory mode sram only or shared sram
+ *.o (.bss.NoInit.activation_buf_sram)
}
}
@@ -88,15 +91,14 @@
; nn model's baked in input matrices
*.o (ifm)
- ; nn model
+ ; nn model's default space
*.o (nn_model)
; labels
*.o (labels)
- ; if the activation buffer (tensor arena) doesn't
- ; fit in the SRAM region, we accommodate it here
- *.o (activation_buf)
+ ; activation buffers a.k.a tensor arena when memory mode dedicated sram
+ *.o (activation_buf_dram)
}
;-----------------------------------------------------
diff --git a/source/application/hal/platforms/bare-metal/bsp/mem_layout/simple_platform.ld b/source/application/hal/platforms/bare-metal/bsp/mem_layout/simple_platform.ld
index ceaff7d..e5b6bd9 100644
--- a/source/application/hal/platforms/bare-metal/bsp/mem_layout/simple_platform.ld
+++ b/source/application/hal/platforms/bare-metal/bsp/mem_layout/simple_platform.ld
@@ -137,7 +137,11 @@
.sram :
{
. = ALIGN(16);
- *(.bss.NoInit.activation_buf)
+ /* Cache area (if used) */
+ *(.bss.NoInit.ethos_u_cache)
+ . = ALIGN (16);
+ /* activation buffers a.k.a tensor arena when memory mode sram only or shared sram */
+ *(.bss.NoInit.activation_buf_sram)
. = ALIGN(16);
} > SRAM AT > SRAM
@@ -170,13 +174,17 @@
/* __attribute__((aligned(16))) is not handled by the CMSIS startup code.
* Force the alignment here as a workaround */
. = ALIGN(16);
+ /* nn model's baked in input matrices */
*(ifm)
. = ALIGN(16);
+ /* nn model's default space */
*(nn_model)
. = ALIGN (16);
+ /* labels */
*(labels)
. = ALIGN (16);
- *(activation_buf)
+ /* activation buffers a.k.a tensor arena when memory mode dedicated sram */
+ *(activation_buf_dram)
. = ALIGN (16);
} > DDR AT > DDR
diff --git a/source/application/hal/platforms/bare-metal/bsp/mem_layout/simple_platform.sct b/source/application/hal/platforms/bare-metal/bsp/mem_layout/simple_platform.sct
index 0c6a388..e84d81e 100644
--- a/source/application/hal/platforms/bare-metal/bsp/mem_layout/simple_platform.sct
+++ b/source/application/hal/platforms/bare-metal/bsp/mem_layout/simple_platform.sct
@@ -16,6 +16,10 @@
; *************************************************************
; *** Scatter-Loading Description File ***
; *************************************************************
+; Please see docs/sections/appendix.md for memory mapping information.
+;
+; Note: Ethos-U NPU can access BRAM, internal SRAM and the DDR sections => activation buffers and
+; the model should only be placed in those regions.
;
;---------------------------------------------------------
; First load region (ITCM)
@@ -63,8 +67,11 @@
;-----------------------------------------------------
isram.bin 0x31000000 UNINIT ALIGN 16 0x00400000
{
- ; activation buffers a.k.a tensor arena
- *.o (.bss.NoInit.activation_buf)
+ ; Cache area (if used)
+ *.o (.bss.NoInit.ethos_u_cache)
+
+ ; activation buffers a.k.a tensor arena when memory mode sram only or shared sram
+ *.o (.bss.NoInit.activation_buf_sram)
}
}
@@ -84,15 +91,14 @@
; nn model's baked in input matrices
*.o (ifm)
- ; nn model
+ ; nn model's default space
*.o (nn_model)
; labels
*.o (labels)
- ; if the activation buffer (tensor arena) doesn't
- ; fit in the SRAM region, we accommodate it here
- *.o (activation_buf)
+ ; activation buffers a.k.a tensor arena when memory mode dedicated sram
+ *.o (activation_buf_dram)
}
;-----------------------------------------------------