diff --git a/docs/sections/building.md b/docs/sections/building.md
index 6cbabd9..2739320 100644
--- a/docs/sections/building.md
+++ b/docs/sections/building.md
@@ -57,8 +57,8 @@
     warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
     ```
 
-> **Note:** If required, add the compiler to the path:
->
+> **Note:** If required, add the compiler to the path (can be added to ~/.bashrc to be set permanently):
+> 
 > `export PATH=/path/to/armclang/bin:$PATH` OR `export PATH=/path/to/gcc-arm-none-eabi-toolchain/bin:$PATH`
 
 - If you are using the proprietary Arm Compiler, ensure that the compiler license has been correctly configured.
diff --git a/docs/sections/memory_considerations.md b/docs/sections/memory_considerations.md
index b3cbfa5..3472f2f 100644
--- a/docs/sections/memory_considerations.md
+++ b/docs/sections/memory_considerations.md
@@ -145,7 +145,7 @@
 |   *Ethos™-U65*   |    `Dedicated_Sram`    |         `Shared_Sram`          |
 
 For further information on the default settings, please refer to: [default_vela.ini](../../scripts/vela/default_vela.ini).
-
+To use the other supported memory modes refer to [vela.ini](https://review.mlplatform.org/plugins/gitiles/ml/ethos-u/ethos-u-vela/+/refs/tags/3.2.0/vela.ini).
 For *Ethos-U55* NPU, the system SRAM can also be used to store the neural network model along with the `tensor arena`.
 Vela supports optimizing the model for this configuration with its `Sram_Only` memory mode.
 Although the Vela settings for this configurations suggests that only AXI0 bus is used, when compiling the model
@@ -155,14 +155,13 @@
 vela \
   --accelerator-config=ethos-u55-128 \
   --optimise Performance \
-  --config scripts/vela/default_vela.ini
+  --config scripts/vela/vela.ini
   --memory-mode=Sram_Only
   --system-config=Ethos_U55_High_End_Embedded
   ds_cnn_clustered_int8.tflite
 
 Info: Changing const_mem_area from Sram to OnChipFlash. This will use the same characteristics as Sram.
 ```
-
 This means that the  neural network model is always placed in the flash region. In this case, timing adapters for the
 AXI buses are set the same values to mimic both bandwidth and latency characteristics of a SRAM memory device.
 See [Ethos-U55 NPU timing adapter default configuration](../../scripts/cmake/timing_adapter/ta_config_u55_high_end.cmake).
diff --git a/source/use_case/noise_reduction/src/UseCaseHandler.cc b/source/use_case/noise_reduction/src/UseCaseHandler.cc
index 2f53ce6..4934abb 100644
--- a/source/use_case/noise_reduction/src/UseCaseHandler.cc
+++ b/source/use_case/noise_reduction/src/UseCaseHandler.cc
@@ -215,6 +215,18 @@
             profiler.PrintProfilingResult();
             IncrementAppCtxClipIdx(ctx);
 
+            std::string clearString{' '};
+            platform.data_psn->present_data_text(
+                    clearString.c_str(), clearString.size(),
+                    dataPsnTxtInfStartX, dataPsnTxtInfStartY, false);
+
+            std::string completeMsg{"Inference complete!"};
+
+            /* Display message on the LCD - inference complete. */
+            platform.data_psn->present_data_text(
+                    completeMsg.c_str(), completeMsg.size(),
+                    dataPsnTxtInfStartX, dataPsnTxtInfStartY, false);
+
         } while (runAll && ctx.Get<uint32_t>("clipIndex") != startClipIdx);
 
         return true;
diff --git a/source/use_case/noise_reduction/usecase.cmake b/source/use_case/noise_reduction/usecase.cmake
index 60f92ae..8dfde58 100644
--- a/source/use_case/noise_reduction/usecase.cmake
+++ b/source/use_case/noise_reduction/usecase.cmake
@@ -20,7 +20,7 @@
     STRING)
 
 if (ETHOS_U_NPU_ENABLED)
-    set(DEFAULT_MODEL_PATH      ${DEFAULT_MODEL_DIR}/rnnoise_INT8_vela_${DEFAULT_NPU_CONFIG_ID}.tflite)
+    set(DEFAULT_MODEL_PATH      ${DEFAULT_MODEL_DIR}/rnnoise_INT8_vela_${ETHOS_U_NPU_CONFIG_ID}.tflite)
 else()
     set(DEFAULT_MODEL_PATH      ${DEFAULT_MODEL_DIR}/rnnoise_INT8.tflite)
 endif()