diff --git a/scripts/cmake/bare-metal-sources.cmake b/scripts/cmake/bare-metal-sources.cmake
deleted file mode 100644
index abca622..0000000
--- a/scripts/cmake/bare-metal-sources.cmake
+++ /dev/null
@@ -1,206 +0,0 @@
-#----------------------------------------------------------------------------
-#  Copyright (c) 2021 Arm Limited. All rights reserved.
-#  SPDX-License-Identifier: Apache-2.0
-#
-#  Licensed under the Apache License, Version 2.0 (the "License");
-#  you may not use this file except in compliance with the License.
-#  You may obtain a copy of the License at
-#
-#      http://www.apache.org/licenses/LICENSE-2.0
-#
-#  Unless required by applicable law or agreed to in writing, software
-#  distributed under the License is distributed on an "AS IS" BASIS,
-#  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-#  See the License for the specific language governing permissions and
-#  limitations under the License.
-#----------------------------------------------------------------------------
-set(CMAKE_INSTALL_PREFIX ${CMAKE_SOURCE_DIR}/build_baremetal)
-set(PLAT_HAL ${CMAKE_CURRENT_SOURCE_DIR}/source/application/hal/platforms/bare-metal)
-
-# If target platform not defined raise an error
-# TARGET_PLATFORM either should have been defined by the user or set to default value mps3
-if (NOT DEFINED TARGET_PLATFORM)
-    message(FATAL_ERROR "Invalid target platform, specify TARGET_PLATFORM=mps3")
-endif ()
-message(STATUS "target platform ${TARGET_PLATFORM}")
-
-set(SOURCE_GEN_DIR          ${CMAKE_BINARY_DIR}/generated/bsp)
-if (NOT DEFINED MEM_PROFILES_SRC_DIR)
-    set(MEM_PROFILES_SRC_DIR    ${CMAKE_CURRENT_SOURCE_DIR}/scripts/cmake/subsystem-profiles)
-endif()
-
-set(MEM_PROFILE_TEMPLATE    ${CMAKE_CURRENT_SOURCE_DIR}/scripts/cmake/templates/peripheral_memmap.h.template)
-set(IRQ_PROFILE_TEMPLATE    ${CMAKE_CURRENT_SOURCE_DIR}/scripts/cmake/templates/peripheral_irqs.h.template)
-set(MEM_REGIONS_TEMPLATE    ${CMAKE_CURRENT_SOURCE_DIR}/scripts/cmake/templates/mem_regions.h.template)
-set(TA_SETTINGS_TEMPLATE    ${CMAKE_CURRENT_SOURCE_DIR}/scripts/cmake/templates/timing_adapter_settings.template)
-set(LINKER_SCRIPT_DIR       "${PLAT_HAL}/bsp/mem_layout")
-set(TENSORFLOW_LITE_MICRO_PLATFORM_LIB_NAME  "libtensorflow-microlite.a")
-set(TENSORFLOW_LITE_MICRO_FLAG               "-DTF_LITE_STATIC_MEMORY")
-set(ETHOS_U_NPU_FLAG                           "-DARM_NPU=1")
-
-if (ETHOS_U_NPU_ENABLED)
-
-    assert_defined(ETHOS_U_NPU_ID)
-    assert_defined(ETHOS_U_NPU_MEMORY_MODE)
-    assert_defined(ETHOS_U_NPU_CONFIG_ID)
-
-    if (ETHOS_U_NPU_MEMORY_MODE STREQUAL Sram_Only)
-
-        if (ETHOS_U_NPU_ID STREQUAL U55)
-            set(ETHOS_U_NPU_MEMORY_MODE_FLAG "-DETHOS_U_NPU_MEMORY_MODE=ETHOS_U_NPU_MEM_MODE_SRAM_ONLY")
-        else ()
-            message(FATAL_ERROR "Non compatible Ethos-U NPU memory mode and processor ${ETHOS_U_NPU_MEMORY_MODE} - ${ETHOS_U_NPU_ID}. `sram_only` can be used only for Ethos-U55.")
-        endif ()
-
-    elseif (ETHOS_U_NPU_MEMORY_MODE STREQUAL Shared_Sram)
-        # Shared Sram can be used for Ethos-U55 and Ethos-U65
-        set(ETHOS_U_NPU_MEMORY_MODE_FLAG "-DETHOS_U_NPU_MEMORY_MODE=ETHOS_U_NPU_MEMORY_MODE_SHARED_SRAM")
-
-    elseif (ETHOS_U_NPU_MEMORY_MODE STREQUAL Dedicated_Sram)
-        # Dedicated Sram is used only for Ethos-U65
-        if (ETHOS_U_NPU_ID STREQUAL U65)
-            set(ETHOS_U_NPU_MEMORY_MODE_FLAG  "-DETHOS_U_NPU_MEMORY_MODE=ETHOS_U_NPU_MEMORY_MODE_DEDICATED_SRAM")
-        else ()
-            message(FATAL_ERROR "Non compatible Ethos-U NPU memory mode and processor ${ETHOS_U_NPU_MEMORY_MODE} - ${ETHOS_U_NPU_ID}. `dedicated_sram` can be used only for Ethos-U65.")
-        endif ()
-
-    else ()
-        message(FATAL_ERROR "Non compatible Ethos-U NPU memory mode ${ETHOS_U_NPU_MEMORY_MODE}")
-    endif ()
-
-    set(OPTIONAL_FLAGS      "${OPTIONAL_FLAGS} ${ETHOS_U_NPU_FLAG} ${ETHOS_U_NPU_MEMORY_MODE_FLAG}")
-endif ()
-
-# Set specific flags depending on target platform and subsystem
-if (TARGET_PLATFORM STREQUAL mps3)
-    set(MPS3_PLATFORM_FLAG          "-DMPS3_PLATFORM=1")
-
-    # If target platform is mps3 and subsystem not defined raise an error,
-    # TARGET_SUBSYSTEM either should have been defined by the user or set to a default value
-    if (NOT DEFINED TARGET_SUBSYSTEM)
-        message(FATAL_ERROR "Target subsystem for mps3 undefined, "
-                            "specify -DTARGET_SUBSYSTEM=<sse-300>")
-    endif ()
-
-    if (TARGET_SUBSYSTEM STREQUAL sse-300)
-        message(STATUS          "target subsystem is ${TARGET_SUBSYSTEM}")
-        set(BSP_PACKAGE_DIR     "${PLAT_HAL}/bsp/bsp-packs/mps3")
-        set(LINKER_SCRIPT_NAME  "${TARGET_PLATFORM}-${TARGET_SUBSYSTEM}")
-
-        # Include the mem profile definitions specific to our target subsystem
-        include(${MEM_PROFILES_SRC_DIR}/corstone-${TARGET_SUBSYSTEM}.cmake)
-        set(OPTIONAL_FLAGS      "${OPTIONAL_FLAGS} ${MPS3_PLATFORM_FLAG}")
-
-        # For deployment on the MPS3 FPGA platform, we need to produce
-        # two bin files - one that is loaded into the ITCM, and another
-        # that is loaded into the DDR region.
-        set(LINKER_SECTION_TAGS     "*.at_itcm" "*.at_ddr")
-        set(LINKER_OUTPUT_BIN_TAGS  "itcm.bin"  "ddr.bin")
-        set(MPS3_FPGA_CONFIG        "${CMAKE_CURRENT_SOURCE_DIR}/scripts/${TARGET_PLATFORM}/${TARGET_SUBSYSTEM}/images.txt")
-    else ()
-        message(FATAL_ERROR "Non compatible target subsystem: ${TARGET_SUBSYSTEM}")
-    endif ()
-elseif (TARGET_PLATFORM STREQUAL simple_platform)
-    set(BSP_PACKAGE_DIR         "${PLAT_HAL}/bsp/bsp-packs/${TARGET_PLATFORM}")
-    set(LINKER_SCRIPT_NAME      "${TARGET_PLATFORM}")
-    include(${MEM_PROFILES_SRC_DIR}/${TARGET_PLATFORM}.cmake)
-    set(OPTIONAL_FLAGS          "${OPTIONAL_FLAGS}")
-    set(LINKER_SECTION_TAGS     "*.at_itcm" "*.at_ddr")
-    set(LINKER_OUTPUT_BIN_TAGS  "itcm.bin"  "ddr.bin")
-else ()
-    message(FATAL_ERROR "Non compatible target platform ${TARGET_PLATFORM}")
-endif ()
-
-# Add link options for the linker script to be used:
-add_linker_script(${LINKER_SCRIPT_DIR} ${LINKER_SCRIPT_NAME})
-
-if (ETHOS_U_NPU_ENABLED)
-    if (ETHOS_U_NPU_ID STREQUAL U55)
-        set(DEFAULT_TA_CONFIG_FILE_PATH "${CMAKE_SCRIPTS_DIR}/timing_adapter/ta_config_u55_high_end.cmake")
-    else ()
-        set(DEFAULT_TA_CONFIG_FILE_PATH "${CMAKE_SCRIPTS_DIR}/timing_adapter/ta_config_u65_high_end.cmake")
-    endif ()
-
-    # must be included after target subsystem CMake file
-    assert_defined(TA_CONFIG_FILE)
-    include(${TA_CONFIG_FILE})
-endif()
-
-# Generate the memory map header file from the mem profile cmake included in one of
-# the previous sections
-message(STATUS "Configuring file from ${MEM_PROFILE_TEMPLATE}"
-                                   ", ${IRQ_PROFILE_TEMPLATE}"
-                                " and ${MEM_REGIONS_TEMPLATE}")
-
-configure_file("${MEM_PROFILE_TEMPLATE}" "${SOURCE_GEN_DIR}/peripheral_memmap.h")
-configure_file("${IRQ_PROFILE_TEMPLATE}" "${SOURCE_GEN_DIR}/peripheral_irqs.h")
-configure_file("${MEM_REGIONS_TEMPLATE}" "${SOURCE_GEN_DIR}/mem_regions.h")
-configure_file("${TA_SETTINGS_TEMPLATE}" "${SOURCE_GEN_DIR}/timing_adapter_settings.h")
-
-message(STATUS "Using BSP package from: ${BSP_PACKAGE_DIR}")
-
-if (DEFINED VERIFY_TEST_OUTPUT)
-    message(STATUS "Test output verification flag is: ${VERIFY_TEST_OUTPUT}")
-    set(OPTIONAL_FLAGS "${OPTIONAL_FLAGS} -DVERIFY_TEST_OUTPUT=${VERIFY_TEST_OUTPUT}")
-endif ()
-
-if (DEFINED LOG_LEVEL)
-    message(STATUS "Setting log level to ${LOG_LEVEL}")
-    set(OPTIONAL_FLAGS "${OPTIONAL_FLAGS} -DLOG_LEVEL=${LOG_LEVEL}")
-endif()
-
-if (DEFINED ACTIVATION_BUF_SRAM_SZ)
-    message(STATUS "Maximum SRAM space for activations buffers for this system: ${ACTIVATION_BUF_SRAM_SZ}")
-    set(OPTIONAL_FLAGS "${OPTIONAL_FLAGS} -DACTIVATION_BUF_SRAM_SZ=${ACTIVATION_BUF_SRAM_SZ}")
-endif()
-
-if (DEFINED ARMCLANG_DEBUG_DWARF_LEVEL)
-    message(STATUS "setting dwarf conformance level to gdwarf-${ARMCLANG_DEBUG_DWARF_LEVEL}")
-    set(OPTIONAL_FLAGS "${OPTIONAL_FLAGS} -gdwarf-${ARMCLANG_DEBUG_DWARF_LEVEL}")
-endif()
-
-set(COMPILER_FLAGS              "${TENSORFLOW_LITE_MICRO_FLAG} ${PROFILING_OPT} ${OPTIONAL_FLAGS}")
-# For some reason, cmake doesn't pass the c++ standard flag, adding it manually
-set(CMAKE_CXX_FLAGS             "${COMPILER_FLAGS}" CACHE INTERNAL "")
-set(CMAKE_C_FLAGS               "${COMPILER_FLAGS}" CACHE INTERNAL "")
-set(CMAKE_ASM_COMPILE_OBJECT    ${CMAKE_CXX_FLAGS})
-
-# Tell linker that reset interrupt handler is our entry point
-add_link_options(--entry Reset_Handler)
-
-set(PLAT_BSP_INCLUDES
-    ${PLAT_HAL}/bsp/cmsis-device/include
-    ${PLAT_HAL}/bsp/include/
-    ${PLAT_HAL}/bsp/bsp-core/include
-    ${BSP_PACKAGE_DIR}/include
-)
-
-# Include directories:
-set(PLAT_INCLUDE_DIRS
-    ${PLAT_BSP_INCLUDES}
-    ${PLAT_HAL}/utils/include
-    ${PLAT_HAL}/images/include
-    ${PLAT_HAL}/data_presentation/lcd/include
-    ${PLAT_HAL}/timer/include
-    ${SOURCE_GEN_DIR}
-    )
-
-# Source files
-file(GLOB_RECURSE SRC_PLAT_HAL
-
-    # Higher level HAL sources - software logic implementations
-    "${PLAT_HAL}/data_*/*.c"
-    "${PLAT_HAL}/images/*.c"
-    "${PLAT_HAL}/timer/*.c"
-    "${PLAT_HAL}/utils/*.c"
-
-    # Low level HAL sources - these enable interaction with
-    # the actual hardware
-    "${PLAT_HAL}/bsp/cmsis-device/*.c"
-    "${PLAT_HAL}/bsp/bsp-core/*.c"
-    "${BSP_PACKAGE_DIR}/*.c"
-    )
-
-# Special retarget source to direct stdin, stdout and stderr streams to the
-# UART block.
-set(PLAT_RETARGET_SOURCE "${PLAT_HAL}/bsp/bsp-core/retarget.c")
diff --git a/scripts/cmake/cmsis-dsp.cmake b/scripts/cmake/cmsis-dsp.cmake
index ab2b0f9..f2de158 100644
--- a/scripts/cmake/cmsis-dsp.cmake
+++ b/scripts/cmake/cmsis-dsp.cmake
@@ -17,12 +17,7 @@
 
 # CMSIS-DSP library CMake helper script.
 
-# 1. We should be cross-compiling (non-native target)
-if (TARGET_PLATFORM STREQUAL native)
-    message(FATAL_ERROR "No CMSIS-DSP support for native target.")
-endif()
-
-# 2. Check if CMSIS sources have been defined
+# Check if CMSIS sources have been defined
 if (NOT DEFINED CMSIS_SRC_PATH)
     message(FATAL_ERROR "CMSIS path should be defined for CMSIS-DSP library to be built")
 endif()
diff --git a/scripts/cmake/common_user_options.cmake b/scripts/cmake/common_user_options.cmake
index 13c88d2..afc5386 100644
--- a/scripts/cmake/common_user_options.cmake
+++ b/scripts/cmake/common_user_options.cmake
@@ -29,8 +29,6 @@
 
 message(STATUS "Assessing common user options...")
 
-set(CMAKE_TOOLCHAIN_DIR ${CMAKE_CURRENT_LIST_DIR}/toolchains)
-set(DEPENDENCY_ROOT_DIR ${CMAKE_CURRENT_LIST_DIR}/../../dependencies)
 include(${CMAKE_CURRENT_LIST_DIR}/util_functions.cmake)
 
 USER_OPTION(LOG_LEVEL "Log level for the application"
@@ -143,22 +141,3 @@
                 FILEPATH)
     endif()
 endif()
-
-if (TARGET_PLATFORM STREQUAL mps3)
-    message(STATUS "Platform: MPS3 FPGA Prototyping Board or FVP")
-    set(DEFAULT_TOOLCHAIN_FILE ${CMAKE_TOOLCHAIN_DIR}/bare-metal-gcc.cmake)
-elseif (TARGET_PLATFORM STREQUAL simple_platform)
-    message(STATUS "Platform: Simple platform with minimal peripherals")
-    set(DEFAULT_TOOLCHAIN_FILE ${CMAKE_TOOLCHAIN_DIR}/bare-metal-gcc.cmake)
-elseif (TARGET_PLATFORM STREQUAL native)
-    message(STATUS "Platform: Native (Linux based x86_64/aarch64 system)")
-    set(DEFAULT_TOOLCHAIN_FILE ${CMAKE_TOOLCHAIN_DIR}/native-gcc.cmake)
-else ()
-    message(FATAL_ERROR "Invalid platform specified: ${TARGET_PLATFORM}")
-endif ()
-
-if (NOT DEFINED CMAKE_TOOLCHAIN_FILE)
-    set(CMAKE_TOOLCHAIN_FILE ${DEFAULT_TOOLCHAIN_FILE}
-        CACHE FILEPATH "Toolchain file")
-endif()
-message(STATUS "Using CMAKE_TOOLCHAIN_FILE: ${CMAKE_TOOLCHAIN_FILE}")
diff --git a/scripts/cmake/native-sources.cmake b/scripts/cmake/native-sources.cmake
deleted file mode 100644
index 6ebf435..0000000
--- a/scripts/cmake/native-sources.cmake
+++ /dev/null
@@ -1,61 +0,0 @@
-#----------------------------------------------------------------------------
-#  Copyright (c) 2021 Arm Limited. All rights reserved.
-#  SPDX-License-Identifier: Apache-2.0
-#
-#  Licensed under the Apache License, Version 2.0 (the "License");
-#  you may not use this file except in compliance with the License.
-#  You may obtain a copy of the License at
-#
-#      http://www.apache.org/licenses/LICENSE-2.0
-#
-#  Unless required by applicable law or agreed to in writing, software
-#  distributed under the License is distributed on an "AS IS" BASIS,
-#  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-#  See the License for the specific language governing permissions and
-#  limitations under the License.
-#----------------------------------------------------------------------------
-# Set the install prefix
-set(CMAKE_INSTALL_PREFIX ${CMAKE_SOURCE_DIR}/build_native)
-set(PLAT_HAL ${CMAKE_CURRENT_SOURCE_DIR}/source/application/hal/platforms/native)
-
-if (ETHOS_U_NPU_ENABLED)
-    message(WARNING "EthosU can't be enabled for native builds."
-                    "Use -DETHOS_U_NPU_ENABLED=OFF flag for this target platform."
-                    "Overriding, disabling use of EthosU...")
-    set(ETHOS_U_NPU_ENABLED OFF)
-endif()
-
-if (DEFINED LOG_LEVEL)
-    message(STATUS "Setting log level to ${LOG_LEVEL}")
-    set (LOG_FLAG "-DLOG_LEVEL=${LOG_LEVEL}")
-endif()
-
-set(TENSORFLOW_LITE_MICRO_PLATFORM_LIB_NAME  "libtensorflow-microlite.a")
-set(TENSORFLOW_LITE_MICRO_FLAGS "-DTF_LITE_STATIC_MEMORY -DACTIVATION_BUF_SRAM_SZ=0")
-
-if (DEFINED VERIFY_TEST_OUTPUT)
-    message(STATUS "Test output verification flag is: ${VERIFY_TEST_OUTPUT}")
-    set(PROFILING_OPT "${PROFILING_OPT} -DVERIFY_TEST_OUTPUT=${VERIFY_TEST_OUTPUT}")
-endif ()
-
-set(CMAKE_C_FLAGS
-        "${PROFILING_OPT} ${LOG_FLAG} ${TENSORFLOW_LITE_MICRO_FLAGS}"
-        CACHE INTERNAL "")
-
-set(CMAKE_CXX_FLAGS
-        "${PROFILING_OPT} ${LOG_FLAG} ${TENSORFLOW_LITE_MICRO_FLAGS}"
-        CACHE INTERNAL "")
-
-# Include directories:
-set(PLAT_INCLUDE_DIRS
-    ${PLAT_HAL}/utils/include
-    ${PLAT_HAL}/images/include
-    ${PLAT_HAL}/data_presentation/log/include
-    ${PLAT_HAL}/timer/include
-    )
-
-# Source files
-file(GLOB_RECURSE SRC_PLAT_HAL
-    "${PLAT_HAL}/**/*.c"
-    "${PLAT_HAL}/**/*.cc"
-    )
diff --git a/scripts/cmake/platforms/mps3/build_configuration.cmake b/scripts/cmake/platforms/mps3/build_configuration.cmake
new file mode 100644
index 0000000..76c9e78
--- /dev/null
+++ b/scripts/cmake/platforms/mps3/build_configuration.cmake
@@ -0,0 +1,67 @@
+#----------------------------------------------------------------------------
+#  Copyright (c) 2022 Arm Limited. All rights reserved.
+#  SPDX-License-Identifier: Apache-2.0
+#
+#  Licensed under the Apache License, Version 2.0 (the "License");
+#  you may not use this file except in compliance with the License.
+#  You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+#  Unless required by applicable law or agreed to in writing, software
+#  distributed under the License is distributed on an "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+#  See the License for the specific language governing permissions and
+#  limitations under the License.
+#----------------------------------------------------------------------------
+
+function(set_platform_global_defaults)
+    message(STATUS "Platform: MPS3 FPGA Prototyping Board or FVP")
+    if (NOT DEFINED CMAKE_TOOLCHAIN_FILE)
+        set(CMAKE_TOOLCHAIN_FILE ${CMAKE_TOOLCHAIN_DIR}/bare-metal-gcc.cmake
+                CACHE FILEPATH "Toolchain file")
+    endif()
+
+    set(LINKER_SCRIPT_NAME "mps3-${TARGET_SUBSYSTEM}" PARENT_SCOPE)
+    set(PLATFORM_DRIVERS_DIR "${HAL_PLATFORM_DIR}/mps3" PARENT_SCOPE)
+
+endfunction()
+
+function(platform_custom_post_build)
+    set(oneValueArgs TARGET_NAME)
+    cmake_parse_arguments(PARSED "" "${oneValueArgs}" "" ${ARGN} )
+
+    set_target_properties(${PARSED_TARGET_NAME} PROPERTIES SUFFIX ".axf")
+    # Add link options for the linker script to be used:
+    add_linker_script(
+            ${PARSED_TARGET_NAME}          # Target
+            ${CMAKE_SCRIPTS_DIR}/platforms/mps3    # Directory path
+            ${LINKER_SCRIPT_NAME})  # Name of the file without suffix
+
+    add_target_map_file(
+            ${PARSED_TARGET_NAME}
+            ${CMAKE_RUNTIME_OUTPUT_DIRECTORY}/${PARSED_TARGET_NAME}.map)
+
+    set(SECTORS_DIR ${CMAKE_RUNTIME_OUTPUT_DIRECTORY}/sectors)
+    set(SECTORS_BIN_DIR ${SECTORS_DIR}/${use_case})
+
+    file(REMOVE_RECURSE ${SECTORS_BIN_DIR})
+    file(MAKE_DIRECTORY ${SECTORS_BIN_DIR})
+
+    set(LINKER_SECTION_TAGS     "*.at_itcm" "*.at_ddr")
+    set(LINKER_OUTPUT_BIN_TAGS  "itcm.bin"  "ddr.bin")
+
+    add_bin_generation_command(
+            TARGET_NAME ${PARSED_TARGET_NAME}
+            OUTPUT_DIR  ${SECTORS_BIN_DIR}
+            AXF_PATH    ${CMAKE_RUNTIME_OUTPUT_DIRECTORY}/${PARSED_TARGET_NAME}.axf
+            SECTION_PATTERNS    "${LINKER_SECTION_TAGS}"
+            OUTPUT_BIN_NAMES    "${LINKER_OUTPUT_BIN_TAGS}")
+
+    set(MPS3_FPGA_CONFIG "${CMAKE_CURRENT_SOURCE_DIR}/scripts/mps3/${TARGET_SUBSYSTEM}/images.txt")
+
+    add_custom_command(TARGET ${PARSED_TARGET_NAME}
+            POST_BUILD
+            COMMAND ${CMAKE_COMMAND} -E copy ${MPS3_FPGA_CONFIG} ${SECTORS_DIR})
+
+endfunction()
\ No newline at end of file
diff --git a/scripts/cmake/platforms/mps3/mps3-sse-300.ld b/scripts/cmake/platforms/mps3/mps3-sse-300.ld
new file mode 100644
index 0000000..d369fa7
--- /dev/null
+++ b/scripts/cmake/platforms/mps3/mps3-sse-300.ld
@@ -0,0 +1,277 @@
+/*
+ * Copyright (c) 2021 Arm Limited. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+__STACK_SIZE = 0x00060000;
+__HEAP_SIZE  = 0x000C0000;
+
+/* System memory brief */
+MEMORY
+{
+  ITCM  (rx)  : ORIGIN = 0x00000000, LENGTH = 0x00080000
+  DTCM  (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00080000
+  BRAM  (rwx) : ORIGIN = 0x11000000, LENGTH = 0x00100000
+  SRAM  (rwx) : ORIGIN = 0x31000000, LENGTH = 0x00200000
+  DDR   (rwx) : ORIGIN = 0x70000000, LENGTH = 0x02000000
+
+  /* Dynamic load regions declared for use by FVP only
+   * These regions are mentioned in the CMake subsystem profile.
+   * Do not change the addresses here in isolation. */
+  DDR_dynamic_model (rx) : ORIGIN = 0x90000000, LENGTH = 0x02000000
+  DDR_dynamic_ifm   (rx) : ORIGIN = 0x92000000, LENGTH = 0x01000000
+  DDR_dynamic_ofm   (rx) : ORIGIN = 0x93000000, LENGTH = 0x01000000
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions ITCM and RAM.
+ * It references following symbols, which must be defined in code:
+ *   Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ *   __exidx_start
+ *   __exidx_end
+ *   __copy_table_start__
+ *   __copy_table_end__
+ *   __zero_table_start__
+ *   __zero_table_end__
+ *   __etext
+ *   __data_start__
+ *   __preinit_array_start
+ *   __preinit_array_end
+ *   __init_array_start
+ *   __init_array_end
+ *   __fini_array_start
+ *   __fini_array_end
+ *   __data_end__
+ *   __bss_start__
+ *   __bss_end__
+ *   __end__
+ *   end
+ *   __HeapLimit
+ *   __StackLimit
+ *   __StackTop
+ *   __stack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+  .text.at_itcm :
+  {
+    KEEP(*(.vectors))
+
+    /**
+     * All code goes here, with one exception of
+     * all_ops_resolver object file. This code
+     * instead placed on BRAM. See comment in the
+     * BRAM section for details.
+     **/
+    *(EXCLUDE_FILE(*all_ops_resolver.o *hal.c.obj) .text*)
+
+    KEEP(*(.init))
+    KEEP(*(.fini))
+
+    /* .ctors */
+    *crtbegin.o(.ctors)
+    *crtbegin?.o(.ctors)
+    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+    *(SORT(.ctors.*))
+    *(.ctors)
+
+    /* .dtors */
+    *crtbegin.o(.dtors)
+    *crtbegin?.o(.dtors)
+    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+    *(SORT(.dtors.*))
+    *(.dtors)
+
+    KEEP(*(.eh_frame*))
+  } > ITCM
+
+  __exidx_start = .;
+  .ARM.exidx.at_itcm :
+  {
+    *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+  } > ITCM
+  __exidx_end = .;
+
+  .zero.table.at_itcm :
+  {
+    . = ALIGN(4);
+    __zero_table_start__ = .;
+
+    LONG (__bss_start__)
+    LONG ((__bss_end__ - __bss_start__)/4) /* Size is in 32-bit words */
+
+    __zero_table_end__ = .;
+  } > ITCM
+
+  .copy.table.at_itcm :
+  {
+    . = ALIGN(4);
+    __copy_table_start__ = .;
+
+    /* Section to be copied - part 1: any data to be placed in BRAM */
+    LONG (__etext)
+    LONG (__data_start__)
+    LONG ((__data_end__ - __data_start__)/4) /* Size is in 32-bit words */
+
+    /* Section to be copied - part 2: RO data for for DTCM */
+    LONG (__etext2)
+    LONG (__ro_data_start__)
+    LONG ((__ro_data_end__ - __ro_data_start__)/4) /* Size is in 32-bit words */
+
+    __copy_table_end__ = .;
+  } > ITCM
+
+  __itcm_total = ALIGN(4);
+
+  ASSERT( __itcm_total < (ORIGIN(ITCM) + LENGTH(ITCM)), "ITCM overflow")
+
+  .sram :
+  {
+    . = ALIGN(16);
+    /* Cache area (if used) */
+    *(.bss.NoInit.ethos_u_cache)
+    . = ALIGN (16);
+    /* activation buffers a.k.a tensor arena when memory mode sram only or shared sram */
+    *(.bss.NoInit.activation_buf_sram)
+    . = ALIGN(16);
+  } > SRAM AT > SRAM
+
+  .bss :
+  {
+    . = ALIGN(4);
+    __bss_start__ = .;
+    *(.bss)
+    *(.bss.*)
+    *(COMMON)
+    . = ALIGN(4);
+    __bss_end__ = .;
+  } > DTCM AT > DTCM
+
+  .stack (ORIGIN(DTCM) + LENGTH(DTCM) - __STACK_SIZE) (COPY) :
+  {
+    . = ALIGN(8);
+    __StackLimit = .;
+    . = . + __STACK_SIZE;
+    . = ALIGN(8);
+    __StackTop = .;
+  } > DTCM
+  PROVIDE(__stack = __StackTop);
+  ASSERT(
+    (__STACK_SIZE + __bss_end__ - __bss_start__) <= LENGTH(DTCM),
+    "DTCM overflow")
+
+  .ddr.at_ddr :
+  {
+    /* __attribute__((aligned(16))) is not handled by the CMSIS startup code.
+     * Force the alignment here as a workaround */
+    . = ALIGN(16);
+    /* nn model's baked in input matrices */
+    *(ifm)
+    . = ALIGN(16);
+    /* nn model's default space */
+    *(nn_model)
+    . = ALIGN (16);
+    /* labels */
+    *(labels)
+    . = ALIGN (16);
+    /* activation buffers a.k.a tensor arena when memory mode dedicated sram */
+    *(activation_buf_dram)
+    . = ALIGN (16);
+  } > DDR AT > DDR
+
+  /**
+   * Location counter can end up 2byte aligned with narrow Thumb code but
+   * __etext is assumed by startup code to be the LMA of a section in DTCM
+   * which must be 4byte aligned
+   */
+  __etext = ALIGN (4);
+
+  .bram.at_ddr :  AT (__etext)
+  {
+    __data_start__ = .;
+    *(vtable)
+    *(.data)
+    *(.data.*)
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP(*(.preinit_array))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP(*(SORT(.init_array.*)))
+    KEEP(*(.init_array))
+    PROVIDE_HIDDEN (__init_array_end = .);
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP(*(SORT(.fini_array.*)))
+    KEEP(*(.fini_array))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+    KEEP(*(.jcr*))
+    . = ALIGN(4);
+
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+    . = ALIGN(4);
+
+    /**
+     * Place the all ops resolver code data here. This accounts
+     * for ~4k worth of saving on the ITCM load region. It is
+     * only designed to be included (by default) for the inference
+     * runner use case.
+     **/
+    *all_ops_resolver.o (*.text*)
+    . = ALIGN(4);
+    *hal.c.obj (*.text*)
+    . = ALIGN(4);
+
+    __data_end__ = .;
+  } > BRAM
+
+  __etext2 = __etext + (__data_end__ - __data_start__);
+
+  .data.at_ddr : AT (__etext2)
+  {
+    . = ALIGN(4);
+    __ro_data_start__ = .;
+
+    *(.rodata*)
+    . = ALIGN(4);
+    * (npu_driver_version)
+    . = ALIGN(4);
+    * (npu_driver_arch_version)
+    . = ALIGN(4);
+
+    __ro_data_end__ = .;
+  } > BRAM
+
+  .heap (COPY) :
+  {
+    . = ALIGN(8);
+    __end__ = .;
+    PROVIDE(end = .);
+    . = . + __HEAP_SIZE;
+    . = ALIGN(8);
+    __HeapLimit = .;
+  } > BRAM
+
+  ASSERT (
+      (__ro_data_end__ - __ro_data_start__)
+    + (__data_end__  - __data_start__)
+    + __HEAP_SIZE <= LENGTH(BRAM),
+    "BRAM overflow")
+}
diff --git a/scripts/cmake/platforms/mps3/mps3-sse-300.sct b/scripts/cmake/platforms/mps3/mps3-sse-300.sct
new file mode 100644
index 0000000..f78dc25
--- /dev/null
+++ b/scripts/cmake/platforms/mps3/mps3-sse-300.sct
@@ -0,0 +1,145 @@
+;  Copyright (c) 2021 Arm Limited. All rights reserved.
+;  SPDX-License-Identifier: Apache-2.0
+;
+;  Licensed under the Apache License, Version 2.0 (the "License");
+;  you may not use this file except in compliance with the License.
+;  You may obtain a copy of the License at
+;
+;      http://www.apache.org/licenses/LICENSE-2.0
+;
+;  Unless required by applicable law or agreed to in writing, software
+;  distributed under the License is distributed on an "AS IS" BASIS,
+;  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+;  See the License for the specific language governing permissions and
+;  limitations under the License.
+
+; *************************************************************
+; ***       Scatter-Loading Description File                ***
+; *************************************************************
+; Please see docs/sections/appendix.md for memory mapping information.
+;
+; Note: Ethos-U NPU can access BRAM, internal SRAM and the DDR sections => activation buffers and
+;       the model should only be placed in those regions.
+;
+;---------------------------------------------------------
+; First load region (ITCM)
+;---------------------------------------------------------
+LOAD_REGION_0       0x00000000                  0x00080000
+{
+    ;-----------------------------------------------------
+    ; First part of code mem - 512kiB
+    ;-----------------------------------------------------
+    itcm.bin        0x00000000                  0x00080000
+    {
+        *.o (RESET, +First)
+        * (InRoot$$Sections)
+
+        ; Essentially only RO-CODE, RO-DATA is in a
+        ; different region.
+        .ANY (+RO)
+    }
+
+    ;-----------------------------------------------------
+    ; 128kiB of 512kiB DTCM is used for any other RW or ZI
+    ; data. Note: this region is internal to the Cortex-M
+    ; CPU.
+    ;-----------------------------------------------------
+    dtcm.bin        0x20000000                  0x00020000
+    {
+        ; Any R/W and/or zero initialised data
+        .ANY(+RW +ZI)
+    }
+
+    ;-----------------------------------------------------
+    ; 384kiB of stack space within the DTCM region. See
+    ; `dtcm.bin` for the first section. Note: by virtue of
+    ; being part of DTCM, this region is only accessible
+    ; from Cortex-M55.
+    ;-----------------------------------------------------
+    ARM_LIB_STACK   0x20020000 EMPTY ALIGN 8    0x00060000
+    {}
+
+    ;-----------------------------------------------------
+    ; FPGA internal SRAM of 2MiB - reserved for activation
+    ; buffers.
+    ; This region should have 3 cycle read latency from
+    ; both Cortex-M55 and Ethos-U NPU
+    ;-----------------------------------------------------
+    isram.bin       0x31000000  UNINIT ALIGN 16 0x00200000
+    {
+        ; Cache area (if used)
+        *.o (.bss.NoInit.ethos_u_cache)
+
+        ; activation buffers a.k.a tensor arena when
+        ; memory mode sram only or shared sram
+        *.o (.bss.NoInit.activation_buf_sram)
+    }
+}
+
+;---------------------------------------------------------
+; Second load region (DDR)
+;---------------------------------------------------------
+LOAD_REGION_1       0x70000000                  0x02000000
+{
+    ;-----------------------------------------------------
+    ; 32 MiB of DDR space for neural network model,
+    ; input vectors and labels. If the activation buffer
+    ; size required by the network is bigger than the
+    ; SRAM size available, it is accommodated here.
+    ;-----------------------------------------------------
+    ddr.bin        0x70000000 ALIGN 16         0x02000000
+    {
+        ; nn model's baked in input matrices
+        *.o (ifm)
+
+        ; nn model's default space
+        *.o (nn_model)
+
+        ; labels
+        *.o (labels)
+
+        ; activation buffers a.k.a tensor arena when memory mode dedicated sram
+        *.o (activation_buf_dram)
+    }
+
+    ;-----------------------------------------------------
+    ; First 256kiB of BRAM (FPGA SRAM) used for RO data.
+    ; Note: Total BRAM size available is 1MiB.
+    ;-----------------------------------------------------
+    bram.bin        0x11000000          ALIGN 8 0x00040000
+    {
+        ; RO data (incl. unwinding tables for debugging)
+        .ANY (+RO-DATA)
+    }
+
+    ;-----------------------------------------------------
+    ; 768 KiB of remaining part of the 1MiB BRAM used as
+    ; heap space.
+    ;-----------------------------------------------------
+    ARM_LIB_HEAP    0x11040000 EMPTY ALIGN 8    0x000C0000
+    {}
+
+    ;-----------------------------------------------------
+    ; The following regions are for use by the FVP to
+    ; allow loading or dumping of dynamic data into or
+    ; from the memory. These regions are mentioned in
+    ; the CMake subsystem profile. Do not change the
+    ; addresses and sizes below in isolation.
+    ;-----------------------------------------------------
+    ; 32 MiB of model space for run-time load of model
+    ;-----------------------------------------------------
+    runtime_model   0x90000000 EMPTY ALIGN 16   0x02000000
+    {}
+
+    ;-----------------------------------------------------
+    ; 16 MiB of IFM space for run-time loading (FVP only)
+    ;-----------------------------------------------------
+    runtime_ifm     0x92000000 EMPTY ALIGN 16   0x01000000
+    {}
+
+    ;-----------------------------------------------------
+    ; 16 MiB of OFM space for run-time loading (FVP only)
+    ;-----------------------------------------------------
+    runtime_ofm     0x93000000 EMPTY ALIGN 16   0x01000000
+    {}
+}
diff --git a/scripts/cmake/platforms/native/build_configuration.cmake b/scripts/cmake/platforms/native/build_configuration.cmake
new file mode 100644
index 0000000..c87ac89
--- /dev/null
+++ b/scripts/cmake/platforms/native/build_configuration.cmake
@@ -0,0 +1,113 @@
+#----------------------------------------------------------------------------
+#  Copyright (c) 2022 Arm Limited. All rights reserved.
+#  SPDX-License-Identifier: Apache-2.0
+#
+#  Licensed under the Apache License, Version 2.0 (the "License");
+#  you may not use this file except in compliance with the License.
+#  You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+#  Unless required by applicable law or agreed to in writing, software
+#  distributed under the License is distributed on an "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+#  See the License for the specific language governing permissions and
+#  limitations under the License.
+#----------------------------------------------------------------------------
+
+set(TEST_TPIP ${DOWNLOAD_DEP_DIR}/test)
+
+file(MAKE_DIRECTORY ${TEST_TPIP})
+set(TEST_TPIP_INCLUDE ${TEST_TPIP}/include)
+file(MAKE_DIRECTORY ${TEST_TPIP_INCLUDE})
+
+ExternalProject_Add(catch2-headers
+        URL https://github.com/catchorg/Catch2/releases/download/v2.11.1/catch.hpp
+        DOWNLOAD_NO_EXTRACT 1
+        CONFIGURE_COMMAND ""
+        BUILD_COMMAND bash -c "cp -R <DOWNLOAD_DIR>/catch.hpp ${TEST_TPIP_INCLUDE}"
+        INSTALL_COMMAND "")
+
+function(set_platform_global_defaults)
+    message(STATUS "Platform: Native (Linux based x86_64/aarch64 system)")
+    if (NOT DEFINED CMAKE_TOOLCHAIN_FILE)
+        set(CMAKE_TOOLCHAIN_FILE ${CMAKE_TOOLCHAIN_DIR}/native-gcc.cmake
+                CACHE FILEPATH "Toolchain file")
+    endif()
+
+endfunction()
+
+function(platform_custom_post_build)
+    set(oneValueArgs TARGET_NAME)
+    cmake_parse_arguments(PARSED "" "${oneValueArgs}" "" ${ARGN} )
+
+
+    # If native build tests
+    set(TEST_SRC_USE_CASE "")
+    foreach(USE_CASES_TESTS_SEARCH_DIR ${USE_CASES_TESTS_SEARCH_DIR_LIST})
+
+        if (EXISTS ${USE_CASES_TESTS_SEARCH_DIR}/${use_case})
+            message(STATUS "Found tests for use-case ${use_case} at ${USE_CASES_TESTS_SEARCH_DIR}/${use_case}.")
+            set(TEST_SRC_USE_CASE ${USE_CASES_TESTS_SEARCH_DIR})
+            break()
+        endif ()
+    endforeach()
+
+    # Add tests only if they exists for the usecase
+    if (NOT ${TEST_SRC_USE_CASE} STREQUAL "")
+
+        set(TEST_RESOURCES_INCLUDE
+                "${TEST_SRCS}/utils/"
+                "${TEST_SRC_USE_CASE}/${use_case}/include/"
+                )
+
+        # Define Test sources and new target to run unit tests
+        file(GLOB_RECURSE TEST_SOURCES
+                "${TEST_SRCS}/common/*.cpp"
+                "${TEST_SRCS}/common/*.cc"
+                "${TEST_SRCS}/utils/*.cc"
+                "${TEST_SRCS}/utils/*.cpp"
+                "${TEST_SRC_USE_CASE}/${use_case}/*.cpp"
+                "${TEST_SRC_USE_CASE}/${use_case}/*.cc"
+                "${TEST_SRC_USE_CASE}/${use_case}/*.c"
+                "${TEST_SRC_USE_CASE}/${use_case}/**/*.cpp"
+                "${TEST_SRC_USE_CASE}/${use_case}/**/*.cc"
+                "${TEST_SRC_USE_CASE}/${use_case}/**/*.c"
+                )
+
+        set(TEST_SRC_GEN_DIR ${CMAKE_BINARY_DIR}/generated/${use_case}/tests/src)
+        set(TEST_INC_GEN_DIR ${CMAKE_BINARY_DIR}/generated/${use_case}/tests/include)
+        file(MAKE_DIRECTORY ${TEST_SRC_GEN_DIR} ${TEST_INC_GEN_DIR})
+
+        set(${use_case}_DEFAULT_TEST_DATA_DIR ${DEFAULT_TEST_DATA_DIR} CACHE PATH "")
+        # Generate test data files to be included in x86 tests
+        generate_test_data_code(
+                INPUT_DIR "${${use_case}_DEFAULT_TEST_DATA_DIR}"
+                DESTINATION_SRC ${TEST_SRC_GEN_DIR}
+                DESTINATION_HDR ${TEST_INC_GEN_DIR}
+                NAMESPACE "test"
+        )
+
+        file(GLOB_RECURSE TEST_SOURCES_GEN
+                "${TEST_SRC_GEN_DIR}/*.cc"
+                "${TEST_SRC_GEN_DIR}/**/*.cc"
+                )
+        message(STATUS "Adding ${TEST_SOURCES_GEN} to test sources")
+        list(APPEND TEST_SOURCES ${TEST_SOURCES_GEN})
+        list(APPEND TEST_RESOURCES_INCLUDE ${TEST_INC_GEN_DIR})
+
+        set(TEST_TARGET_NAME "${CMAKE_PROJECT_NAME}-${use_case}-tests")
+        add_executable(${TEST_TARGET_NAME} ${TEST_SOURCES})
+        target_include_directories(${TEST_TARGET_NAME} PUBLIC
+                ${TEST_TPIP_INCLUDE} ${TEST_RESOURCES_INCLUDE})
+        target_link_libraries(${TEST_TARGET_NAME} PUBLIC ${UC_LIB_NAME})
+        target_compile_definitions(${TEST_TARGET_NAME} PRIVATE
+                "ACTIVATION_BUF_SZ=${${use_case}_ACTIVATION_BUF_SZ}"
+                TESTS)
+
+        add_dependencies(
+                "${TEST_TARGET_NAME}"
+                "catch2-headers"
+        )
+    endif ()
+endfunction()
\ No newline at end of file
diff --git a/scripts/cmake/platforms/simple_platform/build_configuration.cmake b/scripts/cmake/platforms/simple_platform/build_configuration.cmake
new file mode 100644
index 0000000..3d46884
--- /dev/null
+++ b/scripts/cmake/platforms/simple_platform/build_configuration.cmake
@@ -0,0 +1,59 @@
+#----------------------------------------------------------------------------
+#  Copyright (c) 2022 Arm Limited. All rights reserved.
+#  SPDX-License-Identifier: Apache-2.0
+#
+#  Licensed under the Apache License, Version 2.0 (the "License");
+#  you may not use this file except in compliance with the License.
+#  You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+#  Unless required by applicable law or agreed to in writing, software
+#  distributed under the License is distributed on an "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+#  See the License for the specific language governing permissions and
+#  limitations under the License.
+#----------------------------------------------------------------------------
+
+function(set_platform_global_defaults)
+    message(STATUS "Platform: Simple platform with minimal peripherals")
+    if (NOT DEFINED CMAKE_TOOLCHAIN_FILE)
+        set(CMAKE_TOOLCHAIN_FILE ${CMAKE_TOOLCHAIN_DIR}/bare-metal-gcc.cmake
+                CACHE FILEPATH "Toolchain file")
+    endif()
+    set(LINKER_SCRIPT_NAME  "simple_platform" PARENT_SCOPE)
+    set(PLATFORM_DRIVERS_DIR "${HAL_PLATFORM_DIR}/simple" PARENT_SCOPE)
+endfunction()
+
+function(platform_custom_post_build)
+    set(oneValueArgs TARGET_NAME)
+    cmake_parse_arguments(PARSED "" "${oneValueArgs}" "" ${ARGN} )
+
+    set_target_properties(${PARSED_TARGET_NAME} PROPERTIES SUFFIX ".axf")
+    # Add link options for the linker script to be used:
+
+    add_linker_script(
+        ${PARSED_TARGET_NAME}          # Target
+        ${CMAKE_SCRIPTS_DIR}/platforms/simple_platform    # Directory path
+        ${LINKER_SCRIPT_NAME})  # Name of the file without suffix
+
+    add_target_map_file(
+        ${PARSED_TARGET_NAME}
+        ${CMAKE_RUNTIME_OUTPUT_DIRECTORY}/${PARSED_TARGET_NAME}.map)
+
+    set(SECTORS_DIR ${CMAKE_RUNTIME_OUTPUT_DIRECTORY}/sectors)
+    set(SECTORS_BIN_DIR ${SECTORS_DIR}/${use_case})
+
+    file(REMOVE_RECURSE ${SECTORS_BIN_DIR})
+    file(MAKE_DIRECTORY ${SECTORS_BIN_DIR})
+
+    set(LINKER_SECTION_TAGS     "*.at_itcm" "*.at_ddr")
+    set(LINKER_OUTPUT_BIN_TAGS  "itcm.bin"  "ddr.bin")
+
+    add_bin_generation_command(
+        TARGET_NAME ${PARSED_TARGET_NAME}
+        OUTPUT_DIR  ${SECTORS_BIN_DIR}
+        AXF_PATH    ${CMAKE_RUNTIME_OUTPUT_DIRECTORY}/${PARSED_TARGET_NAME}.axf
+        SECTION_PATTERNS    "${LINKER_SECTION_TAGS}"
+        OUTPUT_BIN_NAMES    "${LINKER_OUTPUT_BIN_TAGS}")
+endfunction()
\ No newline at end of file
diff --git a/scripts/cmake/platforms/simple_platform/simple_platform.ld b/scripts/cmake/platforms/simple_platform/simple_platform.ld
new file mode 100644
index 0000000..82cb18e
--- /dev/null
+++ b/scripts/cmake/platforms/simple_platform/simple_platform.ld
@@ -0,0 +1,270 @@
+/*
+ * Copyright (c) 2021 Arm Limited. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+__STACK_SIZE = 0x00060000;
+__HEAP_SIZE  = 0x000C0000;
+
+/* System memory brief */
+MEMORY
+{
+  ITCM  (rx)  : ORIGIN = 0x00000000, LENGTH = 0x00080000
+  DTCM  (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00080000
+  BRAM  (rwx) : ORIGIN = 0x11000000, LENGTH = 0x00100000
+  SRAM  (rwx) : ORIGIN = 0x31000000, LENGTH = 0x00200000
+  DDR   (rwx) : ORIGIN = 0x70000000, LENGTH = 0x02000000
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions ITCM and RAM.
+ * It references following symbols, which must be defined in code:
+ *   Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ *   __exidx_start
+ *   __exidx_end
+ *   __copy_table_start__
+ *   __copy_table_end__
+ *   __zero_table_start__
+ *   __zero_table_end__
+ *   __etext
+ *   __data_start__
+ *   __preinit_array_start
+ *   __preinit_array_end
+ *   __init_array_start
+ *   __init_array_end
+ *   __fini_array_start
+ *   __fini_array_end
+ *   __data_end__
+ *   __bss_start__
+ *   __bss_end__
+ *   __end__
+ *   end
+ *   __HeapLimit
+ *   __StackLimit
+ *   __StackTop
+ *   __stack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+  .text.at_itcm :
+  {
+    KEEP(*(.vectors))
+
+    /**
+     * All code goes here, with one exception of
+     * all_ops_resolver object file. This code
+     * instead placed on BRAM. See comment in the
+     * BRAM section for details.
+     **/
+    *(EXCLUDE_FILE(*all_ops_resolver.o *hal.c.obj) .text*)
+
+    KEEP(*(.init))
+    KEEP(*(.fini))
+
+    /* .ctors */
+    *crtbegin.o(.ctors)
+    *crtbegin?.o(.ctors)
+    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+    *(SORT(.ctors.*))
+    *(.ctors)
+
+    /* .dtors */
+    *crtbegin.o(.dtors)
+    *crtbegin?.o(.dtors)
+    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+    *(SORT(.dtors.*))
+    *(.dtors)
+
+    KEEP(*(.eh_frame*))
+  } > ITCM
+
+  __exidx_start = .;
+  .ARM.exidx.at_itcm :
+  {
+    *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+  } > ITCM
+  __exidx_end = .;
+
+  .zero.table.at_itcm :
+  {
+    . = ALIGN(4);
+    __zero_table_start__ = .;
+
+    LONG (__bss_start__)
+    LONG ((__bss_end__ - __bss_start__)/4) /* Size is in 32-bit words */
+
+    __zero_table_end__ = .;
+  } > ITCM
+
+  .copy.table.at_itcm :
+  {
+    . = ALIGN(4);
+    __copy_table_start__ = .;
+
+    /* Section to be copied - part 1: any data to be placed in BRAM */
+    LONG (__etext)
+    LONG (__data_start__)
+    LONG ((__data_end__ - __data_start__)/4) /* Size is in 32-bit words */
+
+    /* Section to be copied - part 2: RO data for for DTCM */
+    LONG (__etext2)
+    LONG (__ro_data_start__)
+    LONG ((__ro_data_end__ - __ro_data_start__)/4) /* Size is in 32-bit words */
+
+    __copy_table_end__ = .;
+  } > ITCM
+
+  __itcm_total = ALIGN(4);
+
+  ASSERT( __itcm_total < (ORIGIN(ITCM) + LENGTH(ITCM)), "ITCM overflow")
+
+  .sram :
+  {
+    . = ALIGN(16);
+    /* Cache area (if used) */
+    *(.bss.NoInit.ethos_u_cache)
+    . = ALIGN (16);
+    /* activation buffers a.k.a tensor arena when memory mode sram only or shared sram */
+    *(.bss.NoInit.activation_buf_sram)
+    . = ALIGN(16);
+  } > SRAM AT > SRAM
+
+  .bss :
+  {
+    . = ALIGN(4);
+    __bss_start__ = .;
+    *(.bss)
+    *(.bss.*)
+    *(COMMON)
+    . = ALIGN(4);
+    __bss_end__ = .;
+  } > DTCM AT > DTCM
+
+  .stack (ORIGIN(DTCM) + LENGTH(DTCM) - __STACK_SIZE) (COPY) :
+  {
+    . = ALIGN(8);
+    __StackLimit = .;
+    . = . + __STACK_SIZE;
+    . = ALIGN(8);
+    __StackTop = .;
+  } > DTCM
+  PROVIDE(__stack = __StackTop);
+  ASSERT(
+    (__STACK_SIZE + __bss_end__ - __bss_start__) <= LENGTH(DTCM),
+    "DTCM overflow")
+
+  .ddr.at_ddr :
+  {
+    /* __attribute__((aligned(16))) is not handled by the CMSIS startup code.
+     * Force the alignment here as a workaround */
+    . = ALIGN(16);
+    /* nn model's baked in input matrices */
+    *(ifm)
+    . = ALIGN(16);
+    /* nn model's default space */
+    *(nn_model)
+    . = ALIGN (16);
+    /* labels */
+    *(labels)
+    . = ALIGN (16);
+    /* activation buffers a.k.a tensor arena when memory mode dedicated sram */
+    *(activation_buf_dram)
+    . = ALIGN (16);
+  } > DDR AT > DDR
+
+  /**
+   * Location counter can end up 2byte aligned with narrow Thumb code but
+   * __etext is assumed by startup code to be the LMA of a section in DTCM
+   * which must be 4byte aligned
+   */
+  __etext = ALIGN (4);
+
+  .bram.at_ddr :  AT (__etext)
+  {
+    __data_start__ = .;
+    *(vtable)
+    *(.data)
+    *(.data.*)
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP(*(.preinit_array))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP(*(SORT(.init_array.*)))
+    KEEP(*(.init_array))
+    PROVIDE_HIDDEN (__init_array_end = .);
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP(*(SORT(.fini_array.*)))
+    KEEP(*(.fini_array))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+    KEEP(*(.jcr*))
+    . = ALIGN(4);
+
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+    . = ALIGN(4);
+
+    /**
+     * Place the all ops resolver code data here. This accounts
+     * for ~4k worth of saving on the ITCM load region. It is
+     * only designed to be included (by default) for the inference
+     * runner use case.
+     **/
+    *all_ops_resolver.o (*.text*)
+    . = ALIGN(4);
+    *hal.c.obj (*.text*)
+    . = ALIGN(4);
+
+    __data_end__ = .;
+  } > BRAM
+
+  __etext2 = __etext + (__data_end__ - __data_start__);
+
+  .data.at_ddr : AT (__etext2)
+  {
+    . = ALIGN(4);
+    __ro_data_start__ = .;
+
+    *(.rodata*)
+    . = ALIGN(4);
+    * (npu_driver_version)
+    . = ALIGN(4);
+    * (npu_driver_arch_version)
+    . = ALIGN(4);
+
+    __ro_data_end__ = .;
+  } > BRAM
+
+  .heap (COPY) :
+  {
+    . = ALIGN(8);
+    __end__ = .;
+    PROVIDE(end = .);
+    . = . + __HEAP_SIZE;
+    . = ALIGN(8);
+    __HeapLimit = .;
+  } > BRAM
+
+  ASSERT (
+      (__ro_data_end__ - __ro_data_start__)
+    + (__data_end__  - __data_start__)
+    + __HEAP_SIZE <= LENGTH(BRAM),
+    "BRAM overflow")
+}
diff --git a/scripts/cmake/platforms/simple_platform/simple_platform.sct b/scripts/cmake/platforms/simple_platform/simple_platform.sct
new file mode 100644
index 0000000..5825d47
--- /dev/null
+++ b/scripts/cmake/platforms/simple_platform/simple_platform.sct
@@ -0,0 +1,122 @@
+;  Copyright (c) 2021 Arm Limited. All rights reserved.
+;  SPDX-License-Identifier: Apache-2.0
+;
+;  Licensed under the Apache License, Version 2.0 (the "License");
+;  you may not use this file except in compliance with the License.
+;  You may obtain a copy of the License at
+;
+;      http://www.apache.org/licenses/LICENSE-2.0
+;
+;  Unless required by applicable law or agreed to in writing, software
+;  distributed under the License is distributed on an "AS IS" BASIS,
+;  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+;  See the License for the specific language governing permissions and
+;  limitations under the License.
+
+; *************************************************************
+; ***       Scatter-Loading Description File                ***
+; *************************************************************
+; Please see docs/sections/appendix.md for memory mapping information.
+;
+; Note: Ethos-U NPU can access BRAM, internal SRAM and the DDR
+;       sections => activation buffers and the model should only
+;       be placed in those regions.
+;
+;---------------------------------------------------------
+; First load region (ITCM)
+;---------------------------------------------------------
+LOAD_REGION_0       0x00000000                  0x00080000
+{
+    ;-----------------------------------------------------
+    ; First part of code mem - 512kiB
+    ;-----------------------------------------------------
+    itcm.bin        0x00000000                  0x00080000
+    {
+        *.o (RESET, +First)
+        * (InRoot$$Sections)
+
+        ; Essentially only RO-CODE, RO-DATA is in a
+        ; different region.
+        .ANY (+RO)
+    }
+
+    ;-----------------------------------------------------
+    ; 128kiB of 512kiB DTCM is used for any other RW or ZI
+    ; data. Note: this region is internal to the Cortex-M
+    ; CPU.
+    ;-----------------------------------------------------
+    dtcm.bin        0x20000000                  0x00020000
+    {
+        ; Any R/W and/or zero initialised data
+        .ANY(+RW +ZI)
+    }
+
+    ;-----------------------------------------------------
+    ; 384kiB of stack space within the DTCM region. See
+    ; `dtcm.bin` for the first section. Note: by virtue of
+    ; being part of DTCM, this region is only accessible
+    ; from Cortex-M55.
+    ;-----------------------------------------------------
+    ARM_LIB_STACK   0x20020000 EMPTY ALIGN 8    0x00060000
+    {}
+
+    ;-----------------------------------------------------
+    ; SSE-300's internal SRAM of 2MiB - reserved for
+    ; activation buffers.
+    ; This region should have 3 cycle read latency from
+    ; both Cortex-M55 and Ethos-U NPU
+    ;-----------------------------------------------------
+    isram.bin       0x31000000  UNINIT ALIGN 16 0x00200000
+    {
+        ; Cache area (if used)
+        *.o (.bss.NoInit.ethos_u_cache)
+
+        ; activation buffers a.k.a tensor arena when
+        ; memory mode sram only or shared sram
+        *.o (.bss.NoInit.activation_buf_sram)
+    }
+}
+
+;---------------------------------------------------------
+; Second load region (DDR)
+;---------------------------------------------------------
+LOAD_REGION_1       0x70000000                  0x02000000
+{
+    ;-----------------------------------------------------
+    ; 32 MiB of DDR space for neural network model,
+    ; input vectors and labels. If the activation buffer
+    ; size required by the network is bigger than the
+    ; SRAM size available, it is accommodated here.
+    ;-----------------------------------------------------
+    ddr.bin        0x70000000 ALIGN 16         0x02000000
+    {
+        ; nn model's baked in input matrices
+        *.o (ifm)
+
+        ; nn model's default space
+        *.o (nn_model)
+
+        ; labels
+        *.o (labels)
+
+        ; activation buffers a.k.a tensor arena when memory mode dedicated sram
+        *.o (activation_buf_dram)
+    }
+
+    ;-----------------------------------------------------
+    ; First 256kiB of BRAM (FPGA SRAM) used for RO data.
+    ; Note: Total BRAM size available is 1MiB.
+    ;-----------------------------------------------------
+    bram.bin        0x11000000          ALIGN 8 0x00040000
+    {
+        ; RO data (incl. unwinding tables for debugging)
+        .ANY (+RO-DATA)
+    }
+
+    ;-----------------------------------------------------
+    ; 768 KiB of remaining part of the 1MiB BRAM used as
+    ; heap space.
+    ;-----------------------------------------------------
+    ARM_LIB_HEAP    0x11040000 EMPTY ALIGN 8    0x000C0000
+    {}
+}
diff --git a/scripts/cmake/subsystem-profiles/corstone-sse-300.cmake b/scripts/cmake/subsystem-profiles/corstone-sse-300.cmake
deleted file mode 100644
index eec6fde..0000000
--- a/scripts/cmake/subsystem-profiles/corstone-sse-300.cmake
+++ /dev/null
@@ -1,319 +0,0 @@
-#----------------------------------------------------------------------------
-#  Copyright (c) 2021 Arm Limited. All rights reserved.
-#  SPDX-License-Identifier: Apache-2.0
-#
-#  Licensed under the Apache License, Version 2.0 (the "License");
-#  you may not use this file except in compliance with the License.
-#  You may obtain a copy of the License at
-#
-#      http://www.apache.org/licenses/LICENSE-2.0
-#
-#  Unless required by applicable law or agreed to in writing, software
-#  distributed under the License is distributed on an "AS IS" BASIS,
-#  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-#  See the License for the specific language governing permissions and
-#  limitations under the License.
-#----------------------------------------------------------------------------
-
-# CMake configuration file for peripheral memory map for MPS3 as per SSE-300 design
-###################################################################################################
-#                                         Mem sizes                                               #
-###################################################################################################
-set(ITCM_SIZE             "0x00080000" CACHE STRING "ITCM size:       512 kiB")
-set(DTCM_BLK_SIZE         "0x00020000" CACHE STRING "DTCM size:       128 kiB, 4 banks")
-set(BRAM_SIZE             "0x00100000" CACHE STRING "BRAM size:         1 MiB")
-set(ISRAM0_SIZE           "0x00100000" CACHE STRING "ISRAM0 size:       1 MiB")
-set(ISRAM1_SIZE           "0x00100000" CACHE STRING "ISRAM1 size:       1 MiB")
-set(QSPI_SRAM_SIZE        "0x00800000" CACHE STRING "QSPI Flash size:   8 MiB")
-set(DDR4_BLK_SIZE         "0x10000000" CACHE STRING "DDR4 block size: 256 MiB")
-
-###################################################################################################
-#                                Base addresses for memory regions                                #
-###################################################################################################
-set(ITCM_BASE_NS          "0x00000000" CACHE STRING "Instruction TCM Non-Secure base address")
-set(BRAM_BASE_NS          "0x01000000" CACHE STRING "CODE SRAM Non-Secure base address")
-set(DTCM0_BASE_NS         "0x20000000" CACHE STRING "Data TCM block 0 Non-Secure base address")
-set(DTCM1_BASE_NS         "0x20020000" CACHE STRING "Data TCM block 1 Non-Secure base address")
-set(DTCM2_BASE_NS         "0x20040000" CACHE STRING "Data TCM block 2 Non-Secure base address")
-set(DTCM3_BASE_NS         "0x20060000" CACHE STRING "Data TCM block 3 Non-Secure base address")
-set(ISRAM0_BASE_NS        "0x21000000" CACHE STRING "Internal SRAM Area Non-Secure base address")
-set(ISRAM1_BASE_NS        "0x21100000" CACHE STRING "Internal SRAM Area Non-Secure base address")
-set(QSPI_SRAM_BASE_NS     "0x28000000" CACHE STRING "QSPI SRAM Non-Secure base address")
-set(DDR4_BLK0_BASE_NS     "0x60000000" CACHE STRING "DDR4 block 0 Non-Secure base address")
-set(DDR4_BLK1_BASE_NS     "0x80000000" CACHE STRING "DDR4 block 1 Non-Secure base address")
-set(DDR4_BLK2_BASE_NS     "0xA0000000" CACHE STRING "DDR4 block 2 Non-Secure base address")
-set(DDR4_BLK3_BASE_NS     "0xC0000000" CACHE STRING "DDR4 block 3 Non-Secure base address")
-
-set(ITCM_BASE_S           "0x10000000" CACHE STRING "Instruction TCM Secure base address")
-set(BRAM_BASE_S           "0x11000000" CACHE STRING "CODE SRAM Secure base address")
-set(DTCM0_BASE_S          "0x30000000" CACHE STRING "Data TCM block 0 Secure base address")
-set(DTCM1_BASE_S          "0x30020000" CACHE STRING "Data TCM block 1 Secure base address")
-set(DTCM2_BASE_S          "0x30040000" CACHE STRING "Data TCM block 2 Secure base address")
-set(DTCM3_BASE_S          "0x30060000" CACHE STRING "Data TCM block 3 Secure base address")
-set(ISRAM0_BASE_S         "0x31000000" CACHE STRING "Internal SRAM Area Secure base address")
-set(ISRAM1_BASE_S         "0x31100000" CACHE STRING "Internal SRAM Area Secure base address")
-set(QSPI_SRAM_BASE_S      "0x38000000" CACHE STRING "QSPI SRAM Non-Secure base address")
-set(DDR4_BLK0_BASE_S      "0x70000000" CACHE STRING "DDR4 block 0 Secure base address")
-set(DDR4_BLK1_BASE_S      "0x90000000" CACHE STRING "DDR4 block 1 Secure base address")
-set(DDR4_BLK2_BASE_S      "0xB0000000" CACHE STRING "DDR4 block 2 Secure base address")
-set(DDR4_BLK3_BASE_S      "0xD0000000" CACHE STRING "DDR4 block 3 Secure base address")
-
-###################################################################################################
-#                              Application specific config                                        #
-###################################################################################################
-set(APP_NOTE               "AN552")
-set(DESIGN_NAME            "Arm Corstone-300 - ${APP_NOTE}" CACHE STRING "Design name")
-
-# The following parameter is based on the linker/scatter script for SSE-300.
-# Do not change this parameter in isolation.
-# SRAM size reserved for activation buffers
-math(EXPR ACTIVATION_BUF_SRAM_SZ "${ISRAM0_SIZE} + ${ISRAM1_SIZE}" OUTPUT_FORMAT HEXADECIMAL)
-
-###################################################################################################
-#           Base addresses for dynamic loads (to be used for FVP form only)                       #
-###################################################################################################
-# This parameter is also mentioned in the linker/scatter script for SSE-300. Do not change these
-# parameters in isolation.
-set(DYNAMIC_MODEL_BASE      "${DDR4_BLK1_BASE_S}" CACHE STRING
-                            "Region to be used for dynamic load of model into memory")
-set(DYNAMIC_MODEL_SIZE      "0x02000000" CACHE STRING "Size of the space reserved for the model")
-math(EXPR DYNAMIC_IFM_BASE  "${DYNAMIC_MODEL_BASE} + ${DYNAMIC_MODEL_SIZE}" OUTPUT_FORMAT HEXADECIMAL)
-set(DYNAMIC_IFM_SIZE        "0x01000000" CACHE STRING "Size of the space reserved for the IFM")
-math(EXPR DYNAMIC_OFM_BASE  "${DYNAMIC_IFM_BASE} + ${DYNAMIC_IFM_SIZE}" OUTPUT_FORMAT HEXADECIMAL)
-set(DYNAMIC_OFM_SIZE        "0x01000000" CACHE STRING "Size of the space reserved for the OFM")
-
-###################################################################################################
-#                     Base addresses for peripherals - non secure                                 #
-###################################################################################################
-set(CMSDK_GPIO0_BASE      "0x41100000" CACHE STRING "User GPIO 0 Base Address (4KB)")
-set(CMSDK_GPIO1_BASE      "0x41101000" CACHE STRING "User GPIO 1 Base Address (4KB)")
-set(CMSDK_GPIO2_BASE      "0x41102000" CACHE STRING "User GPIO 2 Base Address (4KB)")
-set(CMSDK_GPIO3_BASE      "0x41103000" CACHE STRING "User GPIO 3 Base Address (4KB)")
-set(FMC_CMDSK_GPIO_BASE0  "0x41104000" CACHE STRING "FMC CMDSK GPIO 0 Base Address (4KB)")
-set(FMC_CMDSK_GPIO_BASE1  "0x41105000" CACHE STRING "FMC CMDSK GPIO 1 Base Address (4KB)")
-set(FMC_CMDSK_GPIO_BASE2  "0x41106000" CACHE STRING "FMC CMDSK GPIO 2 Base Address (4KB)")
-set(FMC_USER_AHB_BASE     "0x41107000" CACHE STRING "FMC USER AHB Base Address (4KB)")
-set(DMA0_BASE             "0x41200000" CACHE STRING "DMA0 ExternalManager0 (4KB)")
-set(DMA1_BASE             "0x41201000" CACHE STRING "DMA1 ExternalManager1 (4KB)")
-set(DMA2_BASE             "0x41202000" CACHE STRING "DMA2 ExternalManager2 (4KB)")
-set(DMA3_BASE             "0x41203000" CACHE STRING "DMA3 ExternalManager3 (4KB)")
-
-set(SMSC9220_BASE         "0x41400000" CACHE STRING "Ethernet SMSC9220 Base Address (1MB)")
-set(USB_BASE              "0x41500000" CACHE STRING "USB Base Address (1MB)")
-
-set(USER_APB0_BASE        "0x41700000" CACHE STRING "User APB0")
-set(USER_APB1_BASE        "0x41701000" CACHE STRING "User APB1")
-set(USER_APB2_BASE        "0x41702000" CACHE STRING "User APB2")
-set(USER_APB3_BASE        "0x41703000" CACHE STRING "User APB3")
-
-set(QSPI_XIP_BASE         "0x41800000" CACHE STRING "QSPI XIP config Base Address ")
-set(QSPI_WRITE_BASE       "0x41801000" CACHE STRING "QSPI write config Base Address ")
-
-if (ETHOS_U_NPU_ENABLED)
-    set(ETHOS_U_NPU_BASE        "0x48102000" CACHE STRING "Ethos-U NPU base address")
-    set(ETHOS_U_NPU_TA0_BASE    "0x48103000" CACHE STRING "Ethos-U NPU's timing adapter 0 base address")
-    set(ETHOS_U_NPU_TA1_BASE    "0x48103200" CACHE STRING "Ethos-U NPU's timing adapter 1 base address")
-endif (ETHOS_U_NPU_ENABLED)
-
-set(MPS3_I2C0_BASE        "0x49200000" CACHE STRING "Touch Screen I2C Base Address ")
-set(MPS3_I2C1_BASE        "0x49201000" CACHE STRING "Audio Interface I2C Base Address ")
-set(MPS3_SSP2_BASE        "0x49202000" CACHE STRING "ADC SPI PL022 Base Address")
-set(MPS3_SSP3_BASE        "0x49203000" CACHE STRING "Shield 0 SPI PL022 Base Address")
-set(MPS3_SSP4_BASE        "0x49204000" CACHE STRING "Shield 1 SPI PL022 Base Address")
-set(MPS3_I2C2_BASE        "0x49205000" CACHE STRING "Shield 0 SBCon Base Address ")
-set(MPS3_I2C3_BASE        "0x49206000" CACHE STRING "Shield 1 SBCon Base Address ")
-
-set(USER_APB_BASE         "0x49207000" CACHE STRING "User APB")
-set(MPS3_I2C5_BASE        "0x49208000" CACHE STRING "DDR EPROM I2C SBCon Base Address ")
-
-set(MPS3_SCC_BASE         "0x49300000" CACHE STRING "SCC Base Address ")
-set(MPS3_AAIC_I2S_BASE    "0x49301000" CACHE STRING "Audio Interface I2S Base Address ")
-set(MPS3_FPGAIO_BASE      "0x49302000" CACHE STRING "FPGA IO Base Address ")
-
-set(CMSDK_UART0_BASE      "0x49303000" CACHE STRING "UART 0 Base Address ")
-set(CMSDK_UART1_BASE      "0x49304000" CACHE STRING "UART 1 Base Address ")
-set(CMSDK_UART2_BASE      "0x49305000" CACHE STRING "UART 2 Base Address ")
-set(CMSDK_UART3_BASE      "0x49306000" CACHE STRING "UART 3 Base Address Shield 0")
-set(CMSDK_UART4_BASE      "0x49307000" CACHE STRING "UART 4 Base Address Shield 1")
-set(CMSDK_UART5_BASE      "0x49308000" CACHE STRING "UART 5 Base Address ")
-
-set(CLCD_CONFIG_BASE      "0x4930A000" CACHE STRING "CLCD CONFIG Base Address ")
-set(RTC_BASE              "0x4930B000" CACHE STRING "RTC Base address ")
-
-###################################################################################################
-#                     Base addresses for peripherals - secure                                     #
-###################################################################################################
-set(SEC_CMSDK_GPIO0_BASE   "0x51100000" CACHE STRING "User GPIO 0 Base Address (4KB)")
-set(SEC_CMSDK_GPIO1_BASE   "0x51101000" CACHE STRING "User GPIO 1 Base Address (4KB)")
-set(SEC_CMSDK_GPIO2_BASE   "0x51102000" CACHE STRING "User GPIO 2 Base Address (4KB)")
-set(SEC_CMSDK_GPIO3_BASE   "0x51103000" CACHE STRING "User GPIO 3 Base Address (4KB)")
-
-set(SEC_AHB_USER0_BASE     "0x51104000" CACHE STRING "AHB USER 0 Base Address (4KB)")
-set(SEC_AHB_USER1_BASE     "0x51105000" CACHE STRING "AHB USER 1 Base Address (4KB)")
-set(SEC_AHB_USER2_BASE     "0x51106000" CACHE STRING "AHB USER 2 Base Address (4KB)")
-set(SEC_AHB_USER3_BASE     "0x51107000" CACHE STRING "AHB USER 3 Base Address (4KB)")
-
-set(SEC_DMA0_BASE          "0x51200000" CACHE STRING "DMA0 ExternalManager0 (4KB)")
-set(SEC_DMA1_BASE          "0x51201000" CACHE STRING "DMA1 ExternalManager1 (4KB)")
-set(SEC_DMA2_BASE          "0x51202000" CACHE STRING "DMA2 ExternalManager2 (4KB)")
-set(SEC_DMA3_BASE          "0x51203000" CACHE STRING "DMA3 ExternalManager3 (4KB)")
-
-set(SEC_SMSC9220_BASE      "0x51400000" CACHE STRING "Ethernet SMSC9220 Base Address (1MB)")
-set(SEC_USB_BASE           "0x51500000" CACHE STRING "USB Base Address (1MB)")
-
-set(SEC_USER_APB0_BASE     "0x51700000" CACHE STRING "User APB0 Base Address")
-set(SEC_USER_APB1_BASE     "0x51701000" CACHE STRING "User APB1 Base Address")
-set(SEC_USER_APB2_BASE     "0x51702000" CACHE STRING "User APB2 Base Address")
-set(SEC_USER_APB3_BASE     "0x51703000" CACHE STRING "User APB3 Base Address")
-
-set(SEC_QSPI_XIP_BASE      "0x51800000" CACHE STRING "QSPI XIP config Base Address ")
-set(SEC_QSPI_WRITE_BASE    "0x51801000" CACHE STRING "QSPI write config Base Address ")
-
-if (ETHOS_U_NPU_ENABLED)
-    set(SEC_ETHOS_U_NPU_BASE     "0x58102000" CACHE STRING "Ethos-U NPU base address")
-    set(SEC_ETHOS_U_NPU_TA0_BASE "0x58103000" CACHE STRING "Ethos-U NPU's timing adapter 0 base address")
-    set(SEC_ETHOS_U_NPU_TA1_BASE "0x58103200" CACHE STRING "Ethos-U NPU's timing adapter 1 base address")
-endif (ETHOS_U_NPU_ENABLED)
-
-set(SEC_MPS3_I2C0_BASE     "0x59200000" CACHE STRING "Touch Screen I2C Base Address ")
-set(SEC_MPS3_I2C1_BASE     "0x59201000" CACHE STRING "Audio Interface I2C Base Address ")
-set(SEC_MPS3_SSP2_BASE     "0x59202000" CACHE STRING "ADC SPI PL022 Base Address")
-set(SEC_MPS3_SSP3_BASE     "0x59203000" CACHE STRING "Shield 0 SPI PL022 Base Address")
-set(SEC_MPS3_SSP4_BASE     "0x59204000" CACHE STRING "Shield 1 SPI PL022 Base Address")
-set(SEC_MPS3_I2C2_BASE     "0x59205000" CACHE STRING "Shield 0 SBCon Base Address ")
-set(SEC_MPS3_I2C3_BASE     "0x59206000" CACHE STRING "Shield 1 SBCon Base Address ")
-set(SEC_USER_APB_BASE      "0x59207000" CACHE STRING "User APB Base Address")
-set(SEC_MPS3_I2C5_BASE     "0x59208000" CACHE STRING "DDR EPROM I2C SBCon Base Address ")
-
-set(SEC_MPS3_SCC_BASE         "0x59300000" CACHE STRING "SCC Base Address ")
-set(SEC_MPS3_AAIC_I2S_BASE    "0x59301000" CACHE STRING "Audio Interface I2S Base Address ")
-set(SEC_MPS3_FPGAIO_BASE      "0x59302000" CACHE STRING "FPGA IO Base Address ")
-
-set(SEC_CMSDK_UART0_BASE      "0x59303000" CACHE STRING "UART 0 Base Address ")
-set(SEC_CMSDK_UART1_BASE      "0x59304000" CACHE STRING "UART 1 Base Address ")
-set(SEC_CMSDK_UART2_BASE      "0x59305000" CACHE STRING "UART 2 Base Address ")
-set(SEC_CMSDK_UART3_BASE      "0x59306000" CACHE STRING "UART 3 Base Address Shield 0")
-set(SEC_CMSDK_UART4_BASE      "0x59307000" CACHE STRING "UART 4 Base Address Shield 1")
-set(SEC_CMSDK_UART5_BASE      "0x59308000" CACHE STRING "UART 5 Base Address ")
-
-set(SEC_CLCD_CONFIG_BASE      "0x5930A000" CACHE STRING "CLCD CONFIG Base Address ")
-set(SEC_RTC_BASE              "0x5930B000" CACHE STRING "RTC Base address ")
-
-###################################################################################################
-#                                           MPCs                                                  #
-###################################################################################################
-set(MPC_ISRAM0_BASE_S     "0x50083000" CACHE STRING "ISRAM0 Memory Protection Controller Secure base address")
-set(MPC_ISRAM1_BASE_S     "0x50084000" CACHE STRING "ISRAM1 Memory Protection Controller Secure base address")
-set(MPC_BRAM_BASE_S       "0x57000000" CACHE STRING "SRAM Memory Protection Controller Secure base address")
-set(MPC_QSPI_BASE_S       "0x57001000" CACHE STRING "QSPI Memory Protection Controller Secure base address")
-set(MPC_DDR4_BASE_S       "0x57002000" CACHE STRING "DDR4 Memory Protection Controller Secure base address")
-
-###################################################################################################
-#                                           IRQ numbers                                           #
-###################################################################################################
-set(NONSEC_WATCHDOG_RESET_IRQn    " 0" CACHE STRING " Non-Secure Watchdog Reset Interrupt")
-set(NONSEC_WATCHDOG_IRQn          " 1" CACHE STRING " Non-Secure Watchdog Interrupt         ")
-set(S32K_TIMER_IRQn               " 2" CACHE STRING " S32K SLOWCLK Timer Interrupt          ")
-set(TIMER0_IRQn                   " 3" CACHE STRING " TIMER 0 Interrupt                     ")
-set(TIMER1_IRQn                   " 4" CACHE STRING " TIMER 1 Interrupt                     ")
-set(TIMER2_IRQn                   " 5" CACHE STRING " TIMER 2 Interrupt                     ")
-set(MPC_IRQn                      " 9" CACHE STRING " MPC Combined (Secure) Interrupt       ")
-set(PPC_IRQn                      "10" CACHE STRING " PPC Combined (Secure) Interrupt       ")
-set(MSC_IRQn                      "11" CACHE STRING " MSC Combined (Secure) Interrput       ")
-set(BRIDGE_ERROR_IRQn             "12" CACHE STRING " Bridge Error Combined (Secure) Interrupt ")
-set(MGMT_PPU_IRQn                 "14" CACHE STRING " MGMT_PPU" )
-set(SYS_PPU_IRQn                  "15" CACHE STRING " SYS_PPU" )
-set(CPU0_PPU_IRQn                 "16" CACHE STRING " CPU0_PPU" )
-set(DEBUG_PPU_IRQn                "26" CACHE STRING " DEBUG_PPU" )
-set(TIMER3_AON_IRQn               "27" CACHE STRING " TIMER3_AON" )
-set(CPU0CTIIQ0_IRQn               "28" CACHE STRING " CPU0CTIIQ0" )
-set(CPU0CTIIQ01_IRQn              "29" CACHE STRING " CPU0CTIIQ01" )
-
-set(SYS_TSTAMP_COUNTER_IRQn       "32" CACHE STRING " System timestamp counter interrupt    ")
-set(UARTRX0_IRQn                  "33" CACHE STRING " UART 0 RX Interrupt                   ")
-set(UARTTX0_IRQn                  "34" CACHE STRING " UART 0 TX Interrupt                   ")
-set(UARTRX1_IRQn                  "35" CACHE STRING " UART 1 RX Interrupt                   ")
-set(UARTTX1_IRQn                  "36" CACHE STRING " UART 1 TX Interrupt                   ")
-set(UARTRX2_IRQn                  "37" CACHE STRING " UART 2 RX Interrupt                   ")
-set(UARTTX2_IRQn                  "38" CACHE STRING " UART 2 TX Interrupt                   ")
-set(UARTRX3_IRQn                  "39" CACHE STRING " UART 3 RX Interrupt                   ")
-set(UARTTX3_IRQn                  "40" CACHE STRING " UART 3 TX Interrupt                   ")
-set(UARTRX4_IRQn                  "41" CACHE STRING " UART 4 RX Interrupt                   ")
-set(UARTTX4_IRQn                  "42" CACHE STRING " UART 4 TX Interrupt                   ")
-set(UART0_IRQn                    "43" CACHE STRING " UART 0 combined Interrupt             ")
-set(UART1_IRQn                    "44" CACHE STRING " UART 1 combined Interrupt             ")
-set(UART2_IRQn                    "45" CACHE STRING " UART 2 combined Interrupt             ")
-set(UART3_IRQn                    "46" CACHE STRING " UART 3 combined Interrupt             ")
-set(UART4_IRQn                    "47" CACHE STRING " UART 4 combined Interrupt             ")
-set(UARTOVF_IRQn                  "48" CACHE STRING " UART 0,1,2,3,4 Overflow Interrupt     ")
-set(ETHERNET_IRQn                 "49" CACHE STRING " Ethernet Interrupt                    ")
-set(I2S_IRQn                      "50" CACHE STRING " Audio I2S Interrupt                   ")
-set(TSC_IRQn                      "51" CACHE STRING " Touch Screen Interrupt                ")
-set(USB_IRQn                      "52" CACHE STRING " USB Interrupt                         ")
-set(SPI2_IRQn                     "53" CACHE STRING " ADC (SPI) Interrupt                   ")
-set(SPI3_IRQn                     "54" CACHE STRING " SPI 3 Interrupt (Shield 0)            ")
-set(SPI4_IRQn                     "55" CACHE STRING " SPI 4 Interrupt (Sheild 1)            ")
-
-if (ETHOS_U_NPU_ENABLED)
-set(EthosU_IRQn                   "56" CACHE STRING " Ethos-U55 Interrupt                   ")
-endif ()
-
-set(GPIO0_IRQn                    "69" CACHE STRING " GPIO 0 Combined Interrupt             ")
-set(GPIO1_IRQn                    "70" CACHE STRING " GPIO 1 Combined Interrupt             ")
-set(GPIO2_IRQn                    "71" CACHE STRING " GPIO 2 Combined Interrupt             ")
-set(GPIO3_IRQn                    "72" CACHE STRING " GPIO 3 Combined Interrupt             ")
-set(GPIO0_0_IRQn                  "73" CACHE STRING "")
-set(GPIO0_1_IRQn                  "74" CACHE STRING "")
-set(GPIO0_2_IRQn                  "75" CACHE STRING "")
-set(GPIO0_3_IRQn                  "76" CACHE STRING "")
-set(GPIO0_4_IRQn                  "77" CACHE STRING "")
-set(GPIO0_5_IRQn                  "78" CACHE STRING "")
-set(GPIO0_6_IRQn                  "79" CACHE STRING "")
-set(GPIO0_7_IRQn                  "80" CACHE STRING "")
-set(GPIO0_8_IRQn                  "81" CACHE STRING "")
-set(GPIO0_9_IRQn                  "82" CACHE STRING "")
-set(GPIO0_10_IRQn                 "83" CACHE STRING "")
-set(GPIO0_11_IRQn                 "84" CACHE STRING "")
-set(GPIO0_12_IRQn                 "85" CACHE STRING "")
-set(GPIO0_13_IRQn                 "86" CACHE STRING "")
-set(GPIO0_14_IRQn                 "87" CACHE STRING "")
-set(GPIO0_15_IRQn                 "88" CACHE STRING "")
-set(GPIO1_0_IRQn                  "89" CACHE STRING "")
-set(GPIO1_1_IRQn                  "90" CACHE STRING "")
-set(GPIO1_2_IRQn                  "91" CACHE STRING "")
-set(GPIO1_3_IRQn                  "92" CACHE STRING "")
-set(GPIO1_4_IRQn                  "93" CACHE STRING "")
-set(GPIO1_5_IRQn                  "94" CACHE STRING "")
-set(GPIO1_6_IRQn                  "95" CACHE STRING "")
-set(GPIO1_7_IRQn                  "96" CACHE STRING "")
-set(GPIO1_8_IRQn                  "97" CACHE STRING "")
-set(GPIO1_9_IRQn                  "98" CACHE STRING "")
-set(GPIO1_10_IRQn                 "99" CACHE STRING "")
-set(GPIO1_11_IRQn                 "100" CACHE STRING "")
-set(GPIO1_12_IRQn                 "101" CACHE STRING "")
-set(GPIO1_13_IRQn                 "102" CACHE STRING "")
-set(GPIO1_14_IRQn                 "103" CACHE STRING "")
-set(GPIO1_15_IRQn                 "104" CACHE STRING "")
-set(GPIO2_0_IRQn                  "105" CACHE STRING "")
-set(GPIO2_1_IRQn                  "106" CACHE STRING "")
-set(GPIO2_2_IRQn                  "107" CACHE STRING "")
-set(GPIO2_3_IRQn                  "108" CACHE STRING "")
-set(GPIO2_4_IRQn                  "109" CACHE STRING "")
-set(GPIO2_5_IRQn                  "110" CACHE STRING "")
-set(GPIO2_6_IRQn                  "111" CACHE STRING "")
-set(GPIO2_7_IRQn                  "112" CACHE STRING "")
-set(GPIO2_8_IRQn                  "113" CACHE STRING "")
-set(GPIO2_9_IRQn                  "114" CACHE STRING "")
-set(GPIO2_10_IRQn                 "115" CACHE STRING "")
-set(GPIO2_11_IRQn                 "116" CACHE STRING "")
-set(GPIO2_12_IRQn                 "117" CACHE STRING "")
-set(GPIO2_13_IRQn                 "118" CACHE STRING "")
-set(GPIO2_14_IRQn                 "119" CACHE STRING "")
-set(GPIO2_15_IRQn                 "120" CACHE STRING "")
-set(GPIO3_0_IRQn                  "121" CACHE STRING "")
-set(GPIO3_1_IRQn                  "122" CACHE STRING "")
-set(GPIO3_2_IRQn                  "123" CACHE STRING "")
-set(GPIO3_3_IRQn                  "124" CACHE STRING "")
-set(UARTRX5_IRQn                  "125" CACHE STRING "UART 5 RX Interrupt")
-set(UARTTX5_IRQn                  "126" CACHE STRING "UART 5 TX Interrupt")
-set(UART5_IRQn                    "127" CACHE STRING "UART 5 combined Interrupt")
diff --git a/scripts/cmake/subsystem-profiles/simple_platform.cmake b/scripts/cmake/subsystem-profiles/simple_platform.cmake
deleted file mode 100644
index e6cfef3..0000000
--- a/scripts/cmake/subsystem-profiles/simple_platform.cmake
+++ /dev/null
@@ -1,93 +0,0 @@
-#----------------------------------------------------------------------------
-#  Copyright (c) 2021 Arm Limited. All rights reserved.
-#  SPDX-License-Identifier: Apache-2.0
-#
-#  Licensed under the Apache License, Version 2.0 (the "License");
-#  you may not use this file except in compliance with the License.
-#  You may obtain a copy of the License at
-#
-#      http://www.apache.org/licenses/LICENSE-2.0
-#
-#  Unless required by applicable law or agreed to in writing, software
-#  distributed under the License is distributed on an "AS IS" BASIS,
-#  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-#  See the License for the specific language governing permissions and
-#  limitations under the License.
-#----------------------------------------------------------------------------
-
-# CMake configuration file for peripheral memory map for simple platform. This is a stripped down
-# version of Arm Corstone-300 platform with minimal peripherals to be able to use Ethos-U55. However,
-# for ease of integration with Arm FastModel Tools, it uses PL011 as the UART component instead of
-# the CMSDK UART block used by the MPS3 FPGA and FVP implementations.
-###################################################################################################
-#                                         Mem sizes                                               #
-###################################################################################################
-set(ITCM_SIZE             "0x00080000" CACHE STRING "ITCM size:       512 kiB")
-set(DTCM_BLK_SIZE         "0x00020000" CACHE STRING "DTCM size:       128 kiB, 4 banks")
-set(BRAM_SIZE             "0x00100000" CACHE STRING "BRAM size:         1 MiB")
-set(ISRAM0_SIZE           "0x00100000" CACHE STRING "ISRAM0 size:       1 MiB")
-set(ISRAM1_SIZE           "0x00100000" CACHE STRING "ISRAM1 size:       1 MiB")
-set(DDR4_BLK_SIZE         "0x10000000" CACHE STRING "DDR4 block size: 256 MiB")
-
-###################################################################################################
-#                                Base addresses for memory regions                                #
-###################################################################################################
-set(ITCM_BASE_NS          "0x00000000" CACHE STRING "Instruction TCM Non-Secure base address")
-set(BRAM_BASE_NS          "0x01000000" CACHE STRING "CODE SRAM Non-Secure base address")
-set(DTCM0_BASE_NS         "0x20000000" CACHE STRING "Data TCM block 0 Non-Secure base address")
-set(DTCM1_BASE_NS         "0x20020000" CACHE STRING "Data TCM block 1 Non-Secure base address")
-set(DTCM2_BASE_NS         "0x20040000" CACHE STRING "Data TCM block 2 Non-Secure base address")
-set(DTCM3_BASE_NS         "0x20060000" CACHE STRING "Data TCM block 3 Non-Secure base address")
-set(ISRAM0_BASE_NS        "0x21000000" CACHE STRING "Internal SRAM Area Non-Secure base address")
-set(ISRAM1_BASE_NS        "0x21100000" CACHE STRING "Internal SRAM Area Non-Secure base address")
-set(QSPI_SRAM_BASE_NS     "0x28000000" CACHE STRING "QSPI SRAM Non-Secure base address")
-set(DDR4_BLK0_BASE_NS     "0x60000000" CACHE STRING "DDR4 block 0 Non-Secure base address")
-set(DDR4_BLK1_BASE_NS     "0x80000000" CACHE STRING "DDR4 block 1 Non-Secure base address")
-set(DDR4_BLK2_BASE_NS     "0xA0000000" CACHE STRING "DDR4 block 2 Non-Secure base address")
-set(DDR4_BLK3_BASE_NS     "0xC0000000" CACHE STRING "DDR4 block 3 Non-Secure base address")
-
-set(ITCM_BASE_S           "0x10000000" CACHE STRING "Instruction TCM Secure base address")
-set(BRAM_BASE_S           "0x11000000" CACHE STRING "CODE SRAM Secure base address")
-set(DTCM0_BASE_S          "0x30000000" CACHE STRING "Data TCM block 0 Secure base address")
-set(DTCM1_BASE_S          "0x30020000" CACHE STRING "Data TCM block 1 Secure base address")
-set(DTCM2_BASE_S          "0x30040000" CACHE STRING "Data TCM block 2 Secure base address")
-set(DTCM3_BASE_S          "0x30060000" CACHE STRING "Data TCM block 3 Secure base address")
-set(ISRAM0_BASE_S         "0x31000000" CACHE STRING "Internal SRAM Area Secure base address")
-set(ISRAM1_BASE_S         "0x31100000" CACHE STRING "Internal SRAM Area Secure base address")
-set(DDR4_BLK0_BASE_S      "0x70000000" CACHE STRING "DDR4 block 0 Secure base address")
-set(DDR4_BLK1_BASE_S      "0x90000000" CACHE STRING "DDR4 block 1 Secure base address")
-set(DDR4_BLK2_BASE_S      "0xB0000000" CACHE STRING "DDR4 block 2 Secure base address")
-set(DDR4_BLK3_BASE_S      "0xD0000000" CACHE STRING "DDR4 block 3 Secure base address")
-
-###################################################################################################
-#                              Application specific config                                        #
-###################################################################################################
-
-# This parameter is based on the linker/scatter script for simple platform. Do not change this
-# parameter in isolation.
-set(DESIGN_NAME            "Simple platform" CACHE STRING "Design name")
-
-# SRAM size reserved for activation buffers
-math(EXPR ACTIVATION_BUF_SRAM_SZ "${ISRAM0_SIZE} + ${ISRAM1_SIZE}" OUTPUT_FORMAT HEXADECIMAL)
-
-
-###################################################################################################
-#                                         Base addresses                                          #
-###################################################################################################
-set(PL011_UART0_BASE            "0x49303000" CACHE STRING "PL011 UART 0 Base Address")
-
-if (ETHOS_U_NPU_ENABLED)
-    set(ETHOS_U_NPU_BASE          "0x48102000" CACHE STRING "Ethos-U NPU base address")
-    set(ETHOS_U_NPU_TA0_BASE      "0x48103000" CACHE STRING "Ethos-U NPU's timing adapter 0 base address")
-    set(ETHOS_U_NPU_TA1_BASE      "0x48103200" CACHE STRING "Ethos-U NPU's timing adapter 1 base address")
-    set(SEC_ETHOS_U_NPU_BASE      "0x58102000" CACHE STRING "Ethos-U NPU base address")
-    set(SEC_ETHOS_U_NPU_TA0_BASE  "0x58103000" CACHE STRING "Ethos-U NPU's timing adapter 0 base address")
-    set(SEC_ETHOS_U_NPU_TA1_BASE  "0x58103200" CACHE STRING "Ethos-U NPU's timing adapter 1 base address")
-endif ()
-
-###################################################################################################
-#                                           IRQ numbers                                           #
-###################################################################################################
-if (ETHOS_U_NPU_ENABLED)
-    set(EthosU_IRQn             "56"         CACHE STRING "Ethos-U NPU Interrupt")
-endif ()
diff --git a/scripts/cmake/templates/mem_regions.h.template b/scripts/cmake/templates/mem_regions.h.template
deleted file mode 100644
index 72978ce..0000000
--- a/scripts/cmake/templates/mem_regions.h.template
+++ /dev/null
@@ -1,58 +0,0 @@
-/*
- * Copyright (c) 2021 Arm Limited. All rights reserved.
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-// Auto-generated file
-// ** DO NOT EDIT **
-
-#ifndef MEM_REGION_DEFS_H
-#define MEM_REGION_DEFS_H
-
-#cmakedefine ITCM_SIZE             (@ITCM_SIZE@)     /* ITCM size */
-#cmakedefine DTCM_BLK_SIZE         (@DTCM_BLK_SIZE@)     /* DTCM size, 4 banks of this size available */
-#cmakedefine BRAM_SIZE             (@BRAM_SIZE@)     /* BRAM size */
-#cmakedefine ISRAM0_SIZE           (@ISRAM0_SIZE@)     /* ISRAM0 size */
-#cmakedefine ISRAM1_SIZE           (@ISRAM1_SIZE@)     /* ISRAM1 size */
-#cmakedefine QSPI_SRAM_SIZE        (@QSPI_SRAM_SIZE@)     /* QSPI Flash size */
-#cmakedefine DDR4_BLK_SIZE         (@DDR4_BLK_SIZE@)     /* DDR4 block size */
-
-#cmakedefine ITCM_BASE_NS          (@ITCM_BASE_NS@)     /* Instruction TCM Non-Secure base address */
-#cmakedefine BRAM_BASE_NS          (@BRAM_BASE_NS@)     /* CODE SRAM Non-Secure base address */
-#cmakedefine DTCM0_BASE_NS         (@DTCM0_BASE_NS@)     /* Data TCM block 0 Non-Secure base address */
-#cmakedefine DTCM1_BASE_NS         (@DTCM1_BASE_NS@)     /* Data TCM block 1 Non-Secure base address */
-#cmakedefine DTCM2_BASE_NS         (@DTCM2_BASE_NS@)     /* Data TCM block 2 Non-Secure base address */
-#cmakedefine DTCM3_BASE_NS         (@DTCM3_BASE_NS@)     /* Data TCM block 3 Non-Secure base address */
-#cmakedefine ISRAM0_BASE_NS        (@ISRAM0_BASE_NS@)     /* Internal SRAM Area Non-Secure base address */
-#cmakedefine ISRAM1_BASE_NS        (@ISRAM1_BASE_NS@)     /* Internal SRAM Area Non-Secure base address */
-#cmakedefine QSPI_SRAM_BASE_NS     (@QSPI_SRAM_BASE_NS@)     /* QSPI SRAM Non-Secure base address */
-#cmakedefine DDR4_BLK0_BASE_NS     (@DDR4_BLK0_BASE_NS@)     /* DDR4 block 0 Non-Secure base address */
-#cmakedefine DDR4_BLK1_BASE_NS     (@DDR4_BLK1_BASE_NS@)     /* DDR4 block 1 Non-Secure base address */
-#cmakedefine DDR4_BLK2_BASE_NS     (@DDR4_BLK2_BASE_NS@)     /* DDR4 block 2 Non-Secure base address */
-#cmakedefine DDR4_BLK3_BASE_NS     (@DDR4_BLK3_BASE_NS@)     /* DDR4 block 3 Non-Secure base address */
-
-#cmakedefine ITCM_BASE_S           (@ITCM_BASE_S@)     /* Instruction TCM Secure base address */
-#cmakedefine BRAM_BASE_S           (@BRAM_BASE_S@)     /* CODE SRAM Secure base address */
-#cmakedefine DTCM0_BASE_S          (@DTCM0_BASE_S@)     /* Data TCM block 0 Secure base address */
-#cmakedefine DTCM1_BASE_S          (@DTCM1_BASE_S@)     /* Data TCM block 1 Secure base address */
-#cmakedefine DTCM2_BASE_S          (@DTCM2_BASE_S@)     /* Data TCM block 2 Secure base address */
-#cmakedefine DTCM3_BASE_S          (@DTCM3_BASE_S@)     /* Data TCM block 3 Secure base address */
-#cmakedefine ISRAM0_BASE_S         (@ISRAM0_BASE_S@)     /* Internal SRAM Area Secure base address */
-#cmakedefine ISRAM1_BASE_S         (@ISRAM1_BASE_S@)     /* Internal SRAM Area Secure base address */
-#cmakedefine DDR4_BLK0_BASE_S      (@DDR4_BLK0_BASE_S@)     /* DDR4 block 0 Secure base address */
-#cmakedefine DDR4_BLK1_BASE_S      (@DDR4_BLK1_BASE_S@)     /* DDR4 block 1 Secure base address */
-#cmakedefine DDR4_BLK2_BASE_S      (@DDR4_BLK2_BASE_S@)     /* DDR4 block 2 Secure base address */
-#cmakedefine DDR4_BLK3_BASE_S      (@DDR4_BLK3_BASE_S@)     /* DDR4 block 3 Secure base address */
-
-#endif /*  MEM_REGION_DEFS_H  */
diff --git a/scripts/cmake/templates/peripheral_irqs.h.template b/scripts/cmake/templates/peripheral_irqs.h.template
deleted file mode 100644
index 7696e13..0000000
--- a/scripts/cmake/templates/peripheral_irqs.h.template
+++ /dev/null
@@ -1,138 +0,0 @@
-/*
- * Copyright (c) 2021 Arm Limited. All rights reserved.
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-// Auto-generated file
-// ** DO NOT EDIT **
-
-#ifndef PERIPHERAL_IRQS_H
-#define PERIPHERAL_IRQS_H
-
-/******************************************************************************/
-/*                    Peripheral interrupt numbers                            */
-/******************************************************************************/
-
-/* -------------------  Cortex-M Processor Exceptions Numbers  -------------- */
-/*                 -14 to -1 should be defined by the system header           */
-/* ----------------------  Core Specific Interrupt Numbers  ------------------*/
-#cmakedefine NONSEC_WATCHDOG_RESET_IRQn (@NONSEC_WATCHDOG_RESET_IRQn@)  /* Non-Secure Watchdog Reset Interrupt   */
-#cmakedefine NONSEC_WATCHDOG_IRQn       (@NONSEC_WATCHDOG_IRQn@)  /* Non-Secure Watchdog Interrupt         */
-#cmakedefine S32K_TIMER_IRQn            (@S32K_TIMER_IRQn@)  /* S32K Timer Interrupt                  */
-#cmakedefine TIMER0_IRQn                (@TIMER0_IRQn@)  /* TIMER 0 Interrupt                     */
-#cmakedefine TIMER1_IRQn                (@TIMER1_IRQn@)  /* TIMER 1 Interrupt                     */
-#cmakedefine TIMER2_IRQn                (@TIMER2_IRQn@)  /* TIMER 2 Interrupt                    */
-#cmakedefine MPC_IRQn                   (@MPC_IRQn@)  /* MPC Combined (@Secure@) Interrupt       */
-#cmakedefine PPC_IRQn                   (@PPC_IRQn@)  /* PPC Combined (@Secure@) Interrupt       */
-#cmakedefine MSC_IRQn                   (@MSC_IRQn@)  /* MSC Combined (@Secure@) Interrput       */
-#cmakedefine BRIDGE_ERROR_IRQn          (@BRIDGE_ERROR_IRQn@)  /* Bridge Error Combined (@Secure@) Interrupt */
-#cmakedefine MGMT_PPU_IRQn              (@MGMT_PPU_IRQn@)  /* MGMT_PPU */
-#cmakedefine SYS_PPU_IRQn               (@SYS_PPU_IRQn@)  /* SYS_PPU */
-#cmakedefine CPU0_PPU_IRQn              (@CPU0_PPU_IRQn@)  /* CPU0_PPU */
-#cmakedefine DEBUG_PPU_IRQn             (@DEBUG_PPU_IRQn@)  /* DEBUG_PPU */
-#cmakedefine TIMER3_AON_IRQn            (@TIMER3_AON_IRQn@)  /* TIMER3_AON */
-#cmakedefine CPU0CTIIQ0_IRQn            (@CPU0CTIIQ0_IRQn@)  /* CPU0CTIIQ0 */
-#cmakedefine CPU0CTIIQ01_IRQn           (@CPU0CTIIQ01_IRQn@)  /* CPU0CTIIQ01 */
-
-#cmakedefine SYS_TSTAMP_COUNTER_IRQn    (@SYS_TSTAMP_COUNTER_IRQn@)  /* System timestamp counter interrupt */
-
-/* ----------------------  CMSDK Specific Interrupt Numbers  ----------------- */
-#cmakedefine UARTRX0_IRQn               (@UARTRX0_IRQn@)  /* UART 0 RX Interrupt                   */
-#cmakedefine UARTTX0_IRQn               (@UARTTX0_IRQn@)  /* UART 0 TX Interrupt                   */
-#cmakedefine UARTRX1_IRQn               (@UARTRX1_IRQn@)  /* UART 1 RX Interrupt                   */
-#cmakedefine UARTTX1_IRQn               (@UARTTX1_IRQn@)  /* UART 1 TX Interrupt                   */
-#cmakedefine UARTRX2_IRQn               (@UARTRX2_IRQn@)  /* UART 2 RX Interrupt                   */
-#cmakedefine UARTTX2_IRQn               (@UARTTX2_IRQn@)  /* UART 2 TX Interrupt                   */
-#cmakedefine UARTRX3_IRQn               (@UARTRX3_IRQn@)  /* UART 3 RX Interrupt                   */
-#cmakedefine UARTTX3_IRQn               (@UARTTX3_IRQn@)  /* UART 3 TX Interrupt                   */
-#cmakedefine UARTRX4_IRQn               (@UARTRX4_IRQn@)  /* UART 4 RX Interrupt                   */
-#cmakedefine UARTTX4_IRQn               (@UARTTX4_IRQn@)  /* UART 4 TX Interrupt                   */
-#cmakedefine UART0_IRQn                 (@UART0_IRQn@)  /* UART 0 combined Interrupt             */
-#cmakedefine UART1_IRQn                 (@UART1_IRQn@)  /* UART 1 combined Interrupt             */
-#cmakedefine UART2_IRQn                 (@UART2_IRQn@)  /* UART 2 combined Interrupt             */
-#cmakedefine UART3_IRQn                 (@UART3_IRQn@)  /* UART 3 combined Interrupt             */
-#cmakedefine UART4_IRQn                 (@UART4_IRQn@)  /* UART 4 combined Interrupt             */
-#cmakedefine UARTOVF_IRQn               (@UARTOVF_IRQn@)  /* UART 0,1,2,3 and 4 Overflow Interrupt */
-#cmakedefine ETHERNET_IRQn              (@ETHERNET_IRQn@)  /* Ethernet Interrupt                    */
-#cmakedefine I2S_IRQn                   (@I2S_IRQn@)  /* I2S Interrupt                         */
-#cmakedefine TSC_IRQn                   (@TSC_IRQn@)  /* Touch Screen Interrupt                */
-#cmakedefine SPI2_IRQn                  (@SPI2_IRQn@)  /* SPI 2 Interrupt                       */
-#cmakedefine SPI3_IRQn                  (@SPI3_IRQn@)  /* SPI 3 Interrupt                       */
-#cmakedefine SPI4_IRQn                  (@SPI4_IRQn@)  /* SPI 4 Interrupt                       */
-
-#cmakedefine EthosU_IRQn                (@EthosU_IRQn@)   /* Ethos-Uxx Interrupt */
-
-#cmakedefine GPIO0_IRQn                 (@GPIO0_IRQn@)  /* GPIO 0 Combined Interrupt             */
-#cmakedefine GPIO1_IRQn                 (@GPIO1_IRQn@)  /* GPIO 1 Combined Interrupt             */
-#cmakedefine GPIO2_IRQn                 (@GPIO2_IRQn@)  /* GPIO 2 Combined Interrupt             */
-#cmakedefine GPIO3_IRQn                 (@GPIO3_IRQn@)  /* GPIO 3 Combined Interrupt             */
-
-#cmakedefine GPIO0_0_IRQn               (@GPIO0_0_IRQn@)  /* All P0 I/O pins used as irq source    */
-#cmakedefine GPIO0_1_IRQn               (@GPIO0_1_IRQn@)  /* There are 16 pins in total            */
-#cmakedefine GPIO0_2_IRQn               (@GPIO0_2_IRQn@)
-#cmakedefine GPIO0_3_IRQn               (@GPIO0_3_IRQn@)
-#cmakedefine GPIO0_4_IRQn               (@GPIO0_4_IRQn@)
-#cmakedefine GPIO0_5_IRQn               (@GPIO0_5_IRQn@)
-#cmakedefine GPIO0_6_IRQn               (@GPIO0_6_IRQn@)
-#cmakedefine GPIO0_7_IRQn               (@GPIO0_7_IRQn@)
-#cmakedefine GPIO0_8_IRQn               (@GPIO0_8_IRQn@)
-#cmakedefine GPIO0_9_IRQn               (@GPIO0_9_IRQn@)
-#cmakedefine GPIO0_10_IRQn              (@GPIO0_10_IRQn@)
-#cmakedefine GPIO0_11_IRQn              (@GPIO0_11_IRQn@)
-#cmakedefine GPIO0_12_IRQn              (@GPIO0_12_IRQn@)
-#cmakedefine GPIO0_13_IRQn              (@GPIO0_13_IRQn@)
-#cmakedefine GPIO0_14_IRQn              (@GPIO0_14_IRQn@)
-#cmakedefine GPIO0_15_IRQn              (@GPIO0_15_IRQn@)
-#cmakedefine GPIO1_0_IRQn               (@GPIO1_0_IRQn@)  /* All P1 I/O pins used as irq source    */
-#cmakedefine GPIO1_1_IRQn               (@GPIO1_1_IRQn@)  /* There are 16 pins in total            */
-#cmakedefine GPIO1_2_IRQn               (@GPIO1_2_IRQn@)
-#cmakedefine GPIO1_3_IRQn               (@GPIO1_3_IRQn@)
-#cmakedefine GPIO1_4_IRQn               (@GPIO1_4_IRQn@)
-#cmakedefine GPIO1_5_IRQn               (@GPIO1_5_IRQn@)
-#cmakedefine GPIO1_6_IRQn               (@GPIO1_6_IRQn@)
-#cmakedefine GPIO1_7_IRQn               (@GPIO1_7_IRQn@)
-#cmakedefine GPIO1_8_IRQn               (@GPIO1_8_IRQn@)
-#cmakedefine GPIO1_9_IRQn               (@GPIO1_9_IRQn@)
-#cmakedefine GPIO1_10_IRQn              (@GPIO1_10_IRQn@)
-#cmakedefine GPIO1_11_IRQn              (@GPIO1_11_IRQn@)
-#cmakedefine GPIO1_12_IRQn              (@GPIO1_12_IRQn@)
-#cmakedefine GPIO1_13_IRQn              (@GPIO1_13_IRQn@)
-#cmakedefine GPIO1_14_IRQn              (@GPIO1_14_IRQn@)
-#cmakedefine GPIO1_15_IRQn              (@GPIO1_15_IRQn@)
-#cmakedefine GPIO2_0_IRQn               (@GPIO2_0_IRQn@)  /* All P2 I/O pins used as irq source    */
-#cmakedefine GPIO2_1_IRQn               (@GPIO2_1_IRQn@)  /* There are 15 pins in total            */
-#cmakedefine GPIO2_2_IRQn               (@GPIO2_2_IRQn@)
-#cmakedefine GPIO2_3_IRQn               (@GPIO2_3_IRQn@)
-#cmakedefine GPIO2_4_IRQn               (@GPIO2_4_IRQn@)
-#cmakedefine GPIO2_5_IRQn               (@GPIO2_5_IRQn@)
-#cmakedefine GPIO2_6_IRQn               (@GPIO2_6_IRQn@)
-#cmakedefine GPIO2_7_IRQn               (@GPIO2_7_IRQn@)
-#cmakedefine GPIO2_8_IRQn               (@GPIO2_8_IRQn@)
-#cmakedefine GPIO2_9_IRQn               (@GPIO2_9_IRQn@)
-#cmakedefine GPIO2_10_IRQn              (@GPIO2_10_IRQn@)
-#cmakedefine GPIO2_11_IRQn              (@GPIO2_11_IRQn@)
-#cmakedefine GPIO2_12_IRQn              (@GPIO2_12_IRQn@)
-#cmakedefine GPIO2_13_IRQn              (@GPIO2_13_IRQn@)
-#cmakedefine GPIO2_14_IRQn              (@GPIO2_14_IRQn@)
-#cmakedefine GPIO2_15_IRQn              (@GPIO2_15_IRQn@)
-#cmakedefine GPIO3_0_IRQn               (@GPIO3_0_IRQn@)  /* All P3 I/O pins used as irq source    */
-#cmakedefine GPIO3_1_IRQn               (@GPIO3_1_IRQn@)  /* There are 4 pins in total             */
-#cmakedefine GPIO3_2_IRQn               (@GPIO3_2_IRQn@)
-#cmakedefine GPIO3_3_IRQn               (@GPIO3_3_IRQn@)
-#cmakedefine UARTRX5_IRQn               (@UARTRX5_IRQn@)  /* UART 5 RX Interrupt                   */
-#cmakedefine UARTTX5_IRQn               (@UARTTX5_IRQn@)  /* UART 5 TX Interrupt                   */
-#cmakedefine UART5_IRQn                 (@UART5_IRQn@)  /* UART 5 combined Interrupt             */
-#cmakedefine HDCLCD_IRQn                (@HDCLCD_IRQn@)  /* HDCLCD Interrupt                      */
-
-#endif /* PERIPHERAL_IRQS_H */
diff --git a/scripts/cmake/templates/peripheral_memmap.h.template b/scripts/cmake/templates/peripheral_memmap.h.template
deleted file mode 100644
index d7f0b3a..0000000
--- a/scripts/cmake/templates/peripheral_memmap.h.template
+++ /dev/null
@@ -1,162 +0,0 @@
-/*
- * Copyright (c) 2021 Arm Limited. All rights reserved.
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-// Auto-generated file
-// ** DO NOT EDIT **
-
-#ifndef PERIPHERAL_MEMMAP_H
-#define PERIPHERAL_MEMMAP_H
-
-#cmakedefine DESIGN_NAME              "@DESIGN_NAME@"
-
-/******************************************************************************/
-/*                         Peripheral memory map                              */
-/******************************************************************************/
-
-#cmakedefine CMSDK_GPIO0_BASE         (@CMSDK_GPIO0_BASE@)       /* User GPIO 0 Base Address   */
-#cmakedefine CMSDK_GPIO1_BASE         (@CMSDK_GPIO1_BASE@)       /* User GPIO 1 Base Address   */
-#cmakedefine CMSDK_GPIO2_BASE         (@CMSDK_GPIO2_BASE@)       /* User GPIO 2 Base Address   */
-#cmakedefine CMSDK_GPIO3_BASE         (@CMSDK_GPIO3_BASE@)       /* User GPIO 3 Base Address   */
-
-#cmakedefine FMC_CMDSK_GPIO_BASE0        (@FMC_CMDSK_GPIO_BASE0@)       /* FMC_CMDSK_GPIO_BASE 0 Base Address (4KB) */
-#cmakedefine FMC_CMDSK_GPIO_BASE1        (@FMC_CMDSK_GPIO_BASE1@)       /* FMC_CMDSK_GPIO_BASE 1 Base Address (4KB)*/
-#cmakedefine FMC_CMDSK_GPIO_BASE2        (@FMC_CMDSK_GPIO_BASE2@)       /* FMC_CMDSK_GPIO_BASE 2 Base Address (4KB)*/
-#cmakedefine FMC_USER_AHB_BASE           (@FMC_USER_AHB_BASE@)          /* FMC_USER_AHB_BASE     Base Address (4KB)*/
-
-#cmakedefine DMA0_BASE                (@DMA0_BASE@)       /* DMA0 (4KB) */
-#cmakedefine DMA1_BASE                (@DMA1_BASE@)       /* DMA1 (4KB) */
-#cmakedefine DMA2_BASE                (@DMA2_BASE@)       /* DMA2 (4KB) */
-#cmakedefine DMA3_BASE                (@DMA3_BASE@)       /* DMA3 (4KB) */
-
-#cmakedefine USER_APB0_BASE           (@USER_APB0_BASE@)       /* User APB0 */
-#cmakedefine USER_APB1_BASE           (@USER_APB1_BASE@)       /* User APB1 */
-#cmakedefine USER_APB2_BASE           (@USER_APB2_BASE@)       /* User APB2 */
-#cmakedefine USER_APB3_BASE           (@USER_APB3_BASE@)       /* User APB3 */
-
-#cmakedefine MPS3_I2C0_BASE           (@MPS3_I2C0_BASE@)       /* Touch Screen I2C Base Address */
-#cmakedefine MPS3_I2C1_BASE           (@MPS3_I2C1_BASE@)       /* Audio Interface I2C Base Address */
-#cmakedefine MPS3_SSP2_BASE           (@MPS3_SSP2_BASE@)       /* ADC SPI PL022 Base Address   */
-#cmakedefine MPS3_SSP3_BASE           (@MPS3_SSP3_BASE@)       /* Shield 0 SPI PL022 Base Address   */
-
-#cmakedefine MPS3_SSP4_BASE           (@MPS3_SSP4_BASE@)       /* Shield 1 SPI PL022 Base Address   */
-#cmakedefine MPS3_I2C2_BASE           (@MPS3_I2C2_BASE@)       /* Shield 0 SBCon Base Address */
-#cmakedefine MPS3_I2C3_BASE           (@MPS3_I2C3_BASE@)       /* Shield 1 SBCon Base Address */
-
-#cmakedefine USER_APB_BASE            (@USER_APB_BASE@)       /* User APB Base Address */
-#cmakedefine MPS3_I2C4_BASE           (@MPS3_I2C4_BASE@)       /* HDMI I2C SBCon Base Address */
-#cmakedefine MPS3_I2C5_BASE           (@MPS3_I2C5_BASE@)       /* DDR EPROM I2C SBCon Base Address */
-#cmakedefine MPS3_SCC_BASE            (@MPS3_SCC_BASE@)       /* SCC Base Address    */
-#cmakedefine MPS3_AAIC_I2S_BASE       (@MPS3_AAIC_I2S_BASE@)       /* Audio Interface I2S Base Address */
-#cmakedefine MPS3_FPGAIO_BASE         (@MPS3_FPGAIO_BASE@)       /* FPGA IO Base Address */
-#cmakedefine PL011_UART0_BASE         (@PL011_UART0_BASE@)       /* PL011 UART0 Base Address */
-#cmakedefine CMSDK_UART0_BASE         (@CMSDK_UART0_BASE@)       /* UART 0 Base Address */
-#cmakedefine CMSDK_UART1_BASE         (@CMSDK_UART1_BASE@)       /* UART 1 Base Address */
-#cmakedefine CMSDK_UART2_BASE         (@CMSDK_UART2_BASE@)       /* UART 2 Base Address */
-#cmakedefine CMSDK_UART3_BASE         (@CMSDK_UART3_BASE@)       /* UART 3 Base Address Shield 0*/
-
-#cmakedefine ETHOS_U_NPU_BASE           (@ETHOS_U_NPU_BASE@)    /* Ethos-U NPU base address*/
-#cmakedefine ETHOS_U_NPU_TA0_BASE       (@ETHOS_U_NPU_TA0_BASE@)    /* Ethos-U NPU's timing adapter 0 base address */
-#cmakedefine ETHOS_U_NPU_TA1_BASE       (@ETHOS_U_NPU_TA1_BASE@)    /* Ethos-U NPU's timing adapter 1 base address */
-
-#cmakedefine CMSDK_UART4_BASE         (@CMSDK_UART4_BASE@)       /* UART 4 Base Address Shield 1*/
-#cmakedefine CMSDK_UART5_BASE         (@CMSDK_UART5_BASE@)       /* UART 5 Base Address */
-#cmakedefine HDMI_AUDIO_BASE          (@HDMI_AUDIO_BASE@)       /* HDMI AUDIO Base Address */
-#cmakedefine CLCD_CONFIG_BASE         (@CLCD_CONFIG_BASE@)       /* CLCD CONFIG Base Address */
-#cmakedefine RTC_BASE                 (@RTC_BASE@)       /* RTC Base address */
-#cmakedefine SMSC9220_BASE            (@SMSC9220_BASE@)       /* Ethernet SMSC9220 Base Address */
-#cmakedefine USB_BASE                 (@USB_BASE@)       /* USB Base Address */
-#cmakedefine CMSDK_SDIO_BASE          (@CMSDK_SDIO_BASE@)       /* User SDIO Base Address   */
-#cmakedefine MPS3_CLCD_BASE           (@MPS3_CLCD_BASE@)       /* HDLCD Base Address   */
-#cmakedefine MPS3_eMMC_BASE           (@MPS3_eMMC_BASE@)       /* User eMMC Base Address   */
-#cmakedefine USER_BASE                (@USER_BASE@)       /* User ? Base Address */
-
-#cmakedefine QSPI_XIP_BASE            (@QSPI_XIP_BASE@)       /* QSPI XIP config Base Address */
-#cmakedefine QSPI_WRITE_BASE          (@QSPI_WRITE_BASE@)       /* QSPI write config Base Address */
-
-/******************************************************************************/
-/*                      Secure Peripheral memory map                          */
-/******************************************************************************/
-
-#cmakedefine MPC_ISRAM0_BASE_S        (@MPC_ISRAM0_BASE_S@)       /* ISRAM0 Memory Protection Controller Secure base address */
-#cmakedefine MPC_ISRAM1_BASE_S        (@MPC_ISRAM1_BASE_S@)       /* ISRAM1 Memory Protection Controller Secure base address */
-
-#cmakedefine SEC_CMSDK_GPIO0_BASE     (@SEC_CMSDK_GPIO0_BASE@)       /* User GPIO 0 Base Address   */
-#cmakedefine SEC_CMSDK_GPIO1_BASE     (@SEC_CMSDK_GPIO1_BASE@)       /* User GPIO 0 Base Address   */
-#cmakedefine SEC_CMSDK_GPIO2_BASE     (@SEC_CMSDK_GPIO2_BASE@)       /* User GPIO 0 Base Address   */
-#cmakedefine SEC_CMSDK_GPIO3_BASE     (@SEC_CMSDK_GPIO3_BASE@)       /* User GPIO 0 Base Address   */
-
-#cmakedefine SEC_AHB_USER0_BASE       (@SEC_AHB_USER0_BASE@)       /* AHB USER 0 Base Address (4KB) */
-#cmakedefine SEC_AHB_USER1_BASE       (@SEC_AHB_USER1_BASE@)       /* AHB USER 1 Base Address (4KB)*/
-#cmakedefine SEC_AHB_USER2_BASE       (@SEC_AHB_USER2_BASE@)       /* AHB USER 2 Base Address (4KB)*/
-#cmakedefine SEC_AHB_USER3_BASE       (@SEC_AHB_USER3_BASE@)       /* AHB USER 3 Base Address (4KB)*/
-
-#cmakedefine SEC_DMA0_BASE            (@SEC_DMA0_BASE@)       /* DMA0 (4KB) */
-#cmakedefine SEC_DMA1_BASE            (@SEC_DMA1_BASE@)       /* DMA1 (4KB) */
-#cmakedefine SEC_DMA2_BASE            (@SEC_DMA2_BASE@)       /* DMA2 (4KB) */
-#cmakedefine SEC_DMA3_BASE            (@SEC_DMA3_BASE@)       /* DMA3 (4KB) */
-
-#cmakedefine SEC_USER_APB0_BASE       (@SEC_USER_APB0_BASE@)       /* User APB0 */
-#cmakedefine SEC_USER_APB1_BASE       (@SEC_USER_APB1_BASE@)       /* User APB1 */
-#cmakedefine SEC_USER_APB2_BASE       (@SEC_USER_APB2_BASE@)       /* User APB2 */
-#cmakedefine SEC_USER_APB3_BASE       (@SEC_USER_APB3_BASE@)       /* User APB3 */
-
-#cmakedefine SEC_MPS3_I2C0_BASE       (@SEC_MPS3_I2C0_BASE@)       /* Touch Screen I2C Base Address */
-#cmakedefine SEC_MPS3_I2C1_BASE       (@SEC_MPS3_I2C1_BASE@)       /* Audio Interface I2C Base Address */
-#cmakedefine SEC_MPS3_SSP2_BASE       (@SEC_MPS3_SSP2_BASE@)       /* ADC SPI PL022 Base Address   */
-#cmakedefine SEC_MPS3_SSP3_BASE       (@SEC_MPS3_SSP3_BASE@)       /* Shield 0 SPI PL022 Base Address   */
-
-#cmakedefine SEC_MPS3_SSP4_BASE       (@SEC_MPS3_SSP4_BASE@)       /* Shield 1 SPI PL022 Base Address   */
-#cmakedefine SEC_MPS3_I2C2_BASE       (@SEC_MPS3_I2C2_BASE@)       /* Shield 0 SBCon Base Address */
-#cmakedefine SEC_MPS3_I2C3_BASE       (@SEC_MPS3_I2C3_BASE@)       /* Shield 1 SBCon Base Address */
-
-#cmakedefine SEC_MPS3_I2C4_BASE       (@SEC_MPS3_I2C4_BASE@)       /* HDMI I2C SBCon Base Address */
-#cmakedefine SEC_MPS3_I2C5_BASE       (@SEC_MPS3_I2C5_BASE@)       /* DDR EPROM I2C SBCon Base Address */
-#cmakedefine SEC_MPS3_SCC_BASE        (@SEC_MPS3_SCC_BASE@)       /* SCC Base Address    */
-#cmakedefine SEC_MPS3_AAIC_I2S_BASE   (@SEC_MPS3_AAIC_I2S_BASE@)       /* Audio Interface I2S Base Address */
-#cmakedefine SEC_MPS3_FPGAIO_BASE     (@SEC_MPS3_FPGAIO_BASE@)       /* FPGA IO Base Address */
-#cmakedefine SEC_CMSDK_UART0_BASE     (@SEC_CMSDK_UART0_BASE@)       /* UART 0 Base Address */
-#cmakedefine SEC_CMSDK_UART1_BASE     (@SEC_CMSDK_UART1_BASE@)       /* UART 1 Base Address */
-#cmakedefine SEC_CMSDK_UART2_BASE     (@SEC_CMSDK_UART2_BASE@)       /* UART 2 Base Address */
-#cmakedefine SEC_CMSDK_UART3_BASE     (@SEC_CMSDK_UART3_BASE@)       /* UART 3 Base Address Shield 0*/
-
-#cmakedefine SEC_CMSDK_UART4_BASE     (@SEC_CMSDK_UART4_BASE@)       /* UART 4 Base Address Shield 1*/
-#cmakedefine SEC_CMSDK_UART5_BASE     (@SEC_CMSDK_UART5_BASE@)       /* UART 5 Base Address */
-#cmakedefine SEC_HDMI_AUDIO_BASE      (@SEC_HDMI_AUDIO_BASE@)       /* HDMI AUDIO Base Address */
-#cmakedefine SEC_CLCD_CONFIG_BASE     (@SEC_CLCD_CONFIG_BASE@)       /* CLCD CONFIG Base Address */
-#cmakedefine SEC_RTC_BASE             (@SEC_RTC_BASE@)       /* RTC Base address */
-#cmakedefine SEC_SMSC9220_BASE        (@SEC_SMSC9220_BASE@)       /* Ethernet SMSC9220 Base Address */
-#cmakedefine SEC_USB_BASE             (@SEC_USB_BASE@)       /* USB Base Address */
-
-#cmakedefine SEC_ETHOS_U_NPU_BASE       (@SEC_ETHOS_U_NPU_BASE@)   /* Ethos-U NPU base address*/
-#cmakedefine SEC_ETHOS_U_NPU_TA0_BASE   (@SEC_ETHOS_U_NPU_TA0_BASE@)   /* Ethos-U NPU's timing adapter 0 base address */
-#cmakedefine SEC_ETHOS_U_NPU_TA1_BASE   (@SEC_ETHOS_U_NPU_TA1_BASE@)   /* Ethos-U NPU's timing adapter 1 base address */
-
-#cmakedefine SEC_USER_BASE            (@SEC_USER_BASE@)       /* User ? Base Address */
-
-#cmakedefine SEC_QSPI_XIP_BASE        (@SEC_QSPI_XIP_BASE@)       /* QSPI XIP config Base Address */
-#cmakedefine SEC_QSPI_WRITE_BASE      (@SEC_QSPI_WRITE_BASE@)       /* QSPI write config Base Address */
-
-/******************************************************************************/
-/*                                  MPCs                                      */
-/******************************************************************************/
-
-#cmakedefine MPC_ISRAM0_BASE_S        (@MPC_ISRAM0_BASE_S@)       /* Internal SRAM 0 MPC */
-#cmakedefine MPC_ISRAM1_BASE_S        (@MPC_ISRAM1_BASE_S@)       /* Internal SRAM 1 MPC */
-#cmakedefine MPC_BRAM_BASE_S          (@MPC_BRAM_BASE_S@)       /* SRAM Memory Protection Controller Secure base address */
-#cmakedefine MPC_QSPI_BASE_S          (@MPC_QSPI_BASE_S@)       /* QSPI Memory Protection Controller Secure base address */
-#cmakedefine MPC_DDR4_BASE_S          (@MPC_DDR4_BASE_S@)       /* DDR4 Memory Protection Controller Secure base address */
-
-#endif /* PERIPHERAL_MEMMAP_H */
diff --git a/scripts/cmake/templates/timing_adapter_settings.template b/scripts/cmake/templates/timing_adapter_settings.template
deleted file mode 100644
index d5e202a..0000000
--- a/scripts/cmake/templates/timing_adapter_settings.template
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
- * Copyright (c) 2021 Arm Limited. All rights reserved.
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-// Auto-generated file
-// ** DO NOT EDIT **
-
-#ifndef TIMING_ADAPTER_SETTINGS_H
-#define TIMING_ADAPTER_SETTINGS_H
-
-#cmakedefine TA0_BASE       (@TA0_BASE@)
-#cmakedefine TA1_BASE       (@TA1_BASE@)
-
-/* Timing adapter settings for AXI0 */
-#if defined(TA0_BASE)
-
-#define TA0_MAXR           (@TA0_MAXR@)
-#define TA0_MAXW           (@TA0_MAXW@)
-#define TA0_MAXRW          (@TA0_MAXRW@)
-#define TA0_RLATENCY       (@TA0_RLATENCY@)
-#define TA0_WLATENCY       (@TA0_WLATENCY@)
-#define TA0_PULSE_ON       (@TA0_PULSE_ON@)
-#define TA0_PULSE_OFF      (@TA0_PULSE_OFF@)
-#define TA0_BWCAP          (@TA0_BWCAP@)
-#define TA0_PERFCTRL       (@TA0_PERFCTRL@)
-#define TA0_PERFCNT        (@TA0_PERFCNT@)
-#define TA0_MODE           (@TA0_MODE@)
-#define TA0_HISTBIN        (@TA0_HISTBIN@)
-#define TA0_HISTCNT        (@TA0_HISTCNT@)
-
-#endif /* defined(TA0_BASE) */
-
-/* Timing adapter settings for AXI1 */
-#if defined(TA1_BASE)
-
-#define TA1_MAXR           (@TA1_MAXR@)
-#define TA1_MAXW           (@TA1_MAXW@)
-#define TA1_MAXRW          (@TA1_MAXRW@)
-#define TA1_RLATENCY       (@TA1_RLATENCY@)
-#define TA1_WLATENCY       (@TA1_WLATENCY@)
-#define TA1_PULSE_ON       (@TA1_PULSE_ON@)
-#define TA1_PULSE_OFF      (@TA1_PULSE_OFF@)
-#define TA1_BWCAP          (@TA1_BWCAP@)
-#define TA1_PERFCTRL       (@TA1_PERFCTRL@)
-#define TA1_PERFCNT        (@TA1_PERFCNT@)
-#define TA1_MODE           (@TA1_MODE@)
-#define TA1_HISTBIN        (@TA1_HISTBIN@)
-#define TA1_HISTCNT        (@TA1_HISTCNT@)
-
-#endif /* defined(TA1_BASE) */
-
-#endif /* TIMING_ADAPTER_SETTINGS_H */
\ No newline at end of file
diff --git a/scripts/cmake/tensorflow.cmake b/scripts/cmake/tensorflow.cmake
index 43fbb5c..9a4066d 100644
--- a/scripts/cmake/tensorflow.cmake
+++ b/scripts/cmake/tensorflow.cmake
@@ -43,7 +43,7 @@
 
 set(TENSORFLOW_LITE_MICRO_PATH "${TENSORFLOW_SRC_PATH}/tensorflow/lite/micro")
 set(TENSORFLOW_LITE_MICRO_GENDIR ${CMAKE_CURRENT_BINARY_DIR}/tensorflow/)
-
+set(TENSORFLOW_LITE_MICRO_PLATFORM_LIB_NAME "libtensorflow-microlite.a")
 
 set(ETHOS_EVAL_TARGET_MAKEFILE_INC ${CMAKE_CURRENT_SOURCE_DIR}/scripts/make/cortex_m_ethos_eval_makefile.inc)
 
@@ -65,6 +65,22 @@
         DESTINATION ${TENSORFLOW_LITE_MICRO_PATH}/tools/make/targets/)
 endif()
 
+#TODO: this thing fails the TF build, when the driver is compiled, fatal error: 'ethosETHOSU_ARCH_interface.h' file not found
+#if (CMAKE_SYSTEM_PROCESSOR STREQUAL cortex-m55)
+#    set(TENSORFLOW_LITE_MICRO_TARGET "cortex_m_generic")
+#    set(TENSORFLOW_LITE_MICRO_TARGET_ARCH ${CMAKE_SYSTEM_PROCESSOR}${CPU_FEATURES})
+#    if(ETHOS_U_NPU_ENABLED)
+#        # Arm Ethos-U55 NPU is the co-processor for ML workload:
+#        set(TENSORFLOW_LITE_MICRO_CO_PROCESSOR  "ethos_u")
+#    endif()
+#
+#    set(TENSORFLOW_LITE_MICRO_OPTIMIZED_KERNEL  "cmsis_nn")
+#
+#else()
+#    set(TENSORFLOW_LITE_MICRO_TARGET "linux")
+#    set(TENSORFLOW_LITE_MICRO_TARGET_ARCH x86_64)
+#endif()
+
 if (TENSORFLOW_LITE_MICRO_CLEAN_DOWNLOADS)
     list(APPEND MAKE_TARGETS_LIST "clean_downloads")
 endif()
@@ -93,10 +109,9 @@
         TARGET_ARCH=${TENSORFLOW_LITE_MICRO_TARGET_ARCH}
         BUILD_TYPE=${TENSORFLOW_LITE_MICRO_BUILD_TYPE}
         ETHOSU_ARCH=${ETHOSU_ARCH}
-
+        ETHOSU_DRIVER_PATH=${ETHOS_U_NPU_DRIVER_SRC_PATH}
+        CMSIS_PATH=${CMSIS_SRC_PATH}
         # Conditional arguments
-        $<$<NOT:$<STREQUAL:${TARGET_PLATFORM},"native">>:ETHOSU_DRIVER_PATH=${ETHOS_U_NPU_DRIVER_SRC_PATH}>
-        $<$<NOT:$<STREQUAL:${TARGET_PLATFORM},"native">>:CMSIS_PATH=${CMSIS_SRC_PATH}>
         $<$<BOOL:${ARMCLANG_DEBUG_DWARF_LEVEL}>:ARMCLANG_DEBUG_DWARF_LEVEL=${ARMCLANG_DEBUG_DWARF_LEVEL}>
         $<$<BOOL:${TENSORFLOW_LITE_MICRO_CORE_OPTIMIZATION_LEVEL}>:CORE_OPTIMIZATION_LEVEL=${TENSORFLOW_LITE_MICRO_CORE_OPTIMIZATION_LEVEL}>
         $<$<BOOL:${TENSORFLOW_LITE_MICRO_KERNEL_OPTIMIZATION_LEVEL}>:KERNEL_OPTIMIZATION_LEVEL=${TENSORFLOW_LITE_MICRO_KERNEL_OPTIMIZATION_LEVEL}>
@@ -116,7 +131,18 @@
     WORKING_DIRECTORY ${TENSORFLOW_SRC_PATH})
 
 # Create library
+
 add_library(tensorflow-lite-micro STATIC IMPORTED)
+
 add_dependencies(tensorflow-lite-micro tensorflow_build)
+
 set_property(TARGET tensorflow-lite-micro PROPERTY IMPORTED_LOCATION
              "${CMAKE_LIBRARY_OUTPUT_DIRECTORY}/${TENSORFLOW_LITE_MICRO_PLATFORM_LIB_NAME}")
+
+target_include_directories(tensorflow-lite-micro
+    INTERFACE
+    ${TENSORFLOW_SRC_PATH})
+
+target_compile_definitions(tensorflow-lite-micro
+    INTERFACE
+    TF_LITE_STATIC_MEMORY)
diff --git a/scripts/cmake/toolchains/bare-metal-armclang.cmake b/scripts/cmake/toolchains/bare-metal-armclang.cmake
index afe6e66..065395b 100644
--- a/scripts/cmake/toolchains/bare-metal-armclang.cmake
+++ b/scripts/cmake/toolchains/bare-metal-armclang.cmake
@@ -30,7 +30,6 @@
 # Skip compiler test execution
 set(CMAKE_C_COMPILER_WORKS          1)
 set(CMAKE_CXX_COMPILER_WORKS        1)
-set(PLATFORM_HAL                    1)
 
 if (NOT DEFINED CMAKE_SYSTEM_PROCESSOR)
     set(CMAKE_SYSTEM_PROCESSOR      cortex-m55)
@@ -76,7 +75,6 @@
 
 # Compile definitions:
 add_compile_definitions(
-    PLATFORM_HAL=${PLATFORM_HAL}
     CPU_HEADER_FILE=\"${CPU_HEADER_FILE}\"
     $<$<BOOL:${CPU_COMPILE_DEF}>:${CPU_COMPILE_DEF}>
     $<$<BOOL:${ARM_MATH_DSP}>:ARM_MATH_DSP>
@@ -105,14 +103,14 @@
 endfunction()
 
 # Function to add linker option to use the chosen linker script (scatter file).
-function(add_linker_script SCRIPT_DIR SCRIPT_NAME)
-    set(LINKER_SCRIPT_PATH ${SCRIPT_DIR}/${SCRIPT_NAME}.sct
-        CACHE STRING "Linker script path")
+function(add_linker_script TARGET_NAME SCRIPT_DIR SCRIPT_NAME)
+    set(LINKER_SCRIPT_PATH ${SCRIPT_DIR}/${SCRIPT_NAME}.sct)
     if (NOT EXISTS ${LINKER_SCRIPT_PATH})
         message(FATAL_ERROR "Scatter file not found: ${LINKER_SCRIPT_PATH}")
     endif()
     message(STATUS "Using linker script: ${LINKER_SCRIPT_PATH}")
-    add_link_options(--scatter=${LINKER_SCRIPT_PATH})
+    target_link_options(${TARGET_NAME} PUBLIC
+        --scatter=${LINKER_SCRIPT_PATH})
 endfunction()
 
 # Function to set the command to copy/extract contents from an elf
diff --git a/scripts/cmake/toolchains/bare-metal-gcc.cmake b/scripts/cmake/toolchains/bare-metal-gcc.cmake
index 1ddfb44..89201fb 100644
--- a/scripts/cmake/toolchains/bare-metal-gcc.cmake
+++ b/scripts/cmake/toolchains/bare-metal-gcc.cmake
@@ -28,7 +28,6 @@
 # Skip compiler test execution
 set(CMAKE_C_COMPILER_WORKS          1)
 set(CMAKE_CXX_COMPILER_WORKS        1)
-set(PLATFORM_HAL                    1)
 
 if (NOT DEFINED CMAKE_SYSTEM_PROCESSOR)
     set(CMAKE_SYSTEM_PROCESSOR      cortex-m55)
@@ -75,7 +74,6 @@
 
 # Compile definitions:
 add_compile_definitions(
-    PLATFORM_HAL=${PLATFORM_HAL}
     CPU_HEADER_FILE=\"${CPU_HEADER_FILE}\"
     $<$<BOOL:${CPU_COMPILE_DEF}>:${CPU_COMPILE_DEF}>
     $<$<BOOL:${ARM_MATH_DSP}>:ARM_MATH_DSP>
@@ -99,14 +97,15 @@
 endfunction()
 
 # Function to add linker option to use the chosen linker script.
-function(add_linker_script SCRIPT_DIR SCRIPT_NAME)
+function(add_linker_script TARGET_NAME SCRIPT_DIR SCRIPT_NAME)
     set(LINKER_SCRIPT_PATH ${SCRIPT_DIR}/${SCRIPT_NAME}.ld
         CACHE STRING "Linker script path")
     if (NOT EXISTS ${LINKER_SCRIPT_PATH})
         message(FATAL_ERROR "Linker script not found: ${LINKER_SCRIPT_PATH}")
     endif()
     message(STATUS "Using linker script: ${LINKER_SCRIPT_PATH}")
-    add_link_options("SHELL:-T ${LINKER_SCRIPT_PATH}")
+    target_link_options(${TARGET_NAME} PUBLIC
+        "SHELL:-T ${LINKER_SCRIPT_PATH}")
 endfunction()
 
 # Function to set the command to copy/extract contents from an elf
diff --git a/scripts/cmake/toolchains/native-gcc.cmake b/scripts/cmake/toolchains/native-gcc.cmake
index 4b5a62b..150a59b 100644
--- a/scripts/cmake/toolchains/native-gcc.cmake
+++ b/scripts/cmake/toolchains/native-gcc.cmake
@@ -19,9 +19,6 @@
 set(CMAKE_C_LINKER_PREFERENCE   gcc)
 set(CMAKE_CXX_LINKER_PREFERENCE gcc)
 
-# Platform specific directory:
-set(PLATFORM_HAL                3)
-
 # Warning compiler definitions:
 add_compile_options(
     -Wsign-compare
@@ -38,7 +35,6 @@
 add_compile_options(
     -fPIC
     -pthread
-    -DPLATFORM_HAL=${PLATFORM_HAL}
     "$<$<COMPILE_LANGUAGE:CXX>:-fno-threadsafe-statics>")
 
 # Linker options