Opensource ML embedded evaluation kit
Change-Id: I12e807f19f5cacad7cef82572b6dd48252fd61fd
diff --git a/scripts/cmake/bare-metal-sources.cmake b/scripts/cmake/bare-metal-sources.cmake
new file mode 100644
index 0000000..3e24d7b
--- /dev/null
+++ b/scripts/cmake/bare-metal-sources.cmake
@@ -0,0 +1,170 @@
+#----------------------------------------------------------------------------
+# Copyright (c) 2021 Arm Limited. All rights reserved.
+# SPDX-License-Identifier: Apache-2.0
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#----------------------------------------------------------------------------
+set(CMAKE_INSTALL_PREFIX ${CMAKE_SOURCE_DIR}/build_baremetal)
+set(PLAT_HAL ${CMAKE_CURRENT_SOURCE_DIR}/source/application/hal/platforms/bare-metal)
+
+# If target platform not defined raise an error
+# TARGET_PLATFORM either should have been defined by the user or set to default value mps3
+if (NOT DEFINED TARGET_PLATFORM)
+ message(FATAL_ERROR "Invalid target platform, specify TARGET_PLATFORM=mps3")
+endif ()
+message(STATUS "target platform ${TARGET_PLATFORM}")
+
+set(SOURCE_GEN_DIR ${CMAKE_BINARY_DIR}/generated/bsp)
+if (NOT DEFINED MEM_PROFILES_SRC_DIR)
+ set(MEM_PROFILES_SRC_DIR ${CMAKE_CURRENT_SOURCE_DIR}/scripts/cmake/subsystem-profiles)
+endif()
+set(MEM_PROFILE_TEMPLATE ${CMAKE_CURRENT_SOURCE_DIR}/scripts/cmake/templates/peripheral_memmap.h.template)
+set(IRQ_PROFILE_TEMPLATE ${CMAKE_CURRENT_SOURCE_DIR}/scripts/cmake/templates/peripheral_irqs.h.template)
+set(MEM_REGIONS_TEMPLATE ${CMAKE_CURRENT_SOURCE_DIR}/scripts/cmake/templates/mem_regions.h.template)
+set(TA_SETTINGS_TEMPLATE ${CMAKE_CURRENT_SOURCE_DIR}/scripts/cmake/templates/timing_adapter_settings.template)
+set(TENSORFLOW_LITE_MICRO_PLATFORM_LIB_NAME "libtensorflow-microlite.a")
+set(TENSORFLOW_LITE_MICRO_FLAG "-DTF_LITE_STATIC_MEMORY")
+set(ETHOS_U55_FLAG "-DARM_NPU=1")
+
+if (ETHOS_U55_ENABLED)
+ set(OPTIONAL_FLAGS "${OPTIONAL_FLAGS} ${ETHOS_U55_FLAG}")
+endif ()
+
+# Set specific flags depending on target platform and subsystem
+if (TARGET_PLATFORM STREQUAL mps3)
+ set(MPS3_PLATFORM_FLAG "-DMPS3_PLATFORM=1")
+
+ # If target platform is mps3 and subsystem not defined raise an error,
+ # TARGET_SUBSYSTEM either should have been defined by the user or set to a default value
+ if (NOT DEFINED TARGET_SUBSYSTEM)
+ message(FATAL_ERROR "Target subsystem for mps3 undefined, "
+ "specify -DTARGET_SUBSYSTEM=<sse-200 or sse-300>")
+ endif ()
+
+ if (TARGET_SUBSYSTEM STREQUAL sse-200 OR TARGET_SUBSYSTEM STREQUAL sse-300)
+ message(STATUS "target subsystem is ${TARGET_SUBSYSTEM}")
+ set(BSP_PACKAGE_DIR "${PLAT_HAL}/bsp/bsp-packs/mps3")
+ set(SCAT_FILE "${PLAT_HAL}/bsp/mem_layout/mps3-${TARGET_SUBSYSTEM}.sct")
+
+ # Include the mem profile definitions specific to our target subsystem
+ include(${MEM_PROFILES_SRC_DIR}/corstone-${TARGET_SUBSYSTEM}.cmake)
+ set(OPTIONAL_FLAGS "${OPTIONAL_FLAGS} ${MPS3_PLATFORM_FLAG}")
+ else ()
+ message(FATAL_ERROR "Non compatible target subsystem: ${TARGET_SUBSYSTEM}")
+ endif ()
+elseif (TARGET_PLATFORM STREQUAL simple_platform)
+ set(BSP_PACKAGE_DIR "${PLAT_HAL}/bsp/bsp-packs/${TARGET_PLATFORM}")
+ set(SCAT_FILE "${PLAT_HAL}/bsp/mem_layout/${TARGET_PLATFORM}.sct")
+ include(${MEM_PROFILES_SRC_DIR}/${TARGET_PLATFORM}.cmake)
+ set(OPTIONAL_FLAGS "${OPTIONAL_FLAGS}")
+else ()
+ message(FATAL_ERROR "Non compatible target platform ${TARGET_PLATFORM}")
+endif ()
+
+if (ETHOS_U55_ENABLED)
+ USER_OPTION(TA_CONFIG_FILE "Path to the timing adapter configuration file"
+ "${CMAKE_SCRIPTS_DIR}/ta_config.cmake"
+ FILEPATH)
+
+ # must be included after target subsystem CMake file
+ include(${TA_CONFIG_FILE})
+endif()
+
+# Generate the memory map header file from the mem profile cmake included in one of
+# the previous sections
+message(STATUS "Configuring file from ${MEM_PROFILE_TEMPLATE}"
+ ", ${IRQ_PROFILE_TEMPLATE}"
+ " and ${MEM_REGIONS_TEMPLATE}")
+
+configure_file("${MEM_PROFILE_TEMPLATE}" "${SOURCE_GEN_DIR}/peripheral_memmap.h")
+configure_file("${IRQ_PROFILE_TEMPLATE}" "${SOURCE_GEN_DIR}/peripheral_irqs.h")
+configure_file("${MEM_REGIONS_TEMPLATE}" "${SOURCE_GEN_DIR}/mem_regions.h")
+configure_file("${TA_SETTINGS_TEMPLATE}" "${SOURCE_GEN_DIR}/timing_adapter_settings.h")
+
+message(STATUS "Scatter file: ${SCAT_FILE}")
+message(STATUS "Using BSP package from: ${BSP_PACKAGE_DIR}")
+
+if (DEFINED VERIFY_TEST_OUTPUT)
+ message(STATUS "Test output verification flag is: ${VERIFY_TEST_OUTPUT}")
+ set(OPTIONAL_FLAGS "${OPTIONAL_FLAGS} -DVERIFY_TEST_OUTPUT=${VERIFY_TEST_OUTPUT}")
+endif ()
+
+if (DEFINED LOG_LEVEL)
+ message(STATUS "Setting log level to ${LOG_LEVEL}")
+ set(OPTIONAL_FLAGS "${OPTIONAL_FLAGS} -DLOG_LEVEL=${LOG_LEVEL}")
+endif()
+
+if (DEFINED ACTIVATION_BUF_SRAM_SZ)
+ message(STATUS "Maximum SRAM space for activations buffers for this system: ${ACTIVATION_BUF_SRAM_SZ}")
+ set(OPTIONAL_FLAGS "${OPTIONAL_FLAGS} -DACTIVATION_BUF_SRAM_SZ=${ACTIVATION_BUF_SRAM_SZ}")
+endif()
+
+if (DEFINED ARMCLANG_DEBUG_DWARF_LEVEL)
+ message(STATUS "setting dwarf conformance level to gdwarf-${ARMCLANG_DEBUG_DWARF_LEVEL}")
+ set(OPTIONAL_FLAGS "${OPTIONAL_FLAGS} -gdwarf-${ARMCLANG_DEBUG_DWARF_LEVEL}")
+endif()
+
+set(COMPILER_FLAGS "${ALL_COMMON_FLAGS} ${TENSORFLOW_LITE_MICRO_FLAG} ${PROFILING_OPT} ${OPTIONAL_FLAGS}")
+# For some reason, cmake doesn't pass the c++ standard flag, adding it manually
+set(CMAKE_CXX_FLAGS "${COMPILER_FLAGS} -std=c++11" CACHE INTERNAL "")
+set(CMAKE_C_FLAGS "${COMPILER_FLAGS}" CACHE INTERNAL "")
+set(CMAKE_ASM_FLAGS "${CPU_LD}")
+set(CMAKE_ASM_COMPILE_OBJECT ${CMAKE_CXX_FLAGS})
+
+add_link_options(--strict --callgraph --load_addr_map_info --map)
+add_link_options(--symbols --xref --scatter=${SCAT_FILE})
+
+# Warnings to be ignored:
+# L6314W = No section matches pattern
+# L6439W = Multiply defined Global Symbol
+add_link_options(--diag_suppress=L6439W,L6314W)
+add_link_options(--info sizes,totals,unused,veneers --entry Reset_Handler)
+
+if (CMAKE_BUILD_TYPE STREQUAL Release)
+ add_link_options(--no_debug)
+endif ()
+
+set(CMAKE_EXE_LINKER_FLAGS "${CPU_LD}")
+
+set(PLAT_BSP_INCLUDES
+ ${PLAT_HAL}/bsp/cmsis-device/include
+ ${PLAT_HAL}/bsp/include/
+ ${PLAT_HAL}/bsp/bsp-core/include
+ ${BSP_PACKAGE_DIR}/include
+)
+
+# Include directories:
+set(PLAT_INCLUDE_DIRS
+ ${PLAT_BSP_INCLUDES}
+ ${PLAT_HAL}/utils/include
+ ${PLAT_HAL}/images/include
+ ${PLAT_HAL}/data_presentation/lcd/include
+ ${PLAT_HAL}/timer/include
+ ${SOURCE_GEN_DIR}
+ )
+
+# Source files
+file(GLOB_RECURSE SRC_PLAT_HAL
+
+ # Higher level HAL sources - software logic implementations
+ "${PLAT_HAL}/data_*/*.c"
+ "${PLAT_HAL}/images/*.c"
+ "${PLAT_HAL}/timer/*.c"
+ "${PLAT_HAL}/utils/*.c"
+
+ # Low level HAL sources - these enable interaction with
+ # the actual hardware
+ "${PLAT_HAL}/bsp/cmsis-device/*.c"
+ "${PLAT_HAL}/bsp/bsp-core/*.c"
+ "${BSP_PACKAGE_DIR}/*.c"
+ )
diff --git a/scripts/cmake/bare-metal-toolchain.cmake b/scripts/cmake/bare-metal-toolchain.cmake
new file mode 100644
index 0000000..5d91b98
--- /dev/null
+++ b/scripts/cmake/bare-metal-toolchain.cmake
@@ -0,0 +1,65 @@
+#----------------------------------------------------------------------------
+# Copyright (c) 2021 Arm Limited. All rights reserved.
+# SPDX-License-Identifier: Apache-2.0
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#----------------------------------------------------------------------------
+# specify the cross compiler
+set(CMAKE_C_COMPILER armclang)
+set(CMAKE_CXX_COMPILER armclang)
+set(CMAKE_C_LINKER_PREFERENCE armlink)
+set(CMAKE_ASM_LINKER_PREFERENCE armlink)
+set(CMAKE_ASM_COMPILER armasm)
+set(CMAKE_ASM_COMPILER_AR armar)
+
+set(CMAKE_CROSSCOMPILING true)
+set(CMAKE_SYSTEM_NAME Generic)
+
+set(MIN_ARM_CLANG_VERSION 6.14)
+
+if (NOT DEFINED CMAKE_SYSTEM_PROCESSOR)
+ set(CMAKE_SYSTEM_PROCESSOR cortex-m55)
+endif()
+
+# Skip compiler test execution
+set(CMAKE_C_COMPILER_WORKS 1)
+set(CMAKE_CXX_COMPILER_WORKS 1)
+
+set(PLATFORM_HAL 1)
+
+set(WARNING_OPTS "-Wall -Wextra -Wvla")
+set(SPECIAL_OPTS "-fno-rtti -funsigned-char -fno-function-sections -fno-exceptions")
+set(PLATFORM_FLAGS "-mthumb --target=arm-arm-non-eabi -mlittle-endian -DPLATFORM_HAL=${PLATFORM_HAL}")
+
+set(CMAKE_C_FLAGS_DEBUG "-DDEBUG -O0")
+set(CMAKE_C_FLAGS_RELEASE "-DNDEBUG -O3")
+
+set(CMAKE_CXX_FLAGS_DEBUG "-DDEBUG -O0")
+set(CMAKE_CXX_FLAGS_RELEASE "-DNDEBUG -O3")
+
+if (CMAKE_SYSTEM_PROCESSOR STREQUAL cortex-m55)
+ # Flags for cortex-m55
+ set(CPU_CORTEX_M55 1)
+ set(CPU_CC "-mcpu=cortex-m55 -mfloat-abi=hard -MD -DCPU_CORTEX_M55=1 -DARM_MATH_DSP -DARM_MATH_LOOPUNROLL -D__FPU_USED=1")
+ set(CPU_LD "--cpu=8.1-M.Main.dsp")
+elseif(CMAKE_SYSTEM_PROCESSOR STREQUAL cortex-m33)
+ # Flags for cortex-m33 to go here
+endif()
+
+set(ALL_COMMON_FLAGS "${CPU_CC} ${WARNING_OPTS} ${SPECIAL_OPTS} ${PLATFORM_FLAGS}")
+
+function(enforce_compiler_version)
+ if(CMAKE_CXX_COMPILER_VERSION VERSION_LESS ${MIN_ARM_CLANG_VERSION})
+ message( FATAL_ERROR "Arm compiler version must be ${MIN_ARM_CLANG_VERSION} or greater to support ${CMAKE_SYSTEM_PROCESSOR} architecture." )
+ endif()
+endfunction()
diff --git a/scripts/cmake/cmsis-dsp.cmake b/scripts/cmake/cmsis-dsp.cmake
new file mode 100644
index 0000000..cb0243b
--- /dev/null
+++ b/scripts/cmake/cmsis-dsp.cmake
@@ -0,0 +1,74 @@
+#----------------------------------------------------------------------------
+# Copyright (c) 2021 Arm Limited. All rights reserved.
+# SPDX-License-Identifier: Apache-2.0
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#----------------------------------------------------------------------------
+
+# CMSIS-DSP library CMake helper script.
+
+# 1. We should be cross-compiling (non-native target)
+if (TARGET_PLATFORM STREQUAL native)
+ message(FATAL_ERROR "No CMSIS-DSP support for native target.")
+endif()
+
+# 2. Check if CMSIS sources have been defined
+if (NOT DEFINED CMSIS_SRC_PATH)
+ message(FATAL_ERROR "CMSIS path should be defined for CMSIS-DSP library to be built")
+endif()
+
+# 3. Form a list of all the sources we need in CSMS-DSP library
+set(CMSIS_DSP_PATH_SUFFIX "CMSIS/DSP")
+set(CMSIS_CORE_PATH_SUFFIX "CMSIS/Core")
+set(CMSIS_DSP_SRC_DIR "${CMSIS_SRC_PATH}/${CMSIS_DSP_PATH_SUFFIX}/Source")
+set(CMSIS_DSP_INC_DIR "${CMSIS_SRC_PATH}/${CMSIS_DSP_PATH_SUFFIX}/Include")
+set(CMSIS_DSP_PRI_INC_DIR "${CMSIS_SRC_PATH}/${CMSIS_DSP_PATH_SUFFIX}/PrivateInclude")
+set(CMSIS_CORE_INC_DIR "${CMSIS_SRC_PATH}/${CMSIS_CORE_PATH_SUFFIX}/Include")
+
+file(GLOB_RECURSE
+ CMSIS_DSP_SRC
+ "${CMSIS_DSP_SRC_DIR}/arm_*.c")
+
+# 4. Create static library
+set(CMSIS_DSP_TARGET cmsis-dsp)
+
+add_library(${CMSIS_DSP_TARGET} STATIC ${CMSIS_DSP_SRC})
+
+target_include_directories(${CMSIS_DSP_TARGET} PUBLIC
+ ${CMSIS_DSP_INC_DIR}
+ ${CMSIS_CORE_INC_DIR})
+target_include_directories(${CMSIS_DSP_TARGET} PRIVATE
+ ${CMSIS_DSP_PRI_INC_DIR})
+
+# 5. Add any custom/conditional flags for compilation or linkage
+if (${CMAKE_SYSTEM_PROCESSOR} STREQUAL cortex-m55)
+ target_compile_definitions(${CMSIS_DSP_TARGET} PUBLIC
+ ARM_MATH_MVEI
+ ARM_MATH_DSP
+ ARM_MATH_LOOPUNROLL)
+elseif(${CMAKE_SYSTEM_PROCESSOR} STREQUAL cortex-m33)
+ # Placeholder, if building with Cortex-M33
+endif()
+
+
+# 6. Provide the library path for the top level CMake to use:
+set(CMSIS_DSP_LIB "${CMAKE_LIBRARY_OUTPUT_DIRECTORY}/lib${CMSIS_DSP_TARGET}.a")
+message(STATUS "CMSIS_DSP_LIB set to be generated here: ${CMSIS_DSP_LIB}")
+
+message(STATUS "CMAKE_CURRENT_SOURCE_DIR: " ${CMAKE_CURRENT_SOURCE_DIR})
+message(STATUS "*******************************************************")
+message(STATUS "Library : " ${CMSIS_DSP_TARGET})
+message(STATUS "Build type : " ${CMAKE_BUILD_TYPE})
+message(STATUS "TARGET_PLATFORM : " ${TARGET_PLATFORM})
+message(STATUS "CMAKE_SYSTEM_PROCESSOR : " ${CMAKE_SYSTEM_PROCESSOR})
+message(STATUS "*******************************************************")
diff --git a/scripts/cmake/native-sources.cmake b/scripts/cmake/native-sources.cmake
new file mode 100644
index 0000000..743e075
--- /dev/null
+++ b/scripts/cmake/native-sources.cmake
@@ -0,0 +1,58 @@
+#----------------------------------------------------------------------------
+# Copyright (c) 2021 Arm Limited. All rights reserved.
+# SPDX-License-Identifier: Apache-2.0
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#----------------------------------------------------------------------------
+# Set the install prefix
+set(CMAKE_INSTALL_PREFIX ${CMAKE_SOURCE_DIR}/build_native)
+set(PLAT_HAL ${CMAKE_CURRENT_SOURCE_DIR}/source/application/hal/platforms/native)
+
+if (ETHOS_U55_ENABLED)
+ message(WARNING "EthosU can't be enabled for native builds."
+ "Use -DETHOS_U55_ENABLED=0 flag for this target platform."
+ "Overriding, disabling use of EthosU...")
+ set(ETHOS_U55_ENABLED OFF)
+endif()
+
+if (DEFINED LOG_LEVEL)
+ message(STATUS "Setting log level to ${LOG_LEVEL}")
+ set (LOG_FLAG "-DLOG_LEVEL=${LOG_LEVEL}")
+endif()
+
+set(TENSORFLOW_LITE_MICRO_PLATFORM_LIB_NAME "libtensorflow-microlite.a")
+set(TENSORFLOW_LITE_MICRO_FLAGS "-DTF_LITE_STATIC_MEMORY -DACTIVATION_BUF_SRAM_SZ=0")
+
+set(CMAKE_C_FLAGS
+ "${WARNING_FLAGS} ${SPECIAL_OPTS} ${PLATFORM_FLAGS}\
+ ${PROFILING_OPT} ${TF_FLAG} ${LOG_FLAG} ${TENSORFLOW_LITE_MICRO_FLAGS}"
+ CACHE INTERNAL "")
+set(CMAKE_CXX_FLAGS
+ "${WARNING_FLAGS} ${SPECIAL_OPTS} ${SPECIAL_OPTS_CXX}\
+ ${PLATFORM_FLAGS} ${PROFILING_OPT} ${TF_FLAG} ${LOG_FLAG}\
+ ${TENSORFLOW_LITE_MICRO_FLAGS}"
+ CACHE INTERNAL "")
+
+# Include directories:
+set(PLAT_INCLUDE_DIRS
+ ${PLAT_HAL}/utils/include
+ ${PLAT_HAL}/images/include
+ ${PLAT_HAL}/data_presentation/log/include
+ ${PLAT_HAL}/timer/include
+ )
+
+# Source files
+file(GLOB_RECURSE SRC_PLAT_HAL
+ "${PLAT_HAL}/**/*.c"
+ "${PLAT_HAL}/**/*.cc"
+ )
diff --git a/scripts/cmake/native-toolchain.cmake b/scripts/cmake/native-toolchain.cmake
new file mode 100644
index 0000000..2e28cd4
--- /dev/null
+++ b/scripts/cmake/native-toolchain.cmake
@@ -0,0 +1,40 @@
+#----------------------------------------------------------------------------
+# Copyright (c) 2021 Arm Limited. All rights reserved.
+# SPDX-License-Identifier: Apache-2.0
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#----------------------------------------------------------------------------
+set(CMAKE_CXX_COMPILER g++)
+set(CMAKE_C_COMPILER gcc)
+set(CMAKE_C_LINKER_PREFERENCE gcc)
+set(CMAKE_CXX_LINKER_PREFERENCE gcc)
+
+set(CMAKE_C_FLAGS_DEBUG "-DDEBUG -O0 -g")
+set(CMAKE_C_FLAGS_RELEASE "-DNDEBUG -O3")
+
+set(CMAKE_CXX_FLAGS_DEBUG "-DDEBUG -O0 -g")
+set(CMAKE_CXX_FLAGS_RELEASE "-DNDEBUG -O3")
+
+# Platform specific directory:
+set(PLATFORM_HAL 3)
+set(WARNING_FLAGS "-Wsign-compare -Wshadow \
+ -Wextra -Wall -Wunused-function \
+ -Wmissing-field-initializers \
+ -Wswitch -Wvla -Wunused-parameter")
+set(SPECIAL_OPTS "-fPIC -pthread")
+set(PLATFORM_FLAGS "-DPLATFORM_HAL=${PLATFORM_HAL}")
+set(SPECIAL_OPTS_CXX "-fno-threadsafe-statics")
+set(CMAKE_EXE_LINKER_FLAGS "-lm -lc -lstdc++ --verbose")
+
+function(enforce_compiler_version)
+endfunction()
diff --git a/scripts/cmake/source_gen_utils.cmake b/scripts/cmake/source_gen_utils.cmake
new file mode 100644
index 0000000..8653016
--- /dev/null
+++ b/scripts/cmake/source_gen_utils.cmake
@@ -0,0 +1,270 @@
+#----------------------------------------------------------------------------
+# Copyright (c) 2021 Arm Limited. All rights reserved.
+# SPDX-License-Identifier: Apache-2.0
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#----------------------------------------------------------------------------
+set(SCRIPTS_DIR ${CMAKE_CURRENT_SOURCE_DIR}/scripts)
+
+##############################################################################
+# This function generates C++ files for images located in the directory it is
+# pointed at. NOTE: uses python
+##############################################################################
+function(generate_images_code input_dir src_out hdr_out img_size)
+
+ # Absolute paths for passing into python script
+ get_filename_component(input_dir_abs ${input_dir} ABSOLUTE)
+ get_filename_component(src_out_abs ${src_out} ABSOLUTE)
+ get_filename_component(hdr_out_abs ${hdr_out} ABSOLUTE)
+
+ message(STATUS "Generating image files from ${input_dir_abs}")
+ execute_process(
+ COMMAND ${PYTHON} ${SCRIPTS_DIR}/py/gen_rgb_cpp.py
+ --image_path ${input_dir_abs}
+ --source_folder_path ${src_out_abs}
+ --header_folder_path ${hdr_out_abs}
+ --image_size ${img_size} ${img_size}
+ RESULT_VARIABLE return_code
+ )
+ if (NOT return_code EQUAL "0")
+ message(FATAL_ERROR "Failed to generate image files.")
+ endif ()
+
+endfunction()
+
+##############################################################################
+# This function generates C++ files for audio files located in the directory it is
+# pointed at. NOTE: uses python
+##############################################################################
+function(generate_audio_code input_dir src_out hdr_out s_rate_opt mono_opt off_opt duration_opt res_type_opt min_sample_opt)
+
+ # Absolute paths for passing into python script
+ get_filename_component(input_dir_abs ${input_dir} ABSOLUTE)
+ get_filename_component(src_out_abs ${src_out} ABSOLUTE)
+ get_filename_component(hdr_out_abs ${hdr_out} ABSOLUTE)
+
+ to_py_bool(mono_opt mono_opt_py)
+
+ message(STATUS "Generating audio files from ${input_dir_abs}")
+ execute_process(
+ COMMAND ${PYTHON} ${SCRIPTS_DIR}/py/gen_audio_cpp.py
+ --audio_path ${input_dir_abs}
+ --source_folder_path ${src_out_abs}
+ --header_folder_path ${hdr_out_abs}
+ --sampling_rate ${s_rate_opt}
+ --mono ${mono_opt_py}
+ --offset ${off_opt}
+ --duration ${duration_opt}
+ --res_type ${res_type_opt}
+ --min_samples ${min_sample_opt}
+ RESULT_VARIABLE return_code
+ )
+ if (NOT return_code EQUAL "0")
+ message(FATAL_ERROR "Failed to generate audio files.")
+ endif ()
+
+endfunction()
+
+##############################################################################
+# This function generates default empty input C++ files for applications with no
+# external input. Main use is for the inference runner. NOTE: uses python
+##############################################################################
+function(generate_default_input_code hdr_out)
+
+ # Absolute paths for passing into python script
+ get_filename_component(hdr_out_abs ${hdr_out} ABSOLUTE)
+
+ message(STATUS "Generating default input files")
+ execute_process(
+ COMMAND ${PYTHON} ${SCRIPTS_DIR}/py/gen_default_input_cpp.py
+ --header_folder_path ${hdr_out_abs}
+ RESULT_VARIABLE return_code
+ )
+ if (NOT return_code EQUAL "0")
+ message(FATAL_ERROR "Failed to generate default input .")
+ endif ()
+
+endfunction()
+##############################################################################
+# This function generates C++ files for tflite NN model files.
+# @param[in] MODEL_PATH path to a tflite file
+# @param[in] DESTINATION directory in which the output cc must be
+# placed
+# @param[in] EXPRESSIONS C++ code expressions to add to the generated file
+# @param[in] NAMESPACE model name space
+# NOTE: Uses python
+##############################################################################
+function(generate_tflite_code)
+
+ set(multiValueArgs EXPRESSIONS NAMESPACE)
+ set(oneValueArgs MODEL_PATH DESTINATION)
+ cmake_parse_arguments(PARSED "" "${oneValueArgs}" "${multiValueArgs}" ${ARGN} )
+
+ # Absolute paths for passing into python script
+ get_filename_component(ABS_MODEL_PATH ${PARSED_MODEL_PATH} ABSOLUTE)
+ get_filename_component(ABS_DESTINATION ${PARSED_DESTINATION} ABSOLUTE)
+
+ if (EXISTS ${ABS_MODEL_PATH})
+ message(STATUS "Using ${ABS_MODEL_PATH}")
+ else ()
+ message(FATAL_ERROR "${ABS_MODEL_PATH} not found!")
+ endif ()
+
+
+ foreach(expression ${PARSED_EXPRESSIONS})
+ set(py_arg_exp ${py_arg_exp} --expression=${expression})
+ endforeach()
+
+ foreach(name ${PARSED_NAMESPACE})
+ set(py_arg_exp ${py_arg_exp} --namespaces=${name})
+ endforeach()
+
+ execute_process(
+ COMMAND ${PYTHON} ${SCRIPTS_DIR}/py/gen_model_cpp.py
+ --tflite_path ${ABS_MODEL_PATH}
+ --output_dir ${ABS_DESTINATION} ${py_arg_exp}
+ RESULT_VARIABLE return_code
+ )
+ if (NOT return_code EQUAL "0")
+ message(FATAL_ERROR "Failed to generate model files.")
+ endif ()
+endfunction()
+
+
+##############################################################################
+# This function generates C++ file for a given labels' text file.
+# @param[in] INPUT Path to the label text file
+# @param[in] DESTINATION_SRC directory in which the output cc must be
+# placed
+# @param[in] DESTINATION_HDR directory in which the output h file must be
+# placed
+# @param[in] OUTPUT_FILENAME Path to required output file
+# @param[in] NAMESPACE data name space
+# NOTE: Uses python
+##############################################################################
+function(generate_labels_code)
+
+ set(multiValueArgs NAMESPACE)
+ set(oneValueArgs INPUT DESTINATION_SRC DESTINATION_HDR OUTPUT_FILENAME)
+ cmake_parse_arguments(PARSED "" "${oneValueArgs}" "${multiValueArgs}" ${ARGN} )
+
+ # Absolute paths for passing into python script
+ get_filename_component(input_abs ${PARSED_INPUT} ABSOLUTE)
+ get_filename_component(src_out_abs ${PARSED_DESTINATION_SRC} ABSOLUTE)
+ get_filename_component(hdr_out_abs ${PARSED_DESTINATION_HDR} ABSOLUTE)
+
+ message(STATUS "Generating labels file from ${PARSED_INPUT}")
+ file(REMOVE "${hdr_out_abs}/${PARSED_OUTPUT_FILENAME}.hpp")
+ file(REMOVE "${src_out_abs}/${PARSED_OUTPUT_FILENAME}.cc")
+
+ foreach(name ${PARSED_NAMESPACE})
+ set(py_arg_exp ${py_arg_exp} --namespaces=${name})
+ endforeach()
+
+ message(STATUS "writing to ${hdr_out_abs}/${PARSED_OUTPUT_FILENAME}.hpp and ${src_out_abs}/${PARSED_OUTPUT_FILENAME}.cc")
+ execute_process(
+ COMMAND ${PYTHON} ${SCRIPTS_DIR}/py/gen_labels_cpp.py
+ --labels_file ${input_abs}
+ --source_folder_path ${src_out_abs}
+ --header_folder_path ${hdr_out_abs}
+ --output_file_name ${PARSED_OUTPUT_FILENAME} ${py_arg_exp}
+ RESULT_VARIABLE return_code
+ )
+ if (NOT return_code EQUAL "0")
+ message(FATAL_ERROR "Failed to generate label files.")
+ endif ()
+endfunction()
+
+
+##############################################################################
+# This function generates C++ data files for test located in the directory it is
+# pointed at.
+# @param[in] INPUT_DIR directory in which are the npy files
+# @param[in] DESTINATION_SRC directory in which the output cc must be
+# placed
+# @param[in] DESTINATION_HDR directory in which the output h file must be
+# placed
+# @param[in] USECASE name of the sub-usecase
+# @param[in] NAMESPACE data name space
+# NOTE: Uses python
+##############################################################################
+function(generate_test_data_code)
+
+ set(multiValueArgs NAMESPACE)
+ set(oneValueArgs INPUT_DIR DESTINATION_SRC DESTINATION_HDR USECASE)
+ cmake_parse_arguments(PARSED "" "${oneValueArgs}" "${multiValueArgs}" ${ARGN} )
+
+ # Absolute paths for passing into python script
+ get_filename_component(input_dir_abs ${PARSED_INPUT_DIR} ABSOLUTE)
+ get_filename_component(src_out_abs ${PARSED_DESTINATION_SRC} ABSOLUTE)
+ get_filename_component(hdr_out_abs ${PARSED_DESTINATION_HDR} ABSOLUTE)
+
+ foreach(name ${PARSED_NAMESPACE})
+ set(py_arg_exp ${py_arg_exp} --namespaces=${name})
+ endforeach()
+
+ message(STATUS "Generating test ifm and ofm files from ${input_dir_abs}")
+ execute_process(
+ COMMAND ${PYTHON} ${SCRIPTS_DIR}/py/gen_test_data_cpp.py
+ --data_folder_path ${input_dir_abs}
+ --source_folder_path ${src_out_abs}
+ --header_folder_path ${hdr_out_abs}
+ --usecase ${PARSED_USECASE}
+ ${py_arg_exp}
+ RESULT_VARIABLE return_code
+ )
+ if (NOT return_code EQUAL "0")
+ message(FATAL_ERROR "Failed to generate test data files.")
+ endif ()
+
+endfunction()
+
+
+##############################################################################
+# Function to prepare a python virtual environment for running the functions
+# outlined above.
+##############################################################################
+function(setup_source_generator)
+ if (${CMAKE_HOST_WIN32})
+# windows python3 has python.exe
+ set(PY_EXEC python)
+ set(PYTHON ${CMAKE_BINARY_DIR}/pyenv/Scripts/${PY_EXEC})
+ else()
+ set(PY_EXEC python3)
+ set(PYTHON ${CMAKE_BINARY_DIR}/pyenv/bin/${PY_EXEC})
+ endif()
+ set(PYTHON ${PYTHON} PARENT_SCOPE)
+
+ if (EXISTS ${PYTHON})
+ message(STATUS "Using existing python at ${PYTHON}")
+ return()
+ endif ()
+ message(STATUS "Configuring python environment at ${PYTHON}")
+ execute_process(
+ COMMAND ${PY_EXEC} -m venv ${CMAKE_BINARY_DIR}/pyenv
+ RESULT_VARIABLE return_code
+ )
+ if (NOT return_code EQUAL "0")
+ message(FATAL_ERROR "Failed to setup python3 environment")
+ endif ()
+
+ execute_process(COMMAND ${PYTHON} -m pip install wheel)
+
+ execute_process(
+ COMMAND ${PYTHON} -m pip install -r ${SCRIPTS_DIR}/py/requirements.txt
+ RESULT_VARIABLE return_code
+ )
+ if (NOT return_code EQUAL "0")
+ message(FATAL_ERROR "Failed to setup python3 environment")
+ endif ()
+endfunction()
diff --git a/scripts/cmake/subsystem-profiles/corstone-sse-200.cmake b/scripts/cmake/subsystem-profiles/corstone-sse-200.cmake
new file mode 100644
index 0000000..8e2cd98
--- /dev/null
+++ b/scripts/cmake/subsystem-profiles/corstone-sse-200.cmake
@@ -0,0 +1,255 @@
+#----------------------------------------------------------------------------
+# Copyright (c) 2021 Arm Limited. All rights reserved.
+# SPDX-License-Identifier: Apache-2.0
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#----------------------------------------------------------------------------
+
+# CMake configuration file for peripheral memory map for MPS3 as per SSE-200 design
+###################################################################################################
+# Application specific config #
+###################################################################################################
+
+# This parameter is based on the linker/scatter script for SSE-200. Do not change this parameter
+# in isolation.
+set(ACTIVATION_BUF_SRAM_SZ "0x00200000" CACHE STRING "Maximum SRAM size for activation buffers")
+set(DESIGN_NAME "SSE-200" CACHE STRING "Design name")
+###################################################################################################
+# Mem sizes #
+###################################################################################################
+set(ITCM_SIZE "0x00100000" CACHE STRING "ITCM size: 1 MiB")
+set(DTCM_BLK_SIZE "0x00100000" CACHE STRING "DTCM size: 1 MiB, 4 banks")
+set(BRAM_SIZE "0x00200000" CACHE STRING "BRAM size: 2 MiB")
+set(QSPI_SRAM_SIZE "0x00800000" CACHE STRING "QSPI Flash size: 8 MiB")
+set(DDR4_BLK_SIZE "0x10000000" CACHE STRING "DDR4 block size: 256 MiB")
+
+###################################################################################################
+# Base addresses #
+###################################################################################################
+set(ITCM_BASE_NS "0x00000000" CACHE STRING "Instruction TCM Non-Secure base address")
+set(BRAM_BASE_NS "0x01000000" CACHE STRING "CODE SRAM Non-Secure base address")
+set(DTCM0_BASE_NS "0x20000000" CACHE STRING "Data TCM block 0 Non-Secure base address")
+set(DTCM1_BASE_NS "0x20100000" CACHE STRING "Data TCM block 1 Non-Secure base address")
+set(DTCM2_BASE_NS "0x20200000" CACHE STRING "Data TCM block 2 Non-Secure base address")
+set(DTCM3_BASE_NS "0x20300000" CACHE STRING "Data TCM block 3 Non-Secure base address")
+set(QSPI_SRAM_BASE_NS "0x28000000" CACHE STRING "QSPI SRAM Non-Secure base address")
+set(DDR4_BLK0_BASE_NS "0x60000000" CACHE STRING "DDR4 block 0 Non-Secure base address")
+set(DDR4_BLK1_BASE_NS "0x80000000" CACHE STRING "DDR4 block 1 Non-Secure base address")
+set(DDR4_BLK2_BASE_NS "0xA0000000" CACHE STRING "DDR4 block 2 Non-Secure base address")
+set(DDR4_BLK3_BASE_NS "0xC0000000" CACHE STRING "DDR4 block 3 Non-Secure base address")
+
+set(ITCM_BASE_S "0x10000000" CACHE STRING "Instruction TCM Secure base address")
+set(BRAM_BASE_S "0x11000000" CACHE STRING "CODE SRAM Secure base address")
+set(DTCM0_BASE_S "0x30000000" CACHE STRING "Data TCM block 0 Secure base address")
+set(DTCM1_BASE_S "0x30100000" CACHE STRING "Data TCM block 1 Secure base address")
+set(DTCM2_BASE_S "0x30200000" CACHE STRING "Data TCM block 2 Secure base address")
+set(DTCM3_BASE_S "0x30300000" CACHE STRING "Data TCM block 3 Secure base address")
+set(DDR4_BLK0_BASE_S "0x70000000" CACHE STRING "DDR4 block 0 Secure base address")
+set(DDR4_BLK1_BASE_S "0x90000000" CACHE STRING "DDR4 block 1 Secure base address")
+set(DDR4_BLK2_BASE_S "0xB0000000" CACHE STRING "DDR4 block 2 Secure base address")
+set(DDR4_BLK3_BASE_S "0xD0000000" CACHE STRING "DDR4 block 3 Secure base address")
+
+set(CMSDK_GPIO0_BASE "0x41100000" CACHE STRING "User GPIO 0 Base Address")
+set(CMSDK_GPIO1_BASE "0x41101000" CACHE STRING "User GPIO 1 Base Address")
+set(CMSDK_GPIO2_BASE "0x41102000" CACHE STRING "User GPIO 2 Base Address")
+set(CMSDK_GPIO3_BASE "0x41103000" CACHE STRING "User GPIO 3 Base Address")
+
+if (ETHOS_U55_ENABLED)
+ set(ETHOS_U55_BASE "0x41700000" CACHE STRING "Ethos-U55 base address")
+ set(ETHOS_U55_TA0_BASE "0x41701000" CACHE STRING "Ethos-U55's timing adapter 0 base address")
+ set(ETHOS_U55_TA1_BASE "0x41701200" CACHE STRING "Ethos-U55's timing adapter 1 base address")
+endif ()
+
+set(MPS3_I2C0_BASE "0x41200000" CACHE STRING "Touch Screen I2C Base Address ")
+set(MPS3_I2C1_BASE "0x41201000" CACHE STRING "Audio Interface I2C Base Address ")
+set(MPS3_SSP2_BASE "0x41202000" CACHE STRING "ADC SPI PL022 Base Address")
+set(MPS3_SSP3_BASE "0x41203000" CACHE STRING "Shield 0 SPI PL022 Base Address")
+
+set(MPS3_SSP4_BASE "0x41204000" CACHE STRING "Shield 1 SPI PL022 Base Address")
+set(MPS3_I2C2_BASE "0x41205000" CACHE STRING "Shield 0 SBCon Base Address ")
+set(MPS3_I2C3_BASE "0x41206000" CACHE STRING "Shield 1 SBCon Base Address ")
+
+set(MPS3_I2C4_BASE "0x41207000" CACHE STRING "HDMI I2C SBCon Base Address ")
+set(MPS3_I2C5_BASE "0x41208000" CACHE STRING "DDR EPROM I2C SBCon Base Address ")
+set(MPS3_SCC_BASE "0x41300000" CACHE STRING "SCC Base Address ")
+set(MPS3_AAIC_I2S_BASE "0x41301000" CACHE STRING "Audio Interface I2S Base Address ")
+set(MPS3_FPGAIO_BASE "0x41302000" CACHE STRING "FPGA IO Base Address ")
+set(CMSDK_UART0_BASE "0x41303000" CACHE STRING "UART 0 Base Address ")
+set(CMSDK_UART1_BASE "0x41304000" CACHE STRING "UART 1 Base Address ")
+set(CMSDK_UART2_BASE "0x41305000" CACHE STRING "UART 2 Base Address ")
+set(CMSDK_UART3_BASE "0x41306000" CACHE STRING "UART 3 Base Address Shield 0")
+
+set(CMSDK_UART4_BASE "0x41307000" CACHE STRING "UART 4 Base Address Shield 1")
+set(CMSDK_UART5_BASE "0x41308000" CACHE STRING "UART 5 Base Address ")
+set(HDMI_AUDIO_BASE "0x41309000" CACHE STRING "HDMI AUDIO Base Address ")
+set(CLCD_CONFIG_BASE "0x4130A000" CACHE STRING "CLCD CONFIG Base Address ")
+set(RTC_BASE "0x4130B000" CACHE STRING "RTC Base address ")
+set(SMSC9220_BASE "0x41400000" CACHE STRING "Ethernet SMSC9220 Base Address ")
+set(USB_BASE "0x41500000" CACHE STRING "USB Base Address ")
+
+set(MPS3_eMMC_BASE "0x41702000" CACHE STRING "User eMMC Base Address")
+set(USER_BASE "0x41703000" CACHE STRING "User ? Base Address ")
+
+set(QSPI_XIP_BASE "0x41800000" CACHE STRING "QSPI XIP config Base Address ")
+set(QSPI_WRITE_BASE "0x41801000" CACHE STRING "QSPI write config Base Address ")
+
+set(SEC_CMSDK_GPIO0_BASE "0x51100000" CACHE STRING "User GPIO 0 Base Address")
+set(SEC_CMSDK_GPIO1_BASE "0x51101000" CACHE STRING "User GPIO 0 Base Address")
+set(SEC_CMSDK_GPIO2_BASE "0x51102000" CACHE STRING "User GPIO 0 Base Address")
+set(SEC_CMSDK_GPIO3_BASE "0x51103000" CACHE STRING "User GPIO 0 Base Address")
+
+set(SEC_MPS3_I2C0_BASE "0x51200000" CACHE STRING "Touch Screen I2C Base Address ")
+set(SEC_MPS3_I2C1_BASE "0x51201000" CACHE STRING "Audio Interface I2C Base Address ")
+set(SEC_MPS3_SSP2_BASE "0x51202000" CACHE STRING "ADC SPI PL022 Base Address")
+set(SEC_MPS3_SSP3_BASE "0x51203000" CACHE STRING "Shield 0 SPI PL022 Base Address")
+
+set(SEC_MPS3_SSP4_BASE "0x51204000" CACHE STRING "Shield 1 SPI PL022 Base Address")
+set(SEC_MPS3_I2C2_BASE "0x51205000" CACHE STRING "Shield 0 SBCon Base Address ")
+set(SEC_MPS3_I2C3_BASE "0x51206000" CACHE STRING "Shield 1 SBCon Base Address ")
+
+set(SEC_MPS3_I2C4_BASE "0x51207000" CACHE STRING "HDMI I2C SBCon Base Address ")
+set(SEC_MPS3_I2C5_BASE "0x51208000" CACHE STRING "DDR EPROM I2C SBCon Base Address ")
+set(SEC_MPS3_SCC_BASE "0x51300000" CACHE STRING "SCC Base Address ")
+set(SEC_MPS3_AAIC_I2S_BASE "0x51301000" CACHE STRING "Audio Interface I2S Base Address ")
+set(SEC_MPS3_FPGAIO_BASE "0x51302000" CACHE STRING "FPGA IO Base Address ")
+set(SEC_CMSDK_UART0_BASE "0x51303000" CACHE STRING "UART 0 Base Address ")
+set(SEC_CMSDK_UART1_BASE "0x51304000" CACHE STRING "UART 1 Base Address ")
+set(SEC_CMSDK_UART2_BASE "0x51305000" CACHE STRING "UART 2 Base Address ")
+set(SEC_CMSDK_UART3_BASE "0x51306000" CACHE STRING "UART 3 Base Address Shield 0")
+
+set(SEC_CMSDK_UART4_BASE "0x51307000" CACHE STRING "UART 4 Base Address Shield 1")
+set(SEC_CMSDK_UART5_BASE "0x51308000" CACHE STRING "UART 5 Base Address ")
+set(SEC_HDMI_AUDIO_BASE "0x51309000" CACHE STRING "HDMI AUDIO Base Address ")
+set(SEC_CLCD_CONFIG_BASE "0x5130A000" CACHE STRING "CLCD CONFIG Base Address ")
+set(SEC_RTC_BASE "0x5130B000" CACHE STRING "RTC Base address ")
+set(SEC_SMSC9220_BASE "0x51400000" CACHE STRING "Ethernet SMSC9220 Base Address ")
+set(SEC_USB_BASE "0x51500000" CACHE STRING "USB Base Address ")
+
+if (ETHOS_U55_ENABLED)
+ set(SEC_ETHOS_U55_BASE "0x51700000" CACHE STRING "Ethos-U55 base address")
+ set(SEC_ETHOS_U55_TA0_BASE "0x51701000" CACHE STRING "Ethos-U55's timing adapter 0 base address")
+ set(SEC_ETHOS_U55_TA1_BASE "0x51701200" CACHE STRING "Ethos-U55's timing adapter 1 base address")
+endif ()
+
+set(SEC_MMC_BASE "0x51702000" CACHE STRING "User eMMC Base Address")
+set(SEC_USER_BASE "0x51703000" CACHE STRING "User ? Base Address ")
+
+set(SEC_QSPI_XIP_BASE "0x51800000" CACHE STRING "QSPI XIP config Base Address ")
+set(SEC_QSPI_WRITE_BASE "0x51801000" CACHE STRING "QSPI write config Base Address ")
+
+###################################################################################################
+# IRQ numbers #
+###################################################################################################
+set(NONSEC_WATCHDOG_RESET_IRQn " 0" CACHE STRING " Non-Secure Watchdog Reset Interrupt")
+set(NONSEC_WATCHDOG_IRQn " 1" CACHE STRING " Non-Secure Watchdog Interrupt ")
+set(S32K_TIMER_IRQn " 2" CACHE STRING " S32K Timer Interrupt ")
+set(TIMER0_IRQn " 3" CACHE STRING " TIMER 0 Interrupt ")
+set(TIMER1_IRQn " 4" CACHE STRING " TIMER 1 Interrupt ")
+set(DUALTIMER_IRQn " 5" CACHE STRING " Dual Timer Interrupt ")
+set(MPC_IRQn " 9" CACHE STRING " MPC Combined (Secure) Interrupt ")
+set(PPC_IRQn "10" CACHE STRING " PPC Combined (Secure) Interrupt ")
+set(MSC_IRQn "11" CACHE STRING " MSC Combined (Secure) Interrput ")
+set(BRIDGE_ERROR_IRQn "12" CACHE STRING " Bridge Error Combined (Secure) Interrupt ")
+
+set(UARTRX0_IRQn "32" CACHE STRING " UART 0 RX Interrupt ")
+set(UARTTX0_IRQn "33" CACHE STRING " UART 0 TX Interrupt ")
+set(UARTRX1_IRQn "34" CACHE STRING " UART 1 RX Interrupt ")
+set(UARTTX1_IRQn "35" CACHE STRING " UART 1 TX Interrupt ")
+set(UARTRX2_IRQn "36" CACHE STRING " UART 2 RX Interrupt ")
+set(UARTTX2_IRQn "37" CACHE STRING " UART 2 TX Interrupt ")
+set(UARTRX3_IRQn "38" CACHE STRING " UART 3 RX Interrupt ")
+set(UARTTX3_IRQn "39" CACHE STRING " UART 3 TX Interrupt ")
+set(UARTRX4_IRQn "40" CACHE STRING " UART 4 RX Interrupt ")
+set(UARTTX4_IRQn "41" CACHE STRING " UART 4 TX Interrupt ")
+set(UART0_IRQn "42" CACHE STRING " UART 0 combined Interrupt ")
+set(UART1_IRQn "43" CACHE STRING " UART 1 combined Interrupt ")
+set(UART2_IRQn "44" CACHE STRING " UART 2 combined Interrupt ")
+set(UART3_IRQn "45" CACHE STRING " UART 3 combined Interrupt ")
+set(UART4_IRQn "46" CACHE STRING " UART 4 combined Interrupt ")
+set(UARTOVF_IRQn "47" CACHE STRING " UART 0,1,2,3,4 Overflow Interrupt ")
+set(ETHERNET_IRQn "48" CACHE STRING " Ethernet Interrupt ")
+set(I2S_IRQn "49" CACHE STRING " I2S Interrupt ")
+set(TSC_IRQn "50" CACHE STRING " Touch Screen Interrupt ")
+set(SPI2_IRQn "52" CACHE STRING " SPI 2 Interrupt ")
+set(SPI3_IRQn "53" CACHE STRING " SPI 3 Interrupt ")
+set(SPI4_IRQn "54" CACHE STRING " SPI 4 Interrupt ")
+
+if (ETHOS_U55_ENABLED)
+ if (CPU_CORTEX_M55 EQUAL 1)
+ set(EthosU_IRQn "55" CACHE STRING " Ethos-U55 Interrupt ")
+ elseif (CPU_CORTEX_M33 EQUAL 1)
+ set(EthosU_IRQn "67" CACHE STRING " Ethos-U55 Interrupt ")
+ endif()
+endif ()
+
+set(GPIO0_IRQn "68" CACHE STRING " GPIO 0 Combined Interrupt ")
+set(GPIO1_IRQn "69" CACHE STRING " GPIO 1 Combined Interrupt ")
+set(GPIO2_IRQn "70" CACHE STRING " GPIO 2 Combined Interrupt ")
+set(GPIO3_IRQn "71" CACHE STRING " GPIO 3 Combined Interrupt ")
+
+set(GPIO0_0_IRQn "72" CACHE STRING "")
+set(GPIO0_1_IRQn "73" CACHE STRING "")
+set(GPIO0_2_IRQn "74" CACHE STRING "")
+set(GPIO0_3_IRQn "75" CACHE STRING "")
+set(GPIO0_4_IRQn "76" CACHE STRING "")
+set(GPIO0_5_IRQn "77" CACHE STRING "")
+set(GPIO0_6_IRQn "78" CACHE STRING "")
+set(GPIO0_7_IRQn "79" CACHE STRING "")
+set(GPIO0_8_IRQn "80" CACHE STRING "")
+set(GPIO0_9_IRQn "81" CACHE STRING "")
+set(GPIO0_10_IRQn "82" CACHE STRING "")
+set(GPIO0_11_IRQn "83" CACHE STRING "")
+set(GPIO0_12_IRQn "84" CACHE STRING "")
+set(GPIO0_13_IRQn "85" CACHE STRING "")
+set(GPIO0_14_IRQn "86" CACHE STRING "")
+set(GPIO0_15_IRQn "87" CACHE STRING "")
+set(GPIO1_0_IRQn "88" CACHE STRING "")
+set(GPIO1_1_IRQn "89" CACHE STRING "")
+set(GPIO1_2_IRQn "90" CACHE STRING "")
+set(GPIO1_3_IRQn "91" CACHE STRING "")
+set(GPIO1_4_IRQn "92" CACHE STRING "")
+set(GPIO1_5_IRQn "93" CACHE STRING "")
+set(GPIO1_6_IRQn "94" CACHE STRING "")
+set(GPIO1_7_IRQn "95" CACHE STRING "")
+set(GPIO1_8_IRQn "96" CACHE STRING "")
+set(GPIO1_9_IRQn "97" CACHE STRING "")
+set(GPIO1_10_IRQn "98" CACHE STRING "")
+set(GPIO1_11_IRQn "99" CACHE STRING "")
+set(GPIO1_12_IRQn "100" CACHE STRING "")
+set(GPIO1_13_IRQn "101" CACHE STRING "")
+set(GPIO1_14_IRQn "102" CACHE STRING "")
+set(GPIO1_15_IRQn "103" CACHE STRING "")
+set(GPIO2_0_IRQn "104" CACHE STRING "")
+set(GPIO2_1_IRQn "105" CACHE STRING "")
+set(GPIO2_2_IRQn "106" CACHE STRING "")
+set(GPIO2_3_IRQn "107" CACHE STRING "")
+set(GPIO2_4_IRQn "108" CACHE STRING "")
+set(GPIO2_5_IRQn "109" CACHE STRING "")
+set(GPIO2_6_IRQn "110" CACHE STRING "")
+set(GPIO2_7_IRQn "111" CACHE STRING "")
+set(GPIO2_8_IRQn "112" CACHE STRING "")
+set(GPIO2_9_IRQn "113" CACHE STRING "")
+set(GPIO2_10_IRQn "114" CACHE STRING "")
+set(GPIO2_11_IRQn "115" CACHE STRING "")
+set(GPIO2_12_IRQn "116" CACHE STRING "")
+set(GPIO2_13_IRQn "117" CACHE STRING "")
+set(GPIO2_14_IRQn "118" CACHE STRING "")
+set(GPIO2_15_IRQn "119" CACHE STRING "")
+set(GPIO3_0_IRQn "120" CACHE STRING "")
+set(GPIO3_1_IRQn "121" CACHE STRING "")
+set(GPIO3_2_IRQn "122" CACHE STRING "")
+set(GPIO3_3_IRQn "123" CACHE STRING "")
+set(UARTRX5_IRQn "124" CACHE STRING "UART 5 RX Interrupt")
+set(UARTTX5_IRQn "125" CACHE STRING "UART 5 TX Interrupt")
+set(UART5_IRQn "126" CACHE STRING "UART 5 combined Interrupt")
+set(HDCLCD_IRQn "127" CACHE STRING "HDCLCD Interrupt")
diff --git a/scripts/cmake/subsystem-profiles/corstone-sse-300.cmake b/scripts/cmake/subsystem-profiles/corstone-sse-300.cmake
new file mode 100644
index 0000000..8b565fe
--- /dev/null
+++ b/scripts/cmake/subsystem-profiles/corstone-sse-300.cmake
@@ -0,0 +1,309 @@
+#----------------------------------------------------------------------------
+# Copyright (c) 2021 Arm Limited. All rights reserved.
+# SPDX-License-Identifier: Apache-2.0
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#----------------------------------------------------------------------------
+
+# CMake configuration file for peripheral memory map for MPS3 as per SSE-300 design
+###################################################################################################
+# Application specific config #
+###################################################################################################
+
+# This parameter is based on the linker/scatter script for SSE-300. Do not change this parameter
+# in isolation.
+set(ACTIVATION_BUF_SRAM_SZ "0x00400000" CACHE STRING "Maximum SRAM size for activation buffers")
+set(DESIGN_NAME "Arm Corstone-300 (SSE-300)" CACHE STRING "Design name")
+
+###################################################################################################
+# Mem sizes #
+###################################################################################################
+set(ITCM_SIZE "0x00080000" CACHE STRING "ITCM size: 512 kiB")
+set(DTCM_BLK_SIZE "0x00020000" CACHE STRING "DTCM size: 128 kiB, 4 banks")
+set(BRAM_SIZE "0x00200000" CACHE STRING "BRAM size: 2 MiB")
+set(ISRAM0_SIZE "0x00200000" CACHE STRING "ISRAM0 size: 2 MiB")
+set(ISRAM1_SIZE "0x00200000" CACHE STRING "ISRAM1 size: 2 MiB")
+set(QSPI_SRAM_SIZE "0x00800000" CACHE STRING "QSPI Flash size: 8 MiB")
+set(DDR4_BLK_SIZE "0x10000000" CACHE STRING "DDR4 block size: 256 MiB")
+
+###################################################################################################
+# Base addresses for memory regions #
+###################################################################################################
+set(ITCM_BASE_NS "0x00000000" CACHE STRING "Instruction TCM Non-Secure base address")
+set(BRAM_BASE_NS "0x01000000" CACHE STRING "CODE SRAM Non-Secure base address")
+set(DTCM0_BASE_NS "0x20000000" CACHE STRING "Data TCM block 0 Non-Secure base address")
+set(DTCM1_BASE_NS "0x20020000" CACHE STRING "Data TCM block 1 Non-Secure base address")
+set(DTCM2_BASE_NS "0x20040000" CACHE STRING "Data TCM block 2 Non-Secure base address")
+set(DTCM3_BASE_NS "0x20060000" CACHE STRING "Data TCM block 3 Non-Secure base address")
+set(ISRAM0_BASE_NS "0x21000000" CACHE STRING "Internal SRAM Area Non-Secure base address")
+set(ISRAM1_BASE_NS "0x21200000" CACHE STRING "Internal SRAM Area Non-Secure base address")
+set(QSPI_SRAM_BASE_NS "0x28000000" CACHE STRING "QSPI SRAM Non-Secure base address")
+set(DDR4_BLK0_BASE_NS "0x60000000" CACHE STRING "DDR4 block 0 Non-Secure base address")
+set(DDR4_BLK1_BASE_NS "0x80000000" CACHE STRING "DDR4 block 1 Non-Secure base address")
+set(DDR4_BLK2_BASE_NS "0xA0000000" CACHE STRING "DDR4 block 2 Non-Secure base address")
+set(DDR4_BLK3_BASE_NS "0xC0000000" CACHE STRING "DDR4 block 3 Non-Secure base address")
+
+set(ITCM_BASE_S "0x10000000" CACHE STRING "Instruction TCM Secure base address")
+set(BRAM_BASE_S "0x11000000" CACHE STRING "CODE SRAM Secure base address")
+set(DTCM0_BASE_S "0x30000000" CACHE STRING "Data TCM block 0 Secure base address")
+set(DTCM1_BASE_S "0x30020000" CACHE STRING "Data TCM block 1 Secure base address")
+set(DTCM2_BASE_S "0x30040000" CACHE STRING "Data TCM block 2 Secure base address")
+set(DTCM3_BASE_S "0x30060000" CACHE STRING "Data TCM block 3 Secure base address")
+set(ISRAM0_BASE_S "0x31000000" CACHE STRING "Internal SRAM Area Secure base address")
+set(ISRAM1_BASE_S "0x31200000" CACHE STRING "Internal SRAM Area Secure base address")
+set(DDR4_BLK0_BASE_S "0x70000000" CACHE STRING "DDR4 block 0 Secure base address")
+set(DDR4_BLK1_BASE_S "0x90000000" CACHE STRING "DDR4 block 1 Secure base address")
+set(DDR4_BLK2_BASE_S "0xB0000000" CACHE STRING "DDR4 block 2 Secure base address")
+set(DDR4_BLK3_BASE_S "0xD0000000" CACHE STRING "DDR4 block 3 Secure base address")
+
+
+###################################################################################################
+# Base addresses for peripherals - non secure #
+###################################################################################################
+set(CMSDK_GPIO0_BASE "0x41100000" CACHE STRING "User GPIO 0 Base Address (4KB)")
+set(CMSDK_GPIO1_BASE "0x41101000" CACHE STRING "User GPIO 1 Base Address (4KB)")
+set(CMSDK_GPIO2_BASE "0x41102000" CACHE STRING "User GPIO 2 Base Address (4KB)")
+set(CMSDK_GPIO3_BASE "0x41103000" CACHE STRING "User GPIO 3 Base Address (4KB)")
+
+set(AHB_USER0_BASE "0x41104000" CACHE STRING "AHB USER 0 Base Address (4KB)")
+set(AHB_USER1_BASE "0x41105000" CACHE STRING "AHB USER 1 Base Address (4KB)")
+set(AHB_USER2_BASE "0x41106000" CACHE STRING "AHB USER 2 Base Address (4KB)")
+set(AHB_USER3_BASE "0x41107000" CACHE STRING "AHB USER 3 Base Address (4KB)")
+
+set(DMA0_BASE "0x41200000" CACHE STRING "DMA0 (4KB)")
+set(DMA1_BASE "0x41201000" CACHE STRING "DMA1 (4KB)")
+set(DMA2_BASE "0x41202000" CACHE STRING "DMA2 (4KB)")
+set(DMA3_BASE "0x41203000" CACHE STRING "DMA3 (4KB)")
+
+set(SMSC9220_BASE "0x41400000" CACHE STRING "Ethernet SMSC9220 Base Address (1MB)")
+set(USB_BASE "0x41500000" CACHE STRING "USB Base Address (1MB)")
+
+set(USER_APB0_BASE "0x41700000" CACHE STRING "User APB0")
+set(USER_APB1_BASE "0x41701000" CACHE STRING "User APB1")
+set(USER_APB2_BASE "0x41702000" CACHE STRING "User APB2")
+set(USER_APB3_BASE "0x41703000" CACHE STRING "User APB3")
+
+set(QSPI_XIP_BASE "0x41800000" CACHE STRING "QSPI XIP config Base Address ")
+set(QSPI_WRITE_BASE "0x41801000" CACHE STRING "QSPI write config Base Address ")
+
+if (ETHOS_U55_ENABLED)
+ set(ETHOS_U55_BASE "0x48102000" CACHE STRING "Ethos-U55 base address")
+ set(ETHOS_U55_TA0_BASE "0x48103000" CACHE STRING "Ethos-U55's timing adapter 0 base address")
+ set(ETHOS_U55_TA1_BASE "0x48103200" CACHE STRING "Ethos-U55's timing adapter 1 base address")
+endif (ETHOS_U55_ENABLED)
+
+set(MPS3_I2C0_BASE "0x49200000" CACHE STRING "Touch Screen I2C Base Address ")
+set(MPS3_I2C1_BASE "0x49201000" CACHE STRING "Audio Interface I2C Base Address ")
+set(MPS3_SSP2_BASE "0x49202000" CACHE STRING "ADC SPI PL022 Base Address")
+set(MPS3_SSP3_BASE "0x49203000" CACHE STRING "Shield 0 SPI PL022 Base Address")
+set(MPS3_SSP4_BASE "0x49204000" CACHE STRING "Shield 1 SPI PL022 Base Address")
+set(MPS3_I2C2_BASE "0x49205000" CACHE STRING "Shield 0 SBCon Base Address ")
+set(MPS3_I2C3_BASE "0x49206000" CACHE STRING "Shield 1 SBCon Base Address ")
+
+set(USER_APB_BASE "0x49207000" CACHE STRING "User APB")
+set(MPS3_I2C5_BASE "0x49208000" CACHE STRING "DDR EPROM I2C SBCon Base Address ")
+
+set(MPS3_SCC_BASE "0x49300000" CACHE STRING "SCC Base Address ")
+set(MPS3_AAIC_I2S_BASE "0x49301000" CACHE STRING "Audio Interface I2S Base Address ")
+set(MPS3_FPGAIO_BASE "0x49302000" CACHE STRING "FPGA IO Base Address ")
+
+set(CMSDK_UART0_BASE "0x49303000" CACHE STRING "UART 0 Base Address ")
+set(CMSDK_UART1_BASE "0x49304000" CACHE STRING "UART 1 Base Address ")
+set(CMSDK_UART2_BASE "0x49305000" CACHE STRING "UART 2 Base Address ")
+set(CMSDK_UART3_BASE "0x49306000" CACHE STRING "UART 3 Base Address Shield 0")
+set(CMSDK_UART4_BASE "0x49307000" CACHE STRING "UART 4 Base Address Shield 1")
+set(CMSDK_UART5_BASE "0x49308000" CACHE STRING "UART 5 Base Address ")
+
+set(CLCD_CONFIG_BASE "0x4930A000" CACHE STRING "CLCD CONFIG Base Address ")
+set(RTC_BASE "0x4930B000" CACHE STRING "RTC Base address ")
+
+###################################################################################################
+# Base addresses for peripherals - secure #
+###################################################################################################
+set(SEC_CMSDK_GPIO0_BASE "0x51100000" CACHE STRING "User GPIO 0 Base Address (4KB)")
+set(SEC_CMSDK_GPIO1_BASE "0x51101000" CACHE STRING "User GPIO 1 Base Address (4KB)")
+set(SEC_CMSDK_GPIO2_BASE "0x51102000" CACHE STRING "User GPIO 2 Base Address (4KB)")
+set(SEC_CMSDK_GPIO3_BASE "0x51103000" CACHE STRING "User GPIO 3 Base Address (4KB)")
+
+set(SEC_AHB_USER0_BASE "0x51104000" CACHE STRING "AHB USER 0 Base Address (4KB)")
+set(SEC_AHB_USER1_BASE "0x51105000" CACHE STRING "AHB USER 1 Base Address (4KB)")
+set(SEC_AHB_USER2_BASE "0x51106000" CACHE STRING "AHB USER 2 Base Address (4KB)")
+set(SEC_AHB_USER3_BASE "0x51107000" CACHE STRING "AHB USER 3 Base Address (4KB)")
+
+set(SEC_DMA0_BASE "0x51200000" CACHE STRING "DMA0 (4KB)")
+set(SEC_DMA1_BASE "0x51201000" CACHE STRING "DMA1 (4KB)")
+set(SEC_DMA2_BASE "0x51202000" CACHE STRING "DMA2 (4KB)")
+set(SEC_DMA3_BASE "0x51203000" CACHE STRING "DMA3 (4KB)")
+
+set(SEC_SMSC9220_BASE "0x51400000" CACHE STRING "Ethernet SMSC9220 Base Address (1MB)")
+set(SEC_USB_BASE "0x51500000" CACHE STRING "USB Base Address (1MB)")
+
+set(SEC_USER_APB0_BASE "0x51700000" CACHE STRING "User APB0 Base Address")
+set(SEC_USER_APB1_BASE "0x51701000" CACHE STRING "User APB1 Base Address")
+set(SEC_USER_APB2_BASE "0x51702000" CACHE STRING "User APB2 Base Address")
+set(SEC_USER_APB3_BASE "0x51703000" CACHE STRING "User APB3 Base Address")
+
+set(SEC_QSPI_XIP_BASE "0x51800000" CACHE STRING "QSPI XIP config Base Address ")
+set(SEC_QSPI_WRITE_BASE "0x51801000" CACHE STRING "QSPI write config Base Address ")
+
+if (ETHOS_U55_ENABLED)
+ set(SEC_ETHOS_U55_BASE "0x58102000" CACHE STRING "Ethos-U55 base address")
+ set(SEC_ETHOS_U55_TA0_BASE "0x58103000" CACHE STRING "Ethos-U55's timing adapter 0 base address")
+ set(SEC_ETHOS_U55_TA1_BASE "0x58103200" CACHE STRING "Ethos-U55's timing adapter 1 base address")
+endif (ETHOS_U55_ENABLED)
+
+set(SEC_MPS3_I2C0_BASE "0x58200000" CACHE STRING "Touch Screen I2C Base Address ")
+set(SEC_MPS3_I2C1_BASE "0x58201000" CACHE STRING "Audio Interface I2C Base Address ")
+set(SEC_MPS3_SSP2_BASE "0x58202000" CACHE STRING "ADC SPI PL022 Base Address")
+set(SEC_MPS3_SSP3_BASE "0x58203000" CACHE STRING "Shield 0 SPI PL022 Base Address")
+set(SEC_MPS3_SSP4_BASE "0x58204000" CACHE STRING "Shield 1 SPI PL022 Base Address")
+set(SEC_MPS3_I2C2_BASE "0x58205000" CACHE STRING "Shield 0 SBCon Base Address ")
+set(SEC_MPS3_I2C3_BASE "0x58206000" CACHE STRING "Shield 1 SBCon Base Address ")
+
+set(SEC_USER_APB_BASE "0x58207000" CACHE STRING "User APB Base Address")
+set(SEC_MPS3_I2C5_BASE "0x58208000" CACHE STRING "DDR EPROM I2C SBCon Base Address ")
+
+set(SEC_MPS3_SCC_BASE "0x58300000" CACHE STRING "SCC Base Address ")
+set(SEC_MPS3_AAIC_I2S_BASE "0x58301000" CACHE STRING "Audio Interface I2S Base Address ")
+set(SEC_MPS3_FPGAIO_BASE "0x58302000" CACHE STRING "FPGA IO Base Address ")
+
+set(SEC_CMSDK_UART0_BASE "0x58303000" CACHE STRING "UART 0 Base Address ")
+set(SEC_CMSDK_UART1_BASE "0x58304000" CACHE STRING "UART 1 Base Address ")
+set(SEC_CMSDK_UART2_BASE "0x58305000" CACHE STRING "UART 2 Base Address ")
+set(SEC_CMSDK_UART3_BASE "0x58306000" CACHE STRING "UART 3 Base Address Shield 0")
+set(SEC_CMSDK_UART4_BASE "0x58307000" CACHE STRING "UART 4 Base Address Shield 1")
+set(SEC_CMSDK_UART5_BASE "0x58308000" CACHE STRING "UART 5 Base Address ")
+
+set(SEC_CLCD_CONFIG_BASE "0x5830A000" CACHE STRING "CLCD CONFIG Base Address ")
+set(SEC_RTC_BASE "0x5830B000" CACHE STRING "RTC Base address ")
+
+
+###################################################################################################
+# MPCs #
+###################################################################################################
+set(MPC_ISRAM0_BASE_S "0x50083000" CACHE STRING "ISRAM0 Memory Protection Controller Secure base address")
+set(MPC_ISRAM1_BASE_S "0x50084000" CACHE STRING "ISRAM1 Memory Protection Controller Secure base address")
+set(MPC_BRAM_BASE_S "0x57000000" CACHE STRING "SRAM Memory Protection Controller Secure base address")
+set(MPC_QSPI_BASE_S "0x57001000" CACHE STRING "QSPI Memory Protection Controller Secure base address")
+set(MPC_DDR4_BASE_S "0x57002000" CACHE STRING "DDR4 Memory Protection Controller Secure base address")
+
+###################################################################################################
+# IRQ numbers #
+###################################################################################################
+set(NONSEC_WATCHDOG_RESET_IRQn " 0" CACHE STRING " Non-Secure Watchdog Reset Interrupt")
+set(NONSEC_WATCHDOG_IRQn " 1" CACHE STRING " Non-Secure Watchdog Interrupt ")
+set(S32K_TIMER_IRQn " 2" CACHE STRING " S32K Timer Interrupt ")
+set(TIMER0_IRQn " 3" CACHE STRING " TIMER 0 Interrupt ")
+set(TIMER1_IRQn " 4" CACHE STRING " TIMER 1 Interrupt ")
+set(DUALTIMER_IRQn " 5" CACHE STRING " Dual Timer Interrupt ")
+set(MPC_IRQn " 9" CACHE STRING " MPC Combined (Secure) Interrupt ")
+set(PPC_IRQn "10" CACHE STRING " PPC Combined (Secure) Interrupt ")
+set(MSC_IRQn "11" CACHE STRING " MSC Combined (Secure) Interrput ")
+set(BRIDGE_ERROR_IRQn "12" CACHE STRING " Bridge Error Combined (Secure) Interrupt ")
+set(MGMT_PPU_IRQn "14" CACHE STRING " MGMT_PPU" )
+set(SYS_PPU_IRQn "15" CACHE STRING " SYS_PPU" )
+set(CPU0_PPU_IRQn "16" CACHE STRING " CPU0_PPU" )
+set(DEBUG_PPU_IRQn "26" CACHE STRING " DEBUG_PPU" )
+set(TIMER3_AON_IRQn "27" CACHE STRING " TIMER3_AON" )
+set(CPU0CTIIQ0_IRQn "28" CACHE STRING " CPU0CTIIQ0" )
+set(CPU0CTIIQ01_IRQn "29" CACHE STRING " CPU0CTIIQ01" )
+
+set(SYS_TSTAMP_COUNTER_IRQn "32" CACHE STRING " System timestamp counter interrupt" )
+set(UARTRX0_IRQn "33" CACHE STRING " UART 0 RX Interrupt ")
+set(UARTTX0_IRQn "34" CACHE STRING " UART 0 TX Interrupt ")
+set(UARTRX1_IRQn "35" CACHE STRING " UART 1 RX Interrupt ")
+set(UARTTX1_IRQn "36" CACHE STRING " UART 1 TX Interrupt ")
+set(UARTRX2_IRQn "37" CACHE STRING " UART 2 RX Interrupt ")
+set(UARTTX2_IRQn "38" CACHE STRING " UART 2 TX Interrupt ")
+set(UARTRX3_IRQn "39" CACHE STRING " UART 3 RX Interrupt ")
+set(UARTTX3_IRQn "40" CACHE STRING " UART 3 TX Interrupt ")
+set(UARTRX4_IRQn "41" CACHE STRING " UART 4 RX Interrupt ")
+set(UARTTX4_IRQn "42" CACHE STRING " UART 4 TX Interrupt ")
+set(UART0_IRQn "43" CACHE STRING " UART 0 combined Interrupt ")
+set(UART1_IRQn "44" CACHE STRING " UART 1 combined Interrupt ")
+set(UART2_IRQn "45" CACHE STRING " UART 2 combined Interrupt ")
+set(UART3_IRQn "46" CACHE STRING " UART 3 combined Interrupt ")
+set(UART4_IRQn "47" CACHE STRING " UART 4 combined Interrupt ")
+set(UARTOVF_IRQn "48" CACHE STRING " UART 0,1,2,3,4 Overflow Interrupt ")
+set(ETHERNET_IRQn "49" CACHE STRING " Ethernet Interrupt ")
+set(I2S_IRQn "50" CACHE STRING " Audio I2S Interrupt ")
+set(TSC_IRQn "51" CACHE STRING " Touch Screen Interrupt ")
+set(USB_IRQn "52" CACHE STRING " USB Interrupt ")
+set(SPI2_IRQn "53" CACHE STRING " ADC (SPI) Interrupt ")
+set(SPI3_IRQn "54" CACHE STRING " SPI 3 Interrupt (Shield 0) ")
+set(SPI4_IRQn "55" CACHE STRING " SPI 4 Interrupt (Sheild 1) ")
+
+if (ETHOS_U55_ENABLED)
+set(EthosU_IRQn "56" CACHE STRING " Ethos-U55 Interrupt ")
+endif ()
+
+set(GPIO0_IRQn "69" CACHE STRING " GPIO 0 Combined Interrupt ")
+set(GPIO1_IRQn "70" CACHE STRING " GPIO 1 Combined Interrupt ")
+set(GPIO2_IRQn "71" CACHE STRING " GPIO 2 Combined Interrupt ")
+set(GPIO3_IRQn "72" CACHE STRING " GPIO 3 Combined Interrupt ")
+
+set(GPIO0_0_IRQn "73" CACHE STRING "")
+set(GPIO0_1_IRQn "74" CACHE STRING "")
+set(GPIO0_2_IRQn "75" CACHE STRING "")
+set(GPIO0_3_IRQn "76" CACHE STRING "")
+set(GPIO0_4_IRQn "77" CACHE STRING "")
+set(GPIO0_5_IRQn "78" CACHE STRING "")
+set(GPIO0_6_IRQn "79" CACHE STRING "")
+set(GPIO0_7_IRQn "80" CACHE STRING "")
+set(GPIO0_8_IRQn "81" CACHE STRING "")
+set(GPIO0_9_IRQn "82" CACHE STRING "")
+set(GPIO0_10_IRQn "83" CACHE STRING "")
+set(GPIO0_11_IRQn "84" CACHE STRING "")
+set(GPIO0_12_IRQn "85" CACHE STRING "")
+set(GPIO0_13_IRQn "86" CACHE STRING "")
+set(GPIO0_14_IRQn "87" CACHE STRING "")
+set(GPIO0_15_IRQn "88" CACHE STRING "")
+set(GPIO1_0_IRQn "89" CACHE STRING "")
+set(GPIO1_1_IRQn "90" CACHE STRING "")
+set(GPIO1_2_IRQn "91" CACHE STRING "")
+set(GPIO1_3_IRQn "92" CACHE STRING "")
+set(GPIO1_4_IRQn "93" CACHE STRING "")
+set(GPIO1_5_IRQn "94" CACHE STRING "")
+set(GPIO1_6_IRQn "95" CACHE STRING "")
+set(GPIO1_7_IRQn "96" CACHE STRING "")
+set(GPIO1_8_IRQn "97" CACHE STRING "")
+set(GPIO1_9_IRQn "98" CACHE STRING "")
+set(GPIO1_10_IRQn "99" CACHE STRING "")
+set(GPIO1_11_IRQn "100" CACHE STRING "")
+set(GPIO1_12_IRQn "101" CACHE STRING "")
+set(GPIO1_13_IRQn "102" CACHE STRING "")
+set(GPIO1_14_IRQn "103" CACHE STRING "")
+set(GPIO1_15_IRQn "104" CACHE STRING "")
+set(GPIO2_0_IRQn "105" CACHE STRING "")
+set(GPIO2_1_IRQn "106" CACHE STRING "")
+set(GPIO2_2_IRQn "107" CACHE STRING "")
+set(GPIO2_3_IRQn "108" CACHE STRING "")
+set(GPIO2_4_IRQn "109" CACHE STRING "")
+set(GPIO2_5_IRQn "110" CACHE STRING "")
+set(GPIO2_6_IRQn "111" CACHE STRING "")
+set(GPIO2_7_IRQn "112" CACHE STRING "")
+set(GPIO2_8_IRQn "113" CACHE STRING "")
+set(GPIO2_9_IRQn "114" CACHE STRING "")
+set(GPIO2_10_IRQn "115" CACHE STRING "")
+set(GPIO2_11_IRQn "116" CACHE STRING "")
+set(GPIO2_12_IRQn "117" CACHE STRING "")
+set(GPIO2_13_IRQn "118" CACHE STRING "")
+set(GPIO2_14_IRQn "119" CACHE STRING "")
+set(GPIO2_15_IRQn "120" CACHE STRING "")
+set(GPIO3_0_IRQn "121" CACHE STRING "")
+set(GPIO3_1_IRQn "122" CACHE STRING "")
+set(GPIO3_2_IRQn "123" CACHE STRING "")
+set(GPIO3_3_IRQn "124" CACHE STRING "")
+set(UARTRX5_IRQn "125" CACHE STRING "UART 5 RX Interrupt")
+set(UARTTX5_IRQn "126" CACHE STRING "UART 5 TX Interrupt")
+set(UART5_IRQn "127" CACHE STRING "UART 5 combined Interrupt")
diff --git a/scripts/cmake/subsystem-profiles/simple_platform.cmake b/scripts/cmake/subsystem-profiles/simple_platform.cmake
new file mode 100644
index 0000000..c11706d
--- /dev/null
+++ b/scripts/cmake/subsystem-profiles/simple_platform.cmake
@@ -0,0 +1,51 @@
+#----------------------------------------------------------------------------
+# Copyright (c) 2021 Arm Limited. All rights reserved.
+# SPDX-License-Identifier: Apache-2.0
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#----------------------------------------------------------------------------
+
+# CMake configuration file for peripheral memory map for simple platform. This is a stripped down
+# version of Arm Corstone-300 platform with minimal peripherals to be able to use Ethos-U55. However,
+# for ease of integration with Arm FastModel Tools, it uses PL011 as the UART component instead of
+# the CMSDK UART block used by the MPS3 FPGA and FVP implementations.
+
+###################################################################################################
+# Application specific config #
+###################################################################################################
+
+# This parameter is based on the linker/scatter script for internal FVP. Do not change this
+# parameter in isolation.
+set(ACTIVATION_BUF_SRAM_SZ "0x00200000" CACHE STRING "Maximum SRAM size for activation buffers")
+set(DESIGN_NAME "Simple platform" CACHE STRING "Design name")
+
+###################################################################################################
+# Base addresses #
+###################################################################################################
+set(PL011_UART0_BASE "0x49303000" CACHE STRING "PL011 UART 0 Base Address")
+
+if (ETHOS_U55_ENABLED)
+ set(ETHOS_U55_BASE "0x48102000" CACHE STRING "Ethos-U55 base address")
+ set(ETHOS_U55_TA0_BASE "0x48103000" CACHE STRING "Ethos-U55's timing adapter 0 base address")
+ set(ETHOS_U55_TA1_BASE "0x48103200" CACHE STRING "Ethos-U55's timing adapter 1 base address")
+ set(SEC_ETHOS_U55_BASE "0x58102000" CACHE STRING "Ethos-U55 base address")
+ set(SEC_ETHOS_U55_TA0_BASE "0x58103000" CACHE STRING "Ethos-U55's timing adapter 0 base address")
+ set(SEC_ETHOS_U55_TA1_BASE "0x58103200" CACHE STRING "Ethos-U55's timing adapter 1 base address")
+endif ()
+
+###################################################################################################
+# IRQ numbers #
+###################################################################################################
+if (ETHOS_U55_ENABLED)
+ set(EthosU_IRQn "56" CACHE STRING "Ethos-U55 Interrupt")
+endif ()
diff --git a/scripts/cmake/ta_config.cmake b/scripts/cmake/ta_config.cmake
new file mode 100644
index 0000000..427884c
--- /dev/null
+++ b/scripts/cmake/ta_config.cmake
@@ -0,0 +1,64 @@
+#----------------------------------------------------------------------------
+# Copyright (c) 2021 Arm Limited. All rights reserved.
+# SPDX-License-Identifier: Apache-2.0
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#----------------------------------------------------------------------------
+
+#----------------------------------------------------------------------------
+# CMake description file for the Ethos-U55 Timing Adapter settings (single
+# NPU core with two AXIs).
+#----------------------------------------------------------------------------
+
+set(TA0_BASE "${SEC_ETHOS_U55_TA0_BASE}" CACHE STRING "Timing adapter 0: base-address")
+set(TA1_BASE "${SEC_ETHOS_U55_TA1_BASE}" CACHE STRING "Timing adapter 1: base-address")
+
+message(STATUS "using TA0_BASE @ ${TA0_BASE}; TA1_BASE @ ${TA1_BASE}.")
+
+# Timing adapter settings for AXI0
+set(TA0_MAXR "8" CACHE STRING "6-bit field. Max no. of pending reads. 0=infinite")
+set(TA0_MAXW "8" CACHE STRING "6-bit field. Max no. of pending writes. 0=infinite")
+set(TA0_MAXRW "0" CACHE STRING "6-bit field. Max no. of pending reads+writes. 0=infinite")
+set(TA0_RLATENCY "32" CACHE STRING "12-bit field. Minimum latency (clock cycles) from AVALID to RVALID.")
+set(TA0_WLATENCY "32" CACHE STRING "12-bit field. Minimum latency (clock cycles) from WVALID&WLAST to BVALID.")
+set(TA0_PULSE_ON "3999" CACHE STRING "No. of cycles addresses let through (0-65535).")
+set(TA0_PULSE_OFF "1" CACHE STRING "No. of cycles addresses blocked (0-65535).")
+set(TA0_BWCAP "4000" CACHE STRING "16-bit field. Max no. of 64-bit words transfered per pulse cycle 0=infinite")
+set(TA0_PERFCTRL "0" CACHE STRING "6-bit field selecting an event for event counter 0=default")
+set(TA0_PERFCNT "0" CACHE STRING "32-bit event counter")
+set(TA0_MODE "1" CACHE STRING "Bit 0: 1=enable dynamic clocking to avoid underrun;
+ Bit 1: 1=enable random AR reordering (0=default);
+ Bit 2: 1=enable random R reordering (0=default);
+ Bit 3: 1=enable random B reordering (0=default);
+ Bit 11-4: Frequency scale 0=full speed, 255=(1/256) speed")
+set(TA0_HISTBIN "0" CACHE STRING "Controls which histogram bin (0-15) that should be accessed by HISTCNT.")
+set(TA0_HISTCNT "0" CACHE STRING "32-bit field. Read/write the selected histogram bin.")
+
+# Timing adapter settings for AXI1
+set(TA1_MAXR "2" CACHE STRING "6-bit field. Max no. of pending reads. 0=infinite")
+set(TA1_MAXW "0" CACHE STRING "6-bit field. Max no. of pending writes. 0=infinite")
+set(TA1_MAXRW "0" CACHE STRING "6-bit field. Max no. of pending reads+writes. 0=infinite")
+set(TA1_RLATENCY "64" CACHE STRING "12-bit field. Minimum latency (clock cycles) from AVALID to RVALID.")
+set(TA1_WLATENCY "0" CACHE STRING "12-bit field. Minimum latency (clock cycles) from WVALID&WLAST to BVALID.")
+set(TA1_PULSE_ON "320" CACHE STRING "No. of cycles addresses let through (0-65535).")
+set(TA1_PULSE_OFF "80" CACHE STRING "No. of cycles addresses blocked (0-65535).")
+set(TA1_BWCAP "50" CACHE STRING "16-bit field. Max no. of 64-bit words transfered per pulse cycle 0=infinite")
+set(TA1_PERFCTRL "0" CACHE STRING "6-bit field selecting an event for event counter 0=default")
+set(TA1_PERFCNT "0" CACHE STRING "32-bit event counter")
+set(TA1_MODE "1" CACHE STRING "Bit 0: 1=enable dynamic clocking to avoid underrun;
+ Bit 1: 1=enable random AR reordering (0=default);
+ Bit 2: 1=enable random R reordering (0=default);
+ Bit 3: 1=enable random B reordering (0=default);
+ Bit 11-4: Frequency scale 0=full speed, 255=(1/256) speed")
+set(TA1_HISTBIN "0" CACHE STRING "Controls which histogram bin (0-15) that should be accessed by HISTCNT.")
+set(TA1_HISTCNT "0" CACHE STRING "32-bit field. Read/write the selected histogram bin.")
diff --git a/scripts/cmake/templates/mem_regions.h.template b/scripts/cmake/templates/mem_regions.h.template
new file mode 100644
index 0000000..72978ce
--- /dev/null
+++ b/scripts/cmake/templates/mem_regions.h.template
@@ -0,0 +1,58 @@
+/*
+ * Copyright (c) 2021 Arm Limited. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+// Auto-generated file
+// ** DO NOT EDIT **
+
+#ifndef MEM_REGION_DEFS_H
+#define MEM_REGION_DEFS_H
+
+#cmakedefine ITCM_SIZE (@ITCM_SIZE@) /* ITCM size */
+#cmakedefine DTCM_BLK_SIZE (@DTCM_BLK_SIZE@) /* DTCM size, 4 banks of this size available */
+#cmakedefine BRAM_SIZE (@BRAM_SIZE@) /* BRAM size */
+#cmakedefine ISRAM0_SIZE (@ISRAM0_SIZE@) /* ISRAM0 size */
+#cmakedefine ISRAM1_SIZE (@ISRAM1_SIZE@) /* ISRAM1 size */
+#cmakedefine QSPI_SRAM_SIZE (@QSPI_SRAM_SIZE@) /* QSPI Flash size */
+#cmakedefine DDR4_BLK_SIZE (@DDR4_BLK_SIZE@) /* DDR4 block size */
+
+#cmakedefine ITCM_BASE_NS (@ITCM_BASE_NS@) /* Instruction TCM Non-Secure base address */
+#cmakedefine BRAM_BASE_NS (@BRAM_BASE_NS@) /* CODE SRAM Non-Secure base address */
+#cmakedefine DTCM0_BASE_NS (@DTCM0_BASE_NS@) /* Data TCM block 0 Non-Secure base address */
+#cmakedefine DTCM1_BASE_NS (@DTCM1_BASE_NS@) /* Data TCM block 1 Non-Secure base address */
+#cmakedefine DTCM2_BASE_NS (@DTCM2_BASE_NS@) /* Data TCM block 2 Non-Secure base address */
+#cmakedefine DTCM3_BASE_NS (@DTCM3_BASE_NS@) /* Data TCM block 3 Non-Secure base address */
+#cmakedefine ISRAM0_BASE_NS (@ISRAM0_BASE_NS@) /* Internal SRAM Area Non-Secure base address */
+#cmakedefine ISRAM1_BASE_NS (@ISRAM1_BASE_NS@) /* Internal SRAM Area Non-Secure base address */
+#cmakedefine QSPI_SRAM_BASE_NS (@QSPI_SRAM_BASE_NS@) /* QSPI SRAM Non-Secure base address */
+#cmakedefine DDR4_BLK0_BASE_NS (@DDR4_BLK0_BASE_NS@) /* DDR4 block 0 Non-Secure base address */
+#cmakedefine DDR4_BLK1_BASE_NS (@DDR4_BLK1_BASE_NS@) /* DDR4 block 1 Non-Secure base address */
+#cmakedefine DDR4_BLK2_BASE_NS (@DDR4_BLK2_BASE_NS@) /* DDR4 block 2 Non-Secure base address */
+#cmakedefine DDR4_BLK3_BASE_NS (@DDR4_BLK3_BASE_NS@) /* DDR4 block 3 Non-Secure base address */
+
+#cmakedefine ITCM_BASE_S (@ITCM_BASE_S@) /* Instruction TCM Secure base address */
+#cmakedefine BRAM_BASE_S (@BRAM_BASE_S@) /* CODE SRAM Secure base address */
+#cmakedefine DTCM0_BASE_S (@DTCM0_BASE_S@) /* Data TCM block 0 Secure base address */
+#cmakedefine DTCM1_BASE_S (@DTCM1_BASE_S@) /* Data TCM block 1 Secure base address */
+#cmakedefine DTCM2_BASE_S (@DTCM2_BASE_S@) /* Data TCM block 2 Secure base address */
+#cmakedefine DTCM3_BASE_S (@DTCM3_BASE_S@) /* Data TCM block 3 Secure base address */
+#cmakedefine ISRAM0_BASE_S (@ISRAM0_BASE_S@) /* Internal SRAM Area Secure base address */
+#cmakedefine ISRAM1_BASE_S (@ISRAM1_BASE_S@) /* Internal SRAM Area Secure base address */
+#cmakedefine DDR4_BLK0_BASE_S (@DDR4_BLK0_BASE_S@) /* DDR4 block 0 Secure base address */
+#cmakedefine DDR4_BLK1_BASE_S (@DDR4_BLK1_BASE_S@) /* DDR4 block 1 Secure base address */
+#cmakedefine DDR4_BLK2_BASE_S (@DDR4_BLK2_BASE_S@) /* DDR4 block 2 Secure base address */
+#cmakedefine DDR4_BLK3_BASE_S (@DDR4_BLK3_BASE_S@) /* DDR4 block 3 Secure base address */
+
+#endif /* MEM_REGION_DEFS_H */
diff --git a/scripts/cmake/templates/peripheral_irqs.h.template b/scripts/cmake/templates/peripheral_irqs.h.template
new file mode 100644
index 0000000..8e8888b
--- /dev/null
+++ b/scripts/cmake/templates/peripheral_irqs.h.template
@@ -0,0 +1,138 @@
+/*
+ * Copyright (c) 2021 Arm Limited. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+// Auto-generated file
+// ** DO NOT EDIT **
+
+#ifndef PERIPHERAL_IRQS_H
+#define PERIPHERAL_IRQS_H
+
+/******************************************************************************/
+/* Peripheral interrupt numbers */
+/******************************************************************************/
+
+/* ------------------- Cortex-M Processor Exceptions Numbers -------------- */
+/* -14 to -1 should be defined by the system header */
+/* ---------------------- Core Specific Interrupt Numbers ------------------*/
+#cmakedefine NONSEC_WATCHDOG_RESET_IRQn (@NONSEC_WATCHDOG_RESET_IRQn@) /* Non-Secure Watchdog Reset Interrupt */
+#cmakedefine NONSEC_WATCHDOG_IRQn (@NONSEC_WATCHDOG_IRQn@) /* Non-Secure Watchdog Interrupt */
+#cmakedefine S32K_TIMER_IRQn (@S32K_TIMER_IRQn@) /* S32K Timer Interrupt */
+#cmakedefine TIMER0_IRQn (@TIMER0_IRQn@) /* TIMER 0 Interrupt */
+#cmakedefine TIMER1_IRQn (@TIMER1_IRQn@) /* TIMER 1 Interrupt */
+#cmakedefine DUALTIMER_IRQn (@DUALTIMER_IRQn@) /* Dual Timer Interrupt */
+#cmakedefine MPC_IRQn (@MPC_IRQn@) /* MPC Combined (@Secure@) Interrupt */
+#cmakedefine PPC_IRQn (@PPC_IRQn@) /* PPC Combined (@Secure@) Interrupt */
+#cmakedefine MSC_IRQn (@MSC_IRQn@) /* MSC Combined (@Secure@) Interrput */
+#cmakedefine BRIDGE_ERROR_IRQn (@BRIDGE_ERROR_IRQn@) /* Bridge Error Combined (@Secure@) Interrupt */
+#cmakedefine MGMT_PPU_IRQn (@MGMT_PPU_IRQn@) /* MGMT_PPU */
+#cmakedefine SYS_PPU_IRQn (@SYS_PPU_IRQn@) /* SYS_PPU */
+#cmakedefine CPU0_PPU_IRQn (@CPU0_PPU_IRQn@) /* CPU0_PPU */
+#cmakedefine DEBUG_PPU_IRQn (@DEBUG_PPU_IRQn@) /* DEBUG_PPU */
+#cmakedefine TIMER3_AON_IRQn (@TIMER3_AON_IRQn@) /* TIMER3_AON */
+#cmakedefine CPU0CTIIQ0_IRQn (@CPU0CTIIQ0_IRQn@) /* CPU0CTIIQ0 */
+#cmakedefine CPU0CTIIQ01_IRQn (@CPU0CTIIQ01_IRQn@) /* CPU0CTIIQ01 */
+
+#cmakedefine SYS_TSTAMP_COUNTER_IRQn (@SYS_TSTAMP_COUNTER_IRQn@) /* System timestamp counter interrupt */
+
+/* ---------------------- CMSDK Specific Interrupt Numbers ----------------- */
+#cmakedefine UARTRX0_IRQn (@UARTRX0_IRQn@) /* UART 0 RX Interrupt */
+#cmakedefine UARTTX0_IRQn (@UARTTX0_IRQn@) /* UART 0 TX Interrupt */
+#cmakedefine UARTRX1_IRQn (@UARTRX1_IRQn@) /* UART 1 RX Interrupt */
+#cmakedefine UARTTX1_IRQn (@UARTTX1_IRQn@) /* UART 1 TX Interrupt */
+#cmakedefine UARTRX2_IRQn (@UARTRX2_IRQn@) /* UART 2 RX Interrupt */
+#cmakedefine UARTTX2_IRQn (@UARTTX2_IRQn@) /* UART 2 TX Interrupt */
+#cmakedefine UARTRX3_IRQn (@UARTRX3_IRQn@) /* UART 3 RX Interrupt */
+#cmakedefine UARTTX3_IRQn (@UARTTX3_IRQn@) /* UART 3 TX Interrupt */
+#cmakedefine UARTRX4_IRQn (@UARTRX4_IRQn@) /* UART 4 RX Interrupt */
+#cmakedefine UARTTX4_IRQn (@UARTTX4_IRQn@) /* UART 4 TX Interrupt */
+#cmakedefine UART0_IRQn (@UART0_IRQn@) /* UART 0 combined Interrupt */
+#cmakedefine UART1_IRQn (@UART1_IRQn@) /* UART 1 combined Interrupt */
+#cmakedefine UART2_IRQn (@UART2_IRQn@) /* UART 2 combined Interrupt */
+#cmakedefine UART3_IRQn (@UART3_IRQn@) /* UART 3 combined Interrupt */
+#cmakedefine UART4_IRQn (@UART4_IRQn@) /* UART 4 combined Interrupt */
+#cmakedefine UARTOVF_IRQn (@UARTOVF_IRQn@) /* UART 0,1,2,3 and 4 Overflow Interrupt */
+#cmakedefine ETHERNET_IRQn (@ETHERNET_IRQn@) /* Ethernet Interrupt */
+#cmakedefine I2S_IRQn (@I2S_IRQn@) /* I2S Interrupt */
+#cmakedefine TSC_IRQn (@TSC_IRQn@) /* Touch Screen Interrupt */
+#cmakedefine SPI2_IRQn (@SPI2_IRQn@) /* SPI 2 Interrupt */
+#cmakedefine SPI3_IRQn (@SPI3_IRQn@) /* SPI 3 Interrupt */
+#cmakedefine SPI4_IRQn (@SPI4_IRQn@) /* SPI 4 Interrupt */
+
+#cmakedefine EthosU_IRQn (@EthosU_IRQn@) /* Ethos-Uxx Interrupt */
+
+#cmakedefine GPIO0_IRQn (@GPIO0_IRQn@) /* GPIO 0 Combined Interrupt */
+#cmakedefine GPIO1_IRQn (@GPIO1_IRQn@) /* GPIO 1 Combined Interrupt */
+#cmakedefine GPIO2_IRQn (@GPIO2_IRQn@) /* GPIO 2 Combined Interrupt */
+#cmakedefine GPIO3_IRQn (@GPIO3_IRQn@) /* GPIO 3 Combined Interrupt */
+
+#cmakedefine GPIO0_0_IRQn (@GPIO0_0_IRQn@) /* All P0 I/O pins used as irq source */
+#cmakedefine GPIO0_1_IRQn (@GPIO0_1_IRQn@) /* There are 16 pins in total */
+#cmakedefine GPIO0_2_IRQn (@GPIO0_2_IRQn@)
+#cmakedefine GPIO0_3_IRQn (@GPIO0_3_IRQn@)
+#cmakedefine GPIO0_4_IRQn (@GPIO0_4_IRQn@)
+#cmakedefine GPIO0_5_IRQn (@GPIO0_5_IRQn@)
+#cmakedefine GPIO0_6_IRQn (@GPIO0_6_IRQn@)
+#cmakedefine GPIO0_7_IRQn (@GPIO0_7_IRQn@)
+#cmakedefine GPIO0_8_IRQn (@GPIO0_8_IRQn@)
+#cmakedefine GPIO0_9_IRQn (@GPIO0_9_IRQn@)
+#cmakedefine GPIO0_10_IRQn (@GPIO0_10_IRQn@)
+#cmakedefine GPIO0_11_IRQn (@GPIO0_11_IRQn@)
+#cmakedefine GPIO0_12_IRQn (@GPIO0_12_IRQn@)
+#cmakedefine GPIO0_13_IRQn (@GPIO0_13_IRQn@)
+#cmakedefine GPIO0_14_IRQn (@GPIO0_14_IRQn@)
+#cmakedefine GPIO0_15_IRQn (@GPIO0_15_IRQn@)
+#cmakedefine GPIO1_0_IRQn (@GPIO1_0_IRQn@) /* All P1 I/O pins used as irq source */
+#cmakedefine GPIO1_1_IRQn (@GPIO1_1_IRQn@) /* There are 16 pins in total */
+#cmakedefine GPIO1_2_IRQn (@GPIO1_2_IRQn@)
+#cmakedefine GPIO1_3_IRQn (@GPIO1_3_IRQn@)
+#cmakedefine GPIO1_4_IRQn (@GPIO1_4_IRQn@)
+#cmakedefine GPIO1_5_IRQn (@GPIO1_5_IRQn@)
+#cmakedefine GPIO1_6_IRQn (@GPIO1_6_IRQn@)
+#cmakedefine GPIO1_7_IRQn (@GPIO1_7_IRQn@)
+#cmakedefine GPIO1_8_IRQn (@GPIO1_8_IRQn@)
+#cmakedefine GPIO1_9_IRQn (@GPIO1_9_IRQn@)
+#cmakedefine GPIO1_10_IRQn (@GPIO1_10_IRQn@)
+#cmakedefine GPIO1_11_IRQn (@GPIO1_11_IRQn@)
+#cmakedefine GPIO1_12_IRQn (@GPIO1_12_IRQn@)
+#cmakedefine GPIO1_13_IRQn (@GPIO1_13_IRQn@)
+#cmakedefine GPIO1_14_IRQn (@GPIO1_14_IRQn@)
+#cmakedefine GPIO1_15_IRQn (@GPIO1_15_IRQn@)
+#cmakedefine GPIO2_0_IRQn (@GPIO2_0_IRQn@) /* All P2 I/O pins used as irq source */
+#cmakedefine GPIO2_1_IRQn (@GPIO2_1_IRQn@) /* There are 15 pins in total */
+#cmakedefine GPIO2_2_IRQn (@GPIO2_2_IRQn@)
+#cmakedefine GPIO2_3_IRQn (@GPIO2_3_IRQn@)
+#cmakedefine GPIO2_4_IRQn (@GPIO2_4_IRQn@)
+#cmakedefine GPIO2_5_IRQn (@GPIO2_5_IRQn@)
+#cmakedefine GPIO2_6_IRQn (@GPIO2_6_IRQn@)
+#cmakedefine GPIO2_7_IRQn (@GPIO2_7_IRQn@)
+#cmakedefine GPIO2_8_IRQn (@GPIO2_8_IRQn@)
+#cmakedefine GPIO2_9_IRQn (@GPIO2_9_IRQn@)
+#cmakedefine GPIO2_10_IRQn (@GPIO2_10_IRQn@)
+#cmakedefine GPIO2_11_IRQn (@GPIO2_11_IRQn@)
+#cmakedefine GPIO2_12_IRQn (@GPIO2_12_IRQn@)
+#cmakedefine GPIO2_13_IRQn (@GPIO2_13_IRQn@)
+#cmakedefine GPIO2_14_IRQn (@GPIO2_14_IRQn@)
+#cmakedefine GPIO2_15_IRQn (@GPIO2_15_IRQn@)
+#cmakedefine GPIO3_0_IRQn (@GPIO3_0_IRQn@) /* All P3 I/O pins used as irq source */
+#cmakedefine GPIO3_1_IRQn (@GPIO3_1_IRQn@) /* There are 4 pins in total */
+#cmakedefine GPIO3_2_IRQn (@GPIO3_2_IRQn@)
+#cmakedefine GPIO3_3_IRQn (@GPIO3_3_IRQn@)
+#cmakedefine UARTRX5_IRQn (@UARTRX5_IRQn@) /* UART 5 RX Interrupt */
+#cmakedefine UARTTX5_IRQn (@UARTTX5_IRQn@) /* UART 5 TX Interrupt */
+#cmakedefine UART5_IRQn (@UART5_IRQn@) /* UART 5 combined Interrupt */
+#cmakedefine HDCLCD_IRQn (@HDCLCD_IRQn@) /* HDCLCD Interrupt */
+
+#endif /* PERIPHERAL_IRQS_H */
diff --git a/scripts/cmake/templates/peripheral_memmap.h.template b/scripts/cmake/templates/peripheral_memmap.h.template
new file mode 100644
index 0000000..050d7d7
--- /dev/null
+++ b/scripts/cmake/templates/peripheral_memmap.h.template
@@ -0,0 +1,162 @@
+/*
+ * Copyright (c) 2021 Arm Limited. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+// Auto-generated file
+// ** DO NOT EDIT **
+
+#ifndef PERIPHERAL_MEMMAP_H
+#define PERIPHERAL_MEMMAP_H
+
+#cmakedefine DESIGN_NAME "@DESIGN_NAME@"
+
+/******************************************************************************/
+/* Peripheral memory map */
+/******************************************************************************/
+
+#cmakedefine CMSDK_GPIO0_BASE (@CMSDK_GPIO0_BASE@) /* User GPIO 0 Base Address */
+#cmakedefine CMSDK_GPIO1_BASE (@CMSDK_GPIO1_BASE@) /* User GPIO 1 Base Address */
+#cmakedefine CMSDK_GPIO2_BASE (@CMSDK_GPIO2_BASE@) /* User GPIO 2 Base Address */
+#cmakedefine CMSDK_GPIO3_BASE (@CMSDK_GPIO3_BASE@) /* User GPIO 3 Base Address */
+
+#cmakedefine AHB_USER0_BASE (@AHB_USER0_BASE@) /* AHB USER 0 Base Address (4KB) */
+#cmakedefine AHB_USER1_BASE (@AHB_USER1_BASE@) /* AHB USER 1 Base Address (4KB)*/
+#cmakedefine AHB_USER2_BASE (@AHB_USER2_BASE@) /* AHB USER 2 Base Address (4KB)*/
+#cmakedefine AHB_USER3_BASE (@AHB_USER3_BASE@) /* AHB USER 3 Base Address (4KB)*/
+
+#cmakedefine DMA0_BASE (@DMA0_BASE@) /* DMA0 (4KB) */
+#cmakedefine DMA1_BASE (@DMA1_BASE@) /* DMA1 (4KB) */
+#cmakedefine DMA2_BASE (@DMA2_BASE@) /* DMA2 (4KB) */
+#cmakedefine DMA3_BASE (@DMA3_BASE@) /* DMA3 (4KB) */
+
+#cmakedefine USER_APB0_BASE (@USER_APB0_BASE@) /* User APB0 */
+#cmakedefine USER_APB1_BASE (@USER_APB1_BASE@) /* User APB1 */
+#cmakedefine USER_APB2_BASE (@USER_APB2_BASE@) /* User APB2 */
+#cmakedefine USER_APB3_BASE (@USER_APB3_BASE@) /* User APB3 */
+
+#cmakedefine MPS3_I2C0_BASE (@MPS3_I2C0_BASE@) /* Touch Screen I2C Base Address */
+#cmakedefine MPS3_I2C1_BASE (@MPS3_I2C1_BASE@) /* Audio Interface I2C Base Address */
+#cmakedefine MPS3_SSP2_BASE (@MPS3_SSP2_BASE@) /* ADC SPI PL022 Base Address */
+#cmakedefine MPS3_SSP3_BASE (@MPS3_SSP3_BASE@) /* Shield 0 SPI PL022 Base Address */
+
+#cmakedefine MPS3_SSP4_BASE (@MPS3_SSP4_BASE@) /* Shield 1 SPI PL022 Base Address */
+#cmakedefine MPS3_I2C2_BASE (@MPS3_I2C2_BASE@) /* Shield 0 SBCon Base Address */
+#cmakedefine MPS3_I2C3_BASE (@MPS3_I2C3_BASE@) /* Shield 1 SBCon Base Address */
+
+#cmakedefine USER_APB_BASE (@USER_APB_BASE@) /* User APB Base Address */
+#cmakedefine MPS3_I2C4_BASE (@MPS3_I2C4_BASE@) /* HDMI I2C SBCon Base Address */
+#cmakedefine MPS3_I2C5_BASE (@MPS3_I2C5_BASE@) /* DDR EPROM I2C SBCon Base Address */
+#cmakedefine MPS3_SCC_BASE (@MPS3_SCC_BASE@) /* SCC Base Address */
+#cmakedefine MPS3_AAIC_I2S_BASE (@MPS3_AAIC_I2S_BASE@) /* Audio Interface I2S Base Address */
+#cmakedefine MPS3_FPGAIO_BASE (@MPS3_FPGAIO_BASE@) /* FPGA IO Base Address */
+#cmakedefine PL011_UART0_BASE (@PL011_UART0_BASE@) /* PL011 UART0 Base Address */
+#cmakedefine CMSDK_UART0_BASE (@CMSDK_UART0_BASE@) /* UART 0 Base Address */
+#cmakedefine CMSDK_UART1_BASE (@CMSDK_UART1_BASE@) /* UART 1 Base Address */
+#cmakedefine CMSDK_UART2_BASE (@CMSDK_UART2_BASE@) /* UART 2 Base Address */
+#cmakedefine CMSDK_UART3_BASE (@CMSDK_UART3_BASE@) /* UART 3 Base Address Shield 0*/
+
+#cmakedefine ETHOS_U55_BASE (@ETHOS_U55_BASE@) /* Ethos-U55 base address*/
+#cmakedefine ETHOS_U55_TA0_BASE (@ETHOS_U55_TA0_BASE@) /* Ethos-U55's timing adapter 0 base address */
+#cmakedefine ETHOS_U55_TA1_BASE (@ETHOS_U55_TA1_BASE@) /* Ethos-U55's timing adapter 1 base address */
+
+#cmakedefine CMSDK_UART4_BASE (@CMSDK_UART4_BASE@) /* UART 4 Base Address Shield 1*/
+#cmakedefine CMSDK_UART5_BASE (@CMSDK_UART5_BASE@) /* UART 5 Base Address */
+#cmakedefine HDMI_AUDIO_BASE (@HDMI_AUDIO_BASE@) /* HDMI AUDIO Base Address */
+#cmakedefine CLCD_CONFIG_BASE (@CLCD_CONFIG_BASE@) /* CLCD CONFIG Base Address */
+#cmakedefine RTC_BASE (@RTC_BASE@) /* RTC Base address */
+#cmakedefine SMSC9220_BASE (@SMSC9220_BASE@) /* Ethernet SMSC9220 Base Address */
+#cmakedefine USB_BASE (@USB_BASE@) /* USB Base Address */
+#cmakedefine CMSDK_SDIO_BASE (@CMSDK_SDIO_BASE@) /* User SDIO Base Address */
+#cmakedefine MPS3_CLCD_BASE (@MPS3_CLCD_BASE@) /* HDLCD Base Address */
+#cmakedefine MPS3_eMMC_BASE (@MPS3_eMMC_BASE@) /* User eMMC Base Address */
+#cmakedefine USER_BASE (@USER_BASE@) /* User ? Base Address */
+
+#cmakedefine QSPI_XIP_BASE (@QSPI_XIP_BASE@) /* QSPI XIP config Base Address */
+#cmakedefine QSPI_WRITE_BASE (@QSPI_WRITE_BASE@) /* QSPI write config Base Address */
+
+/******************************************************************************/
+/* Secure Peripheral memory map */
+/******************************************************************************/
+
+#cmakedefine MPC_ISRAM0_BASE_S (@MPC_ISRAM0_BASE_S@) /* ISRAM0 Memory Protection Controller Secure base address */
+#cmakedefine MPC_ISRAM1_BASE_S (@MPC_ISRAM1_BASE_S@) /* ISRAM1 Memory Protection Controller Secure base address */
+
+#cmakedefine SEC_CMSDK_GPIO0_BASE (@SEC_CMSDK_GPIO0_BASE@) /* User GPIO 0 Base Address */
+#cmakedefine SEC_CMSDK_GPIO1_BASE (@SEC_CMSDK_GPIO1_BASE@) /* User GPIO 0 Base Address */
+#cmakedefine SEC_CMSDK_GPIO2_BASE (@SEC_CMSDK_GPIO2_BASE@) /* User GPIO 0 Base Address */
+#cmakedefine SEC_CMSDK_GPIO3_BASE (@SEC_CMSDK_GPIO3_BASE@) /* User GPIO 0 Base Address */
+
+#cmakedefine SEC_AHB_USER0_BASE (@SEC_AHB_USER0_BASE@) /* AHB USER 0 Base Address (4KB) */
+#cmakedefine SEC_AHB_USER1_BASE (@SEC_AHB_USER1_BASE@) /* AHB USER 1 Base Address (4KB)*/
+#cmakedefine SEC_AHB_USER2_BASE (@SEC_AHB_USER2_BASE@) /* AHB USER 2 Base Address (4KB)*/
+#cmakedefine SEC_AHB_USER3_BASE (@SEC_AHB_USER3_BASE@) /* AHB USER 3 Base Address (4KB)*/
+
+#cmakedefine SEC_DMA0_BASE (@SEC_DMA0_BASE@) /* DMA0 (4KB) */
+#cmakedefine SEC_DMA1_BASE (@SEC_DMA1_BASE@) /* DMA1 (4KB) */
+#cmakedefine SEC_DMA2_BASE (@SEC_DMA2_BASE@) /* DMA2 (4KB) */
+#cmakedefine SEC_DMA3_BASE (@SEC_DMA3_BASE@) /* DMA3 (4KB) */
+
+#cmakedefine SEC_USER_APB0_BASE (@SEC_USER_APB0_BASE@) /* User APB0 */
+#cmakedefine SEC_USER_APB1_BASE (@SEC_USER_APB1_BASE@) /* User APB1 */
+#cmakedefine SEC_USER_APB2_BASE (@SEC_USER_APB2_BASE@) /* User APB2 */
+#cmakedefine SEC_USER_APB3_BASE (@SEC_USER_APB3_BASE@) /* User APB3 */
+
+#cmakedefine SEC_MPS3_I2C0_BASE (@SEC_MPS3_I2C0_BASE@) /* Touch Screen I2C Base Address */
+#cmakedefine SEC_MPS3_I2C1_BASE (@SEC_MPS3_I2C1_BASE@) /* Audio Interface I2C Base Address */
+#cmakedefine SEC_MPS3_SSP2_BASE (@SEC_MPS3_SSP2_BASE@) /* ADC SPI PL022 Base Address */
+#cmakedefine SEC_MPS3_SSP3_BASE (@SEC_MPS3_SSP3_BASE@) /* Shield 0 SPI PL022 Base Address */
+
+#cmakedefine SEC_MPS3_SSP4_BASE (@SEC_MPS3_SSP4_BASE@) /* Shield 1 SPI PL022 Base Address */
+#cmakedefine SEC_MPS3_I2C2_BASE (@SEC_MPS3_I2C2_BASE@) /* Shield 0 SBCon Base Address */
+#cmakedefine SEC_MPS3_I2C3_BASE (@SEC_MPS3_I2C3_BASE@) /* Shield 1 SBCon Base Address */
+
+#cmakedefine SEC_MPS3_I2C4_BASE (@SEC_MPS3_I2C4_BASE@) /* HDMI I2C SBCon Base Address */
+#cmakedefine SEC_MPS3_I2C5_BASE (@SEC_MPS3_I2C5_BASE@) /* DDR EPROM I2C SBCon Base Address */
+#cmakedefine SEC_MPS3_SCC_BASE (@SEC_MPS3_SCC_BASE@) /* SCC Base Address */
+#cmakedefine SEC_MPS3_AAIC_I2S_BASE (@SEC_MPS3_AAIC_I2S_BASE@) /* Audio Interface I2S Base Address */
+#cmakedefine SEC_MPS3_FPGAIO_BASE (@SEC_MPS3_FPGAIO_BASE@) /* FPGA IO Base Address */
+#cmakedefine SEC_CMSDK_UART0_BASE (@SEC_CMSDK_UART0_BASE@) /* UART 0 Base Address */
+#cmakedefine SEC_CMSDK_UART1_BASE (@SEC_CMSDK_UART1_BASE@) /* UART 1 Base Address */
+#cmakedefine SEC_CMSDK_UART2_BASE (@SEC_CMSDK_UART2_BASE@) /* UART 2 Base Address */
+#cmakedefine SEC_CMSDK_UART3_BASE (@SEC_CMSDK_UART3_BASE@) /* UART 3 Base Address Shield 0*/
+
+#cmakedefine SEC_CMSDK_UART4_BASE (@SEC_CMSDK_UART4_BASE@) /* UART 4 Base Address Shield 1*/
+#cmakedefine SEC_CMSDK_UART5_BASE (@SEC_CMSDK_UART5_BASE@) /* UART 5 Base Address */
+#cmakedefine SEC_HDMI_AUDIO_BASE (@SEC_HDMI_AUDIO_BASE@) /* HDMI AUDIO Base Address */
+#cmakedefine SEC_CLCD_CONFIG_BASE (@SEC_CLCD_CONFIG_BASE@) /* CLCD CONFIG Base Address */
+#cmakedefine SEC_RTC_BASE (@SEC_RTC_BASE@) /* RTC Base address */
+#cmakedefine SEC_SMSC9220_BASE (@SEC_SMSC9220_BASE@) /* Ethernet SMSC9220 Base Address */
+#cmakedefine SEC_USB_BASE (@SEC_USB_BASE@) /* USB Base Address */
+
+#cmakedefine SEC_ETHOS_U55_BASE (@SEC_ETHOS_U55_BASE@) /* Ethos-U55 base address*/
+#cmakedefine SEC_ETHOS_U55_TA0_BASE (@SEC_ETHOS_U55_TA0_BASE@) /* Ethos-U55's timing adapter 0 base address */
+#cmakedefine SEC_ETHOS_U55_TA1_BASE (@SEC_ETHOS_U55_TA1_BASE@) /* Ethos-U55's timing adapter 1 base address */
+
+#cmakedefine SEC_USER_BASE (@SEC_USER_BASE@) /* User ? Base Address */
+
+#cmakedefine SEC_QSPI_XIP_BASE (@SEC_QSPI_XIP_BASE@) /* QSPI XIP config Base Address */
+#cmakedefine SEC_QSPI_WRITE_BASE (@SEC_QSPI_WRITE_BASE@) /* QSPI write config Base Address */
+
+/******************************************************************************/
+/* MPCs */
+/******************************************************************************/
+
+#cmakedefine MPC_ISRAM0_BASE_S (@MPC_ISRAM0_BASE_S@) /* Internal SRAM 0 MPC */
+#cmakedefine MPC_ISRAM1_BASE_S (@MPC_ISRAM1_BASE_S@) /* Internal SRAM 1 MPC */
+#cmakedefine MPC_BRAM_BASE_S (@MPC_BRAM_BASE_S@) /* SRAM Memory Protection Controller Secure base address */
+#cmakedefine MPC_QSPI_BASE_S (@MPC_QSPI_BASE_S@) /* QSPI Memory Protection Controller Secure base address */
+#cmakedefine MPC_DDR4_BASE_S (@MPC_DDR4_BASE_S@) /* DDR4 Memory Protection Controller Secure base address */
+
+#endif /* PERIPHERAL_MEMMAP_H */
diff --git a/scripts/cmake/templates/timing_adapter_settings.template b/scripts/cmake/templates/timing_adapter_settings.template
new file mode 100644
index 0000000..d5e202a
--- /dev/null
+++ b/scripts/cmake/templates/timing_adapter_settings.template
@@ -0,0 +1,64 @@
+/*
+ * Copyright (c) 2021 Arm Limited. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+// Auto-generated file
+// ** DO NOT EDIT **
+
+#ifndef TIMING_ADAPTER_SETTINGS_H
+#define TIMING_ADAPTER_SETTINGS_H
+
+#cmakedefine TA0_BASE (@TA0_BASE@)
+#cmakedefine TA1_BASE (@TA1_BASE@)
+
+/* Timing adapter settings for AXI0 */
+#if defined(TA0_BASE)
+
+#define TA0_MAXR (@TA0_MAXR@)
+#define TA0_MAXW (@TA0_MAXW@)
+#define TA0_MAXRW (@TA0_MAXRW@)
+#define TA0_RLATENCY (@TA0_RLATENCY@)
+#define TA0_WLATENCY (@TA0_WLATENCY@)
+#define TA0_PULSE_ON (@TA0_PULSE_ON@)
+#define TA0_PULSE_OFF (@TA0_PULSE_OFF@)
+#define TA0_BWCAP (@TA0_BWCAP@)
+#define TA0_PERFCTRL (@TA0_PERFCTRL@)
+#define TA0_PERFCNT (@TA0_PERFCNT@)
+#define TA0_MODE (@TA0_MODE@)
+#define TA0_HISTBIN (@TA0_HISTBIN@)
+#define TA0_HISTCNT (@TA0_HISTCNT@)
+
+#endif /* defined(TA0_BASE) */
+
+/* Timing adapter settings for AXI1 */
+#if defined(TA1_BASE)
+
+#define TA1_MAXR (@TA1_MAXR@)
+#define TA1_MAXW (@TA1_MAXW@)
+#define TA1_MAXRW (@TA1_MAXRW@)
+#define TA1_RLATENCY (@TA1_RLATENCY@)
+#define TA1_WLATENCY (@TA1_WLATENCY@)
+#define TA1_PULSE_ON (@TA1_PULSE_ON@)
+#define TA1_PULSE_OFF (@TA1_PULSE_OFF@)
+#define TA1_BWCAP (@TA1_BWCAP@)
+#define TA1_PERFCTRL (@TA1_PERFCTRL@)
+#define TA1_PERFCNT (@TA1_PERFCNT@)
+#define TA1_MODE (@TA1_MODE@)
+#define TA1_HISTBIN (@TA1_HISTBIN@)
+#define TA1_HISTCNT (@TA1_HISTCNT@)
+
+#endif /* defined(TA1_BASE) */
+
+#endif /* TIMING_ADAPTER_SETTINGS_H */
\ No newline at end of file
diff --git a/scripts/cmake/tensorflow.cmake b/scripts/cmake/tensorflow.cmake
new file mode 100644
index 0000000..1123c7f
--- /dev/null
+++ b/scripts/cmake/tensorflow.cmake
@@ -0,0 +1,130 @@
+#----------------------------------------------------------------------------
+# Copyright (c) 2021 Arm Limited. All rights reserved.
+# SPDX-License-Identifier: Apache-2.0
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#----------------------------------------------------------------------------
+
+include(ProcessorCount)
+ProcessorCount(J)
+
+if (CMAKE_BUILD_TYPE STREQUAL Debug)
+ set(TENSORFLOW_LITE_MICRO_DEFAULT_BUILD_TYPE "debug")
+ set(TENSORFLOW_LITE_MICRO_OPTIMIZATION_LEVEL "-O0")
+elseif (CMAKE_BUILD_TYPE STREQUAL Release)
+ set(TENSORFLOW_LITE_MICRO_DEFAULT_BUILD_TYPE "release")
+ set(TENSORFLOW_LITE_MICRO_OPTIMIZATION_LEVEL "-O3")
+elseif(CMAKE_BUILD_TYPE STREQUAL RelWithDebInfo)
+ set(TENSORFLOW_LITE_MICRO_DEFAULT_BUILD_TYPE "release_with_logs")
+ # No override for optimsiation level; we rely on the default
+ # optimisation applied by TensorFlow Lite Micro build here.
+elseif (NOT DEFINED TENSORFLOW_LITE_MICRO_BUILD_TYPE)
+ message(WARNING "TENSORFLOW_LITE_MICRO_BUILD_TYPE is not set.")
+ message(FATAL_ERROR "Build type ${CMAKE_BUILD_TYPE} does not have a corresponding "
+ "default to set TensorFlow build type")
+endif()
+
+USER_OPTION(TENSORFLOW_LITE_MICRO_BUILD_TYPE "TensorFlow Lite Mirco build type (release/debug etc.)"
+ ${TENSORFLOW_LITE_MICRO_DEFAULT_BUILD_TYPE}
+ STRING)
+
+USER_OPTION(TENSORFLOW_LITE_MICRO_CLEAN_DOWNLOADS "Select if TPIP downloads should be cleaned before each build."
+ OFF
+ BOOL)
+
+USER_OPTION(TENSORFLOW_LITE_MICRO_CLEAN_BUILD "Select if clean target should be added to a list of targets"
+ ON
+ BOOL)
+
+if (CMAKE_CXX_COMPILER_ID STREQUAL "ARMClang")
+ set(TENSORFLOW_LITE_MICRO_TOOLCHAIN "armclang")
+elseif (CMAKE_CXX_COMPILER_ID STREQUAL "GNU")
+ set(TENSORFLOW_LITE_MICRO_TOOLCHAIN "gcc")
+else ()
+ message(FATAL_ERROR "No compiler ID is set")
+endif()
+
+get_filename_component(TENSORFLOW_LITE_MICRO_TARGET_TOOLCHAIN_ROOT ${CMAKE_C_COMPILER} DIRECTORY)
+set(TENSORFLOW_LITE_MICRO_TARGET_TOOLCHAIN_ROOT "${TENSORFLOW_LITE_MICRO_TARGET_TOOLCHAIN_ROOT}/")
+
+set(TENSORFLOW_LITE_MICRO_PATH "${TENSORFLOW_SRC_PATH}/tensorflow/lite/micro")
+set(TENSORFLOW_LITE_MICRO_GENDIR ${CMAKE_CURRENT_BINARY_DIR}/tensorflow/)
+
+set(CMSIS_DSP_MAKEFILE_INC ${CMAKE_CURRENT_SOURCE_DIR}/scripts/make/cmsis_dsp.inc)
+set(ETHOS_EVAL_TARGET_MAKEFILE_INC ${CMAKE_CURRENT_SOURCE_DIR}/scripts/make/cortex_m_ethos_eval_makefile.inc)
+
+if (TARGET_PLATFORM STREQUAL native)
+ set(TENSORFLOW_LITE_MICRO_TARGET "linux")
+ set(TENSORFLOW_LITE_MICRO_TARGET_ARCH x86_64)
+else()
+ set(TENSORFLOW_LITE_MICRO_TARGET "cortex_m_ethos_eval")
+ set(TENSORFLOW_LITE_MICRO_TARGET_ARCH ${CMAKE_SYSTEM_PROCESSOR}${CPU_FEATURES})
+ if(ETHOS_U55_ENABLED)
+ # Arm Ethos-U55 NPU is the co-processor for ML workload:
+ set(TENSORFLOW_LITE_MICRO_CO_PROCESSOR "ethos_u")
+ endif()
+
+ set(TENSORFLOW_LITE_MICRO_OPTIMIZED_KERNEL "cmsis_nn")
+
+ # Copy over the target helper (cortex_m_ethos_eval)
+ file(COPY ${ETHOS_EVAL_TARGET_MAKEFILE_INC}
+ DESTINATION ${TENSORFLOW_LITE_MICRO_PATH}/tools/make/targets/)
+endif()
+
+if (TENSORFLOW_LITE_MICRO_CLEAN_DOWNLOADS)
+ list(APPEND MAKE_TARGETS_LIST "clean_downloads")
+endif()
+
+if (TENSORFLOW_LITE_MICRO_CLEAN_BUILD)
+ list(APPEND MAKE_TARGETS_LIST "clean")
+endif()
+
+# Primary target
+list(APPEND MAKE_TARGETS_LIST "microlite")
+message(STATUS "TensorFlow Lite Micro build to be called for these targets: ${MAKE_TARGETS_LIST}")
+
+# Commands and targets
+add_custom_target(tensorflow_build ALL
+
+ # Command to build the TensorFlow Lite Micro library
+ COMMAND make -j${J} -f ${TENSORFLOW_LITE_MICRO_PATH}/tools/make/Makefile ${MAKE_TARGETS_LIST}
+ TARGET_TOOLCHAIN_ROOT=${TENSORFLOW_LITE_MICRO_TARGET_TOOLCHAIN_ROOT}
+ TOOLCHAIN=${TENSORFLOW_LITE_MICRO_TOOLCHAIN}
+ GENDIR=${TENSORFLOW_LITE_MICRO_GENDIR}
+ TARGET=${TENSORFLOW_LITE_MICRO_TARGET}
+ TARGET_ARCH=${TENSORFLOW_LITE_MICRO_TARGET_ARCH}
+ BUILD_TYPE=${TENSORFLOW_LITE_MICRO_BUILD_TYPE}
+ ETHOSU_DRIVER_PATH=${ETHOS_U55_DRIVER_SRC_PATH}
+ CMSIS_PATH=${CMSIS_SRC_PATH}
+
+ # Conditional arguments
+ $<$<BOOL:${ARMCLANG_DEBUG_DWARF_LEVEL}>:ARMCLANG_DEBUG_DWARF_LEVEL=${ARMCLANG_DEBUG_DWARF_LEVEL}>
+ $<$<BOOL:${TENSORFLOW_LITE_MICRO_OPTIMIZATION_LEVEL}>:OPTIMIZATION_LEVEL=${TENSORFLOW_LITE_MICRO_OPTIMIZATION_LEVEL}>
+ $<$<BOOL:${TENSORFLOW_LITE_MICRO_OPTIMIZED_KERNEL}>:OPTIMIZED_KERNEL_DIR=${TENSORFLOW_LITE_MICRO_OPTIMIZED_KERNEL}>
+ $<$<BOOL:${TENSORFLOW_LITE_MICRO_CO_PROCESSOR}>:CO_PROCESSOR=${TENSORFLOW_LITE_MICRO_CO_PROCESSOR}>
+
+ # Command to copy over the generated library to the local build tree.
+ COMMAND ${CMAKE_COMMAND} -E copy ${TENSORFLOW_LITE_MICRO_GENDIR}/lib/${TENSORFLOW_LITE_MICRO_PLATFORM_LIB_NAME}
+ ${CMAKE_LIBRARY_OUTPUT_DIRECTORY}/${TENSORFLOW_LITE_MICRO_PLATFORM_LIB_NAME}
+
+ COMMENT "Building TensorFlow Lite Micro library..."
+
+ BYPRODUCTS ${TENSORFLOW_SRC_PATH}/tensorflow/tensorflow/lite/micro/tools/make/downloads
+ ${CMAKE_LIBRARY_OUTPUT_DIRECTORY}/${TENSORFLOW_LITE_MICRO_PLATFORM_LIB_NAME}
+ ${TENSORFLOW_LITE_MICRO_GENDIR}/lib/${TENSORFLOW_LITE_MICRO_PLATFORM_LIB_NAME}
+
+ WORKING_DIRECTORY ${TENSORFLOW_SRC_PATH})
+
+# Create library
+add_library(tensorflow-lite-micro STATIC IMPORTED)
+add_dependencies(tensorflow-lite-micro tensorflow_build)
diff --git a/scripts/cmake/util_functions.cmake b/scripts/cmake/util_functions.cmake
new file mode 100644
index 0000000..6d76131
--- /dev/null
+++ b/scripts/cmake/util_functions.cmake
@@ -0,0 +1,143 @@
+#----------------------------------------------------------------------------
+# Copyright (c) 2021 Arm Limited. All rights reserved.
+# SPDX-License-Identifier: Apache-2.0
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#----------------------------------------------------------------------------
+
+##############################################################################
+# Helper function to provide user option and corresponding default value
+##############################################################################
+function(USER_OPTION name description default type)
+
+ if (NOT DEFINED ${name})
+ set(${name} ${default} CACHE ${type} ${description})
+ endif()
+
+ # if it is a path
+ if (${type} STREQUAL PATH)
+
+ # Get the absolute path, relative to the cmake root
+ get_filename_component(ABSPATH "${${name}}" ABSOLUTE BASE_DIR ${CMAKE_SOURCE_DIR})
+
+ # check that this is a directory
+ if (NOT IS_DIRECTORY ${ABSPATH})
+ message(FATAL_ERROR
+ "Invalid directory path. Description: ${description}; Path: ${ABSPATH}")
+ endif()
+
+ set(${name} ${ABSPATH} CACHE ${type} ${description} FORCE)
+
+ # if this is a file path
+ elseif(${type} STREQUAL FILEPATH)
+
+ # Get the absolute path, relative to the cmake root
+ get_filename_component(ABSPATH "${${name}}" ABSOLUTE BASE_DIR ${CMAKE_SOURCE_DIR})
+
+ # check that the file exists:
+ if (NOT EXISTS ${ABSPATH})
+ message(FATAL_ERROR
+ "Invalid file path. Description: ${description}; Path: ${ABSPATH}")
+ endif()
+
+ set(${name} ${ABSPATH} CACHE ${type} ${description} FORCE)
+
+ endif()
+
+ message(STATUS "User option ${name} is set to ${${name}}")
+ LIST(APPEND USER_OPTIONS ${name})
+ set(USER_OPTIONS ${USER_OPTIONS} CACHE INTERNAL "")
+
+endfunction()
+
+# Function to get the path type for a variable
+# Args:
+# path_var[in]: path variable for which the cmake path type is requested
+# cmake_path_type[out]: CMake path type. Set to FILEPATH when it is a file
+# or PATH when it points to a directory. If the path
+# is invalid, this remains empty.
+function(get_path_type path_var cmake_path_type)
+ # Validate path - get absolute value
+ get_filename_component(ABSPATH "${path_var}" ABSOLUTE
+ BASE_DIR ${CMAKE_SOURCE_DIR})
+
+ if (DEFINED path_var)
+ if (IS_DIRECTORY ${ABSPATH})
+ set(${cmake_path_type} PATH PARENT_SCOPE)
+ message(STATUS "Variable of PATH type")
+ elseif(EXISTS ${ABSPATH})
+ set(${cmake_path_type} FILEPATH PARENT_SCOPE)
+ else()
+ set(${cmake_path_type} "" PARENT_SCOPE)
+ endif()
+ else()
+ set(${cmake_path_type} UNINITIALIZED PARENT_SCOPE)
+ endif()
+
+endfunction()
+
+# Function to print all the user options added using the function `USER_OPTION`
+function(print_useroptions)
+ message(STATUS "--------------------------------------------------------------------------------------------------")
+ message(STATUS "Defined build user options:")
+ message(STATUS "")
+ foreach(opt ${USER_OPTIONS})
+ message(STATUS " ${opt}=${${opt}}")
+ endforeach()
+ message(STATUS "--------------------------------------------------------------------------------------------------")
+endfunction()
+
+function (SUBDIRLIST result curdir)
+ file(GLOB children RELATIVE ${curdir} ${curdir}/*)
+ set(dirlist "")
+ foreach(child ${children})
+ if(IS_DIRECTORY ${curdir}/${child})
+ LIST(APPEND dirlist ${child})
+ endif()
+ endforeach()
+ set(${result} ${dirlist} PARENT_SCOPE)
+endfunction()
+
+function(to_py_bool cmake_bool py_bool)
+ if(${${cmake_bool}})
+ set(${py_bool} True PARENT_SCOPE)
+ else()
+ set(${py_bool} False PARENT_SCOPE)
+ endif()
+endfunction()
+
+# Function to download a files from the Arm Model Zoo
+# Arguments:
+# file_sub_path: subpath within the model zoo respository
+# download_path: location where this file is to be downloaded (path including filename)
+function(download_file_from_modelzoo file_sub_path download_path)
+
+ set(MODEL_ZOO_REPO "https://github.com/ARM-software/ML-zoo/raw")
+ set(MODEL_ZOO_VERSION "68b5fbc77ed28e67b2efc915997ea4477c1d9d5b")
+
+ string(JOIN "/" FILE_URL
+ ${MODEL_ZOO_REPO} ${MODEL_ZOO_VERSION} ${file_sub_path})
+
+ message(STATUS "Downloading ${FILE_URL} to ${download_path}...")
+
+ file(DOWNLOAD ${FILE_URL} ${download_path}
+ STATUS DOWNLOAD_STATE)
+ list(GET DOWNLOAD_STATE 0 RET_VAL)
+
+ if(${RET_VAL})
+ list(GET DOWNLOAD_STATE 1 RET_MSG)
+ message(FATAL_ERROR "Download failed with error code: ${RET_VAL}; "
+ "Error message: ${RET_MSG}")
+ endif()
+
+endfunction()