MLECO-4826: Targeting Arm Corstone-315 boot ROM
* Updating linker scripts + scatter files to utilise
64KiB boot region of Corstone-315.
* Now target 3 loading regions - boot, bram and dram.
Change-Id: Ieb9f03e53d913ded4facc15ab2171ce647b405e5
Signed-off-by: Alex Tawse <alex.tawse@arm.com>
Tested-by: mlecosys <mlecosys@arm.com>
Reviewed-by: Kshitij Sisodia <kshitij.sisodia@arm.com>
Signed-off-by: Kshitij Sisodia <kshitij.sisodia@arm.com>
diff --git a/scripts/cmake/platforms/mps3/build_configuration.cmake b/scripts/cmake/platforms/mps3/build_configuration.cmake
index 101abdd..8613f50 100644
--- a/scripts/cmake/platforms/mps3/build_configuration.cmake
+++ b/scripts/cmake/platforms/mps3/build_configuration.cmake
@@ -17,7 +17,7 @@
#----------------------------------------------------------------------------
function(set_platform_global_defaults)
- message(STATUS "Platform: MPS3 FPGA Prototyping Board or FVP")
+ message(STATUS "Platform: Arm MPS3 FPGA Prototyping Board or FVP")
# Set default subsystem for MPS3:
USER_OPTION(TARGET_SUBSYSTEM "Specify platform target subsystem: sse-300 or sse-310"
diff --git a/scripts/cmake/platforms/mps3/sse-310/mps3-sse-310.ld b/scripts/cmake/platforms/mps3/sse-310/mps3-sse-310.ld
index 085be99..0b6ad79 100644
--- a/scripts/cmake/platforms/mps3/sse-310/mps3-sse-310.ld
+++ b/scripts/cmake/platforms/mps3/sse-310/mps3-sse-310.ld
@@ -1,5 +1,5 @@
/*
- * SPDX-FileCopyrightText: Copyright 2021, 2023 Arm Limited and/or its affiliates <open-source-office@arm.com>
+ * SPDX-FileCopyrightText: Copyright 2021, 2023-2024 Arm Limited and/or its affiliates <open-source-office@arm.com>
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@@ -22,8 +22,8 @@
MEMORY
{
ITCM (rx) : ORIGIN = 0x10000000, LENGTH = 0x00008000
- DTCM (rwx) : ORIGIN = 0x30000000, LENGTH = 0x00008000
BRAM (rwx) : ORIGIN = 0x11000000, LENGTH = 0x00200000
+ DTCM (rwx) : ORIGIN = 0x30000000, LENGTH = 0x00008000
SRAM (rwx) : ORIGIN = 0x31000000, LENGTH = 0x00400000
DDR (rwx) : ORIGIN = 0x70000000, LENGTH = 0x02000000
diff --git a/scripts/cmake/platforms/mps4/build_configuration.cmake b/scripts/cmake/platforms/mps4/build_configuration.cmake
index 918091a..8230c1f 100644
--- a/scripts/cmake/platforms/mps4/build_configuration.cmake
+++ b/scripts/cmake/platforms/mps4/build_configuration.cmake
@@ -83,8 +83,8 @@
file(MAKE_DIRECTORY ${SECTORS_BIN_DIR})
if (TARGET_SUBSYSTEM STREQUAL sse-315)
- set(LINKER_SECTION_TAGS "*.at_itcm" "*.at_ddr")
- set(LINKER_OUTPUT_BIN_TAGS "itcm.bin" "ddr.bin")
+ set(LINKER_SECTION_TAGS "*.at_boot" "*.at_bram" "*.at_ddr")
+ set(LINKER_OUTPUT_BIN_TAGS "boot.bin" "bram.bin" "ddr.bin")
endif()
add_bin_generation_command(
@@ -119,7 +119,6 @@
-C mps4_board.uart0.shutdown_on_eot=1
-C mps4_board.visualisation.disable-visualisation=1
-C vis_hdlcd.disable_visualisation=1
- -C mps4_board.subsystem.iotss3_systemcontrol.INITSVTOR_RST=0x12000000
--stat)
endif()
endif ()
diff --git a/scripts/cmake/platforms/mps4/sse-315/mps4-sse-315.ld b/scripts/cmake/platforms/mps4/sse-315/mps4-sse-315.ld
index 10ead0e..a5647f9 100644
--- a/scripts/cmake/platforms/mps4/sse-315/mps4-sse-315.ld
+++ b/scripts/cmake/platforms/mps4/sse-315/mps4-sse-315.ld
@@ -22,9 +22,9 @@
MEMORY
{
ITCM (rx) : ORIGIN = 0x10000000, LENGTH = 0x00008000
- DTCM (rwx) : ORIGIN = 0x30000000, LENGTH = 0x00008000
BOOT (rx) : ORIGIN = 0x11000000, LENGTH = 0x00010000
BRAM (rwx) : ORIGIN = 0x12000000, LENGTH = 0x00200000
+ DTCM (rwx) : ORIGIN = 0x30000000, LENGTH = 0x00008000
SRAM (rwx) : ORIGIN = 0x31000000, LENGTH = 0x00400000
DDR (rwx) : ORIGIN = 0x70000000, LENGTH = 0x02000000
@@ -70,9 +70,13 @@
SECTIONS
{
- .text.at_bram :
+ .text.at_boot :
{
KEEP(*(.vectors))
+ } > BOOT AT > BOOT
+
+ .text.at_bram :
+ {
*(.text*)
KEEP(*(.init))
diff --git a/scripts/cmake/platforms/mps4/sse-315/mps4-sse-315.sct b/scripts/cmake/platforms/mps4/sse-315/mps4-sse-315.sct
index 4451f21..35b5904 100644
--- a/scripts/cmake/platforms/mps4/sse-315/mps4-sse-315.sct
+++ b/scripts/cmake/platforms/mps4/sse-315/mps4-sse-315.sct
@@ -25,30 +25,41 @@
;
;---------------------------------------------------------
-; First load region (FPGA SRAM) 2MiB region
-; NOTE: The default INITSVTOR is 0x11000000 and not the
-; ITCM (32K) which we do not use for any code, but
-; could potentially put some critical code in there
-; if we need to.
-; @TODO: The memory pointed to by the INITSVTOR is a 64
-; kiB location for boot code which we should use.
+; First load region (SRAM) 64KiB boot region
;---------------------------------------------------------
-LOAD_REGION_0 0x12000000 0x00200000
+LOAD_REGION_0 0x11000000 0x00010000
{
;-----------------------------------------------------
- ; First 640K of FGPA SRAM.
+ ; 64K boot ROM. Our vector table also
+ ; resides here as the default INITSVTOR is 0x11000000.
+ ; We currently do not use the ITCM for any code, but
+ ; could potentially put some critical code in there
+ ; if we need to.
;-----------------------------------------------------
- bram.bin 0x12000000 0x000A0000
+ boot.bin 0x11000000 0x00010000
{
- *.o (RESET, +First)
- * (InRoot$$Sections)
+ *.o (RESET, +First)
+ *(InRoot$$Sections)
+ }
+}
- ; Essentially only RO (code + data)
+;---------------------------------------------------------
+; Second load region (FPGA SRAM) 2MiB region
+;---------------------------------------------------------
+LOAD_REGION_1 0X12000000 0x00200000
+{
+ ;-----------------------------------------------------
+ ; First 640K of SRAM/BRAM region for RO code,
+ ; 8 byte aligned.
+ ;-----------------------------------------------------
+ bram.bin 0x12000000 ALIGN 8 0x000A0000
+ {
+ ; Essentially only RO (code)
.ANY (+RO)
}
;-----------------------------------------------------
- ; Next 384K of SRAM/BRAM region for RO, RW and ZI
+ ; Next 384K of SRAM/BRAM region for RW and ZI
; data, 8 byte aligned.
;-----------------------------------------------------
data.bin 0x120A0000 ALIGN 8 0x00060000
@@ -91,9 +102,9 @@
}
;---------------------------------------------------------
-; Second load region (DDR)
+; Third load region (DDR)
;---------------------------------------------------------
-LOAD_REGION_1 0x70000000 0x02000000
+LOAD_REGION_2 0x70000000 0x02000000
{
;-----------------------------------------------------
; 32 MiB of DDR space for neural network model,