diff --git a/CMakeLists.txt b/CMakeLists.txt
index a3e238a..9d6ed7c 100644
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@@ -234,6 +234,7 @@
     if (${SRC_USE_CASE} STREQUAL "")
         message(FATAL_ERROR "Failed to find sources for ${use_case}!")
     endif ()
+
     # Executable application:
     set(TARGET_NAME "ethos-u-${use_case}")
 
diff --git a/docs/documentation.md b/docs/documentation.md
index 7049630..f1fab8c 100644
--- a/docs/documentation.md
+++ b/docs/documentation.md
@@ -37,13 +37,17 @@
   [Arm Compiler download Page](https://developer.arm.com/tools-and-software/embedded/arm-compiler/downloads)
 
 - An Arm® MPS3 FPGA prototyping board and components for FPGA evaluation or a `Fixed Virtual Platform` binary:
-  - An MPS3 board loaded with Arm® Corstone™-300 reference package (`AN547`) from:
+  - An MPS3 board loaded with Arm® Corstone™-300 reference package (`AN552`) from:
     <https://developer.arm.com/tools-and-software/development-boards/fpga-prototyping-boards/download-fpga-images>. You
     must have a USB connection between your machine and the MPS3 board - for UART menu and for deploying the
     application.
   - `Arm Corstone-300` based FVP for MPS3 is available from:
     <https://developer.arm.com/tools-and-software/open-source-software/arm-platforms-software/arm-ecosystem-fvps>.
 
+> **NOTE**: There are two Arm® Corstone™-300 implementations available for the MPS3 FPGA board - application
+> notes `AN547` and `AN552`. We are aligned with the latest application note `AN552`. However, the application built
+> for MPS3 target should work on both FPGA packages.
+
 ### Additional reading
 
 This document contains information that is specific to Arm® Ethos™-U55 and Arm® Ethos™-U65 products. Please refer to the following documents
@@ -336,4 +340,4 @@
 
 ## FAQ
 
-Please refer to: [FAQ](./sections/faq.md#faq)
\ No newline at end of file
+Please refer to: [FAQ](./sections/faq.md#faq)
diff --git a/docs/sections/deployment.md b/docs/sections/deployment.md
index a3cbbd2..034fb19 100644
--- a/docs/sections/deployment.md
+++ b/docs/sections/deployment.md
@@ -22,7 +22,7 @@
 The FVP is available publicly from the following page:
 [Arm Ecosystem FVP downloads](https://developer.arm.com/tools-and-software/open-source-software/arm-platforms-software/arm-ecosystem-fvps).
 
-Please ensure that you download the correct archive from the list under `Arm Corstone-300`. You need the one which:
+Please ensure that you download the correct archive from the list under Arm® *Corstone™-300*. You need the one which:
 
 - Emulates MPS3 board and *not* for MPS2 FPGA board,
 - Contains support for Arm® *Ethos™-U55*.
@@ -158,24 +158,31 @@
 ### Deployment on MPS3 board
 
 > **Note:**: These instructions are valid only if the evaluation is being done using the MPS3 FPGA platform using
-> `SSE-300`.
+> an Arm® *Corstone™-300* implementation.
 
 To run the application on MPS3 platform, you must first ensure that the platform has been set up using the correct
 configuration.
 
-For details on platform set-up, please see the relevant documentation. For the Arm `Corstone-300`, the PDF is available
-here: [Arm Developer](https://developer.arm.com/-/media/Arm%20Developer%20Community/PDF/DAI0547B_SSE300_PLUS_U55_FPGA_for_mps3.pdf?revision=d088d931-03c7-40e4-9045-31ed8c54a26f&la=en&hash=F0C7837C8ACEBC3A0CF02D871B3A6FF93E09C6B8).
+For details on platform set-up, please see the relevant documentation. For the Arm® Corstone™-300 implementation
+`AN552`, the document is available here: [Arm Developer](https://developer.arm.com/documentation/dai0552/).
 
-For the MPS3 board, instead of loading the `axf` file directly, copy the executable blobs generated under the
-`sectors/<use_case>` subdirectory to the micro SD card located on the board. Also, the `sectors/images.txt` file is used
-by the MPS3 to understand which memory regions the blobs must be loaded into.
+For the MPS3 FPGA board, instead of loading the `axf` file directly, copy the executable blobs generated under the
+`sectors/<use_case>` subdirectory to the micro SD card located on the board. Also, the `sectors/images.txt` file is
+used by the MPS3 to understand which memory regions the blobs must be loaded into.
 
 Once the USB A to USB B cable between the MPS3 and the development machine is connected, and the MPS3 board powered on,
 the board enumerates as a mass storage device over this USB connection.
 
 Depending on the version of the board you are using, there might be two devices listed. The device named `V2M-MPS3`, or
-`V2MMPS3`, which is the `SD card`. Note that if `V2M-MPS3` or `V2MMPS3` device is not listed, you may need to enable USB
-connection from the board. You can do this by opening a serial connection to the first serial port and issuing a `usb_on` command.
+`V2MMPS3` is the `SD card`. Note that if `V2M-MPS3` or `V2MMPS3` device is not listed, you may need to enable USB
+connection from the board. You can do this by opening a serial connection to the first serial port (as specified in
+point 3 in the instructions below) and issuing a `usb_on` command at the prompt:
+
+```commandline
+Cmd> usb_on
+Enabling debug USB...
+USB Serial Number = 5000123456789
+```
 
 If the `axf` or `elf` file is within the ITCM load size limit, it can be copied into the FPGA memory directly without
 having to break it down into separate load region-specific blobs. However, if the neural network models exceed this
@@ -196,21 +203,23 @@
     cp -av ./bin/sectors/img_class/* /media/user/V2M-MPS3/SOFTWARE/
     ```
 
-    Note that the `itcm.bin` and `ddr.bin` files correspond to the part of the application residing in the first and second load region respectively,
-    as defined in the [scatter file](../../source/application/hal/platforms/bare-metal/bsp/mem_layout/mps3-sse-300.sct).
+    Note that the `itcm.bin` and `ddr.bin` files correspond to the part of the application residing in the first and
+    second load region respectively, as defined in the
+    [scatter file](../../source/application/hal/platforms/bare-metal/bsp/mem_layout/mps3-sse-300.sct).
 
 2. The `./bin/sectors/images.txt` file must be copied over to the MPS3. The exact location for the destination depends
    on the version of the MPS3 board and the application note for the bit file in use.
 
-   For example, the revision C of the MPS3 board hardware uses an application note directory named `AN547`, to replace the
+   For example, the revision C of the MPS3 board hardware uses an application note directory named `AN552`, to replace the
    `images.txt` file, like so:
 
     ```commandline
-    cp ./bin/sectors/images.txt /media/user/V2M-MPS3/MB/HBI0309C/AN547/images.txt
+    cp ./bin/sectors/images.txt /media/user/V2M-MPS3/MB/HBI0309C/AN552/images.txt
     ```
 
 3. Open the first serial port available from MPS3. For example, `/dev/ttyUSB0`. This can be typically done using
-   minicom, screen, or Putty application. Make sure the flow control setting is switched off:
+   `minicom`, `screen`, or `Putty` applications. Make sure the configuration is set to 115200 8/N/1 and that the
+   flow control setting is switched off:
 
     ```commandline
     minicom --D /dev/ttyUSB0
@@ -238,10 +247,12 @@
     ```
 
     ```log
-    Rebooting...Disabling debug USB..Board rebooting...
+    Rebooting...
+    Disabling debug USB..
+    Board rebooting...
 
-    ARM V2M-MPS3 Firmware v1.3.2
-    Build Date: Apr 20 2018
+    ARM V2M-MPS3 Firmware v1.5.1
+    Build Date: Jun  2 2021
 
     Powering up system...
     Switching on main power...
@@ -252,40 +263,37 @@
     FPGA memory locations. For example:
 
     ```log
-    Reading images file \MB\HBI0309C\AN547\images.txt
+    Reading images file \MB\HBI0309C\AN552\images.txt
     Writing File \SOFTWARE\itcm.bin to Address 0x00000000
-
-    ............
-
+    ......
     File \SOFTWARE\itcm.bin written to memory address 0x00000000
     Image loaded from \SOFTWARE\itcm.bin
-    Writing File \SOFTWARE\ddr.bin to Address 0x08000000
-
-    ..........................................................................
-
-
-    File \SOFTWARE\ddr.bin written to memory address 0x08000000
+    Writing File \SOFTWARE\ddr.bin to Address 0x0C000000
+    .......................................................................................................................................................................
+    File \SOFTWARE\ddr.bin written to memory address 0x0C000000
     Image loaded from \SOFTWARE\ddr.bin
     ```
 
-6. When the reboot from previous step is completed, issue a reset command on the command prompt:
+6. If the reboot from previous step completes without starting the application, issue a reset command:
 
     ``` commandline
     $ Cmd> reset
     ```
 
-    This triggers the application to start, and the output becomes visible on the second serial connection.
+    This should trigger the application to start, and the output should be visible on the second serial
+    connection. By default, the FPGA configuration should start the application as soon as it is loaded
+    into the memory and the above command should not be required.
 
-7. On the second serial port, the output is similar to that in section 2.2, is visible, like so:
+7. On the second serial port the output should show the standard output and error streams from the
+   application deployed. For example:
 
     ```log
-    INFO - Setting up system tick IRQ (for NPU)
     INFO - V2M-MPS3 revision C
-    INFO - Application Note AN540, Revision B
-    INFO - FPGA build 1
-    INFO - Core clock has been set to: 32000000 Hz
-    INFO - CPU ID: 0x410fd220
-    INFO - CPU: Cortex-M55 r0p0
+    INFO - Application Note AN552, Revision B
+    INFO - MPS3 build 2
+    INFO - MPS3 core clock has been set to: 32000000Hz
+    INFO - CPU ID: 0x411fd220
+    INFO - CPU: Cortex-M55 r1p0
     ...
     ```
 
diff --git a/docs/sections/memory_considerations.md b/docs/sections/memory_considerations.md
index 89acb1e..b3cbfa5 100644
--- a/docs/sections/memory_considerations.md
+++ b/docs/sections/memory_considerations.md
@@ -41,27 +41,28 @@
 See the example for Arm® *Corstone™-300* description file [corstone-sse-300.cmake](../../scripts/cmake/subsystem-profiles/corstone-sse-300.cmake). For the discussion on this page, it is useful to note the following definitions:
 
 ```
-set(ISRAM0_SIZE           "0x00200000" CACHE STRING "ISRAM0 size:       2 MiB")
-set(ISRAM1_SIZE           "0x00200000" CACHE STRING "ISRAM1 size:       2 MiB")
+set(ISRAM0_SIZE           "0x00100000" CACHE STRING "ISRAM0 size:       1 MiB")
+set(ISRAM1_SIZE           "0x00100000" CACHE STRING "ISRAM1 size:       1 MiB")
 ...
 # SRAM size reserved for activation buffers
 math(EXPR ACTIVATION_BUF_SRAM_SZ "${ISRAM0_SIZE} + ${ISRAM1_SIZE}" OUTPUT_FORMAT HEXADECIMAL)
 ```
-This will set `ACTIVATION_BUF_SRAM_SZ` to be **4 MiB** for Arm® *Corstone™-300* target platform.
+This will set `ACTIVATION_BUF_SRAM_SZ` to be **2 MiB** for Arm® *Corstone™-300* target platform.
 As mentioned in the comments within the file, this size is directly linked to the size mentioned
 in the linker scripts, and therefore, it should not be changed without corresponding changes
-in the linker script too. For example, a snippet from the scatter file for Corstone™-300 shows:
+in the linker script too. For example, a snippet from the scatter file for Arm® *Corstone™-300*
+shows:
 
 ```
 ;-----------------------------------------------------
-; SSE-300's internal SRAM of 4MiB - reserved for
-; activation buffers.
+; FPGA internal SRAM of 2MiB - reserved for activation
+; buffers.
 ; This region should have 3 cycle read latency from
 ; both Cortex-M55 and Ethos-U NPU
 ;-----------------------------------------------------
-isram.bin       0x31000000  UNINIT ALIGN 16 0x00400000
+isram.bin       0x31000000  UNINIT ALIGN 16 0x00200000
 {
-  ...
+    ...
 }
 ```
 If the usable size of the internal SRAM was to be increased/decreased, the change should be
@@ -73,16 +74,13 @@
 CMake files, there are other parameters linked to what the reserved space for activation
 buffers is. These are:
 
-- The file [default_vela.ini](../../scripts/vela/default_vela.ini) contains a parameter called
-  `arena_cache_size` under `Shared_Sram` memory mode. For example:
+- The file [set_up_default_resources.py](../../set_up_default_resources.py) contains a
+  parameter called `mps3_max_sram_sz`:
   ```
-  [Memory_Mode.Shared_Sram]
-  const_mem_area=Axi1
-  arena_mem_area=Axi0
-  cache_mem_area=Axi0
-  arena_cache_size=4194304
+  # The internal SRAM size for Corstone-300 implementation on MPS3 specified by AN552
+  mps3_max_sram_sz = 2 * 1024 * 1024 # 2 MiB (2 banks of 1 MiB each)
   ```
-  This size of **4 MiB** here is provided here to allow the default vela optimisation process to
+  This size of **2 MiB** here is provided here to allow the default vela optimisation process to
   use this size as a hint for the available SRAM size for use by the CPU and the NPU.
 
 - In every `usecase.cmake` file (present within each use case's source directory), there is
diff --git a/release_notes.txt b/release_notes.txt
index 5bd8137..aaa9151 100644
--- a/release_notes.txt
+++ b/release_notes.txt
@@ -5,6 +5,7 @@
     * Added Noise Reduction use case.
     * Updated support for Arm GNU Embedded Toolchain 10.3-2021.07 and Arm Compiler 6.17.
     * Documentation updates.
+    * Changes to support AN552 design - the new Arm® Corstone™-300 implementation.
 
 Changes in 21.08
     * Support for 21.05 Ethos-U component (core-software, core-driver, Vela 3.0.0).
@@ -57,4 +58,4 @@
     * Used EAC Ethos-U55 software model and drivers.
     * Windows support for build scripts.
 Known issues:
-    * telnet connection to FastModel environment may hang after some period of inactivity.
\ No newline at end of file
+    * telnet connection to FastModel environment may hang after some period of inactivity.
diff --git a/scripts/cmake/subsystem-profiles/corstone-sse-300.cmake b/scripts/cmake/subsystem-profiles/corstone-sse-300.cmake
index 7e27f3c..9382d4a 100644
--- a/scripts/cmake/subsystem-profiles/corstone-sse-300.cmake
+++ b/scripts/cmake/subsystem-profiles/corstone-sse-300.cmake
@@ -21,9 +21,9 @@
 ###################################################################################################
 set(ITCM_SIZE             "0x00080000" CACHE STRING "ITCM size:       512 kiB")
 set(DTCM_BLK_SIZE         "0x00020000" CACHE STRING "DTCM size:       128 kiB, 4 banks")
-set(BRAM_SIZE             "0x00200000" CACHE STRING "BRAM size:         2 MiB")
-set(ISRAM0_SIZE           "0x00200000" CACHE STRING "ISRAM0 size:       2 MiB")
-set(ISRAM1_SIZE           "0x00200000" CACHE STRING "ISRAM1 size:       2 MiB")
+set(BRAM_SIZE             "0x00100000" CACHE STRING "BRAM size:         1 MiB")
+set(ISRAM0_SIZE           "0x00100000" CACHE STRING "ISRAM0 size:       1 MiB")
+set(ISRAM1_SIZE           "0x00100000" CACHE STRING "ISRAM1 size:       1 MiB")
 set(QSPI_SRAM_SIZE        "0x00800000" CACHE STRING "QSPI Flash size:   8 MiB")
 set(DDR4_BLK_SIZE         "0x10000000" CACHE STRING "DDR4 block size: 256 MiB")
 
@@ -37,7 +37,7 @@
 set(DTCM2_BASE_NS         "0x20040000" CACHE STRING "Data TCM block 2 Non-Secure base address")
 set(DTCM3_BASE_NS         "0x20060000" CACHE STRING "Data TCM block 3 Non-Secure base address")
 set(ISRAM0_BASE_NS        "0x21000000" CACHE STRING "Internal SRAM Area Non-Secure base address")
-set(ISRAM1_BASE_NS        "0x21200000" CACHE STRING "Internal SRAM Area Non-Secure base address")
+set(ISRAM1_BASE_NS        "0x21100000" CACHE STRING "Internal SRAM Area Non-Secure base address")
 set(QSPI_SRAM_BASE_NS     "0x28000000" CACHE STRING "QSPI SRAM Non-Secure base address")
 set(DDR4_BLK0_BASE_NS     "0x60000000" CACHE STRING "DDR4 block 0 Non-Secure base address")
 set(DDR4_BLK1_BASE_NS     "0x80000000" CACHE STRING "DDR4 block 1 Non-Secure base address")
@@ -51,7 +51,7 @@
 set(DTCM2_BASE_S          "0x30040000" CACHE STRING "Data TCM block 2 Secure base address")
 set(DTCM3_BASE_S          "0x30060000" CACHE STRING "Data TCM block 3 Secure base address")
 set(ISRAM0_BASE_S         "0x31000000" CACHE STRING "Internal SRAM Area Secure base address")
-set(ISRAM1_BASE_S         "0x31200000" CACHE STRING "Internal SRAM Area Secure base address")
+set(ISRAM1_BASE_S         "0x31100000" CACHE STRING "Internal SRAM Area Secure base address")
 set(DDR4_BLK0_BASE_S      "0x70000000" CACHE STRING "DDR4 block 0 Secure base address")
 set(DDR4_BLK1_BASE_S      "0x90000000" CACHE STRING "DDR4 block 1 Secure base address")
 set(DDR4_BLK2_BASE_S      "0xB0000000" CACHE STRING "DDR4 block 2 Secure base address")
@@ -60,11 +60,11 @@
 ###################################################################################################
 #                              Application specific config                                        #
 ###################################################################################################
+set(APP_NOTE               "AN552")
+set(DESIGN_NAME            "Arm Corstone-300 - ${APP_NOTE}" CACHE STRING "Design name")
 
-# This parameter is based on the linker/scatter script for SSE-300. Do not change this parameter
-# in isolation.
-set(DESIGN_NAME            "Arm Corstone-300 (SSE-300)" CACHE STRING "Design name")
-
+# The following parameter is based on the linker/scatter script for SSE-300.
+# Do not change this parameter in isolation.
 # SRAM size reserved for activation buffers
 math(EXPR ACTIVATION_BUF_SRAM_SZ "${ISRAM0_SIZE} + ${ISRAM1_SIZE}" OUTPUT_FORMAT HEXADECIMAL)
 
@@ -258,7 +258,7 @@
 set(SPI4_IRQn                     "55" CACHE STRING " SPI 4 Interrupt (Sheild 1)            ")
 
 if (ETHOS_U_NPU_ENABLED)
-set(EthosU_IRQn                   "56" CACHE STRING " Ethos-U55 Interrupt                  ")
+set(EthosU_IRQn                   "56" CACHE STRING " Ethos-U55 Interrupt                   ")
 endif ()
 
 set(GPIO0_IRQn                    "69" CACHE STRING " GPIO 0 Combined Interrupt             ")
diff --git a/scripts/cmake/subsystem-profiles/simple_platform.cmake b/scripts/cmake/subsystem-profiles/simple_platform.cmake
index 664697b..e6cfef3 100644
--- a/scripts/cmake/subsystem-profiles/simple_platform.cmake
+++ b/scripts/cmake/subsystem-profiles/simple_platform.cmake
@@ -24,9 +24,9 @@
 ###################################################################################################
 set(ITCM_SIZE             "0x00080000" CACHE STRING "ITCM size:       512 kiB")
 set(DTCM_BLK_SIZE         "0x00020000" CACHE STRING "DTCM size:       128 kiB, 4 banks")
-set(BRAM_SIZE             "0x00200000" CACHE STRING "BRAM size:         2 MiB")
-set(ISRAM0_SIZE           "0x00200000" CACHE STRING "ISRAM0 size:       2 MiB")
-set(ISRAM1_SIZE           "0x00200000" CACHE STRING "ISRAM1 size:       2 MiB")
+set(BRAM_SIZE             "0x00100000" CACHE STRING "BRAM size:         1 MiB")
+set(ISRAM0_SIZE           "0x00100000" CACHE STRING "ISRAM0 size:       1 MiB")
+set(ISRAM1_SIZE           "0x00100000" CACHE STRING "ISRAM1 size:       1 MiB")
 set(DDR4_BLK_SIZE         "0x10000000" CACHE STRING "DDR4 block size: 256 MiB")
 
 ###################################################################################################
@@ -39,7 +39,7 @@
 set(DTCM2_BASE_NS         "0x20040000" CACHE STRING "Data TCM block 2 Non-Secure base address")
 set(DTCM3_BASE_NS         "0x20060000" CACHE STRING "Data TCM block 3 Non-Secure base address")
 set(ISRAM0_BASE_NS        "0x21000000" CACHE STRING "Internal SRAM Area Non-Secure base address")
-set(ISRAM1_BASE_NS        "0x21200000" CACHE STRING "Internal SRAM Area Non-Secure base address")
+set(ISRAM1_BASE_NS        "0x21100000" CACHE STRING "Internal SRAM Area Non-Secure base address")
 set(QSPI_SRAM_BASE_NS     "0x28000000" CACHE STRING "QSPI SRAM Non-Secure base address")
 set(DDR4_BLK0_BASE_NS     "0x60000000" CACHE STRING "DDR4 block 0 Non-Secure base address")
 set(DDR4_BLK1_BASE_NS     "0x80000000" CACHE STRING "DDR4 block 1 Non-Secure base address")
@@ -53,7 +53,7 @@
 set(DTCM2_BASE_S          "0x30040000" CACHE STRING "Data TCM block 2 Secure base address")
 set(DTCM3_BASE_S          "0x30060000" CACHE STRING "Data TCM block 3 Secure base address")
 set(ISRAM0_BASE_S         "0x31000000" CACHE STRING "Internal SRAM Area Secure base address")
-set(ISRAM1_BASE_S         "0x31200000" CACHE STRING "Internal SRAM Area Secure base address")
+set(ISRAM1_BASE_S         "0x31100000" CACHE STRING "Internal SRAM Area Secure base address")
 set(DDR4_BLK0_BASE_S      "0x70000000" CACHE STRING "DDR4 block 0 Secure base address")
 set(DDR4_BLK1_BASE_S      "0x90000000" CACHE STRING "DDR4 block 1 Secure base address")
 set(DDR4_BLK2_BASE_S      "0xB0000000" CACHE STRING "DDR4 block 2 Secure base address")
diff --git a/scripts/cmake/toolchains/bare-metal-gcc.cmake b/scripts/cmake/toolchains/bare-metal-gcc.cmake
index 455f5ec..2bf5fd3 100644
--- a/scripts/cmake/toolchains/bare-metal-gcc.cmake
+++ b/scripts/cmake/toolchains/bare-metal-gcc.cmake
@@ -62,6 +62,7 @@
 add_compile_options(
     -funsigned-char
     -fno-function-sections
+    -fdata-sections
     "$<$<COMPILE_LANGUAGE:CXX>:-fno-unwind-tables;-fno-rtti;-fno-exceptions>")
 
 # Arch compile options:
@@ -88,12 +89,13 @@
     -mlittle-endian
     --specs=nosys.specs
     --stats
+    "SHELL:-Xlinker --gc-sections"
     "$<$<CONFIG:RELEASE>:--no-debug>")
 
 # Function to add a map file output for the linker to dump diagnostic information to.
 function(add_target_map_file TARGET_NAME MAP_FILE_PATH)
     target_link_options(${TARGET_NAME} PUBLIC
-        -Xlinker -Map=${MAP_FILE_PATH})
+        "SHELL:-Xlinker -Map=${MAP_FILE_PATH}")
 endfunction()
 
 # Function to add linker option to use the chosen linker script.
diff --git a/scripts/mps3/sse-300/images.txt b/scripts/mps3/sse-300/images.txt
index b00c8b7..90e59b8 100644
--- a/scripts/mps3/sse-300/images.txt
+++ b/scripts/mps3/sse-300/images.txt
@@ -1,6 +1,7 @@
 TITLE: Arm MPS3 FPGA prototyping board Images Configuration File
 
-; MCC mapping for Corstone-300 MPS3 bitfile package AN547
+; MCC mapping for Corstone-300 MPS3 bitfile package AN547 and
+; AN552
 ; +-------------+---------------+-------------------------------+
 ; | FPGA addr   | MCC addr      |  Region                       |
 ; +-------------+---------------+-------------------------------+
diff --git a/set_up_default_resources.py b/set_up_default_resources.py
index 3eff6bf..f364795 100755
--- a/set_up_default_resources.py
+++ b/set_up_default_resources.py
@@ -134,8 +134,8 @@
                                     'ethos_u_npu_id',
                                     'ethos_u_config_id'])
 
-# The default internal SRAM size for Corstone-300 implementation on MPS3
-mps3_max_sram_sz = 4 * 1024 * 1024 # 4 MiB
+# The internal SRAM size for Corstone-300 implementation on MPS3 specified by AN552
+mps3_max_sram_sz = 2 * 1024 * 1024 # 2 MiB (2 banks of 1 MiB each)
 
 
 def call_command(command: str) -> str:
diff --git a/source/application/hal/platforms/bare-metal/bsp/mem_layout/mps3-sse-300.ld b/source/application/hal/platforms/bare-metal/bsp/mem_layout/mps3-sse-300.ld
index bcbc81f..d369fa7 100644
--- a/source/application/hal/platforms/bare-metal/bsp/mem_layout/mps3-sse-300.ld
+++ b/source/application/hal/platforms/bare-metal/bsp/mem_layout/mps3-sse-300.ld
@@ -16,15 +16,15 @@
  */
 
 __STACK_SIZE = 0x00060000;
-__HEAP_SIZE  = 0x000f0000;
+__HEAP_SIZE  = 0x000C0000;
 
 /* System memory brief */
 MEMORY
 {
   ITCM  (rx)  : ORIGIN = 0x00000000, LENGTH = 0x00080000
   DTCM  (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00080000
-  BRAM  (rwx) : ORIGIN = 0x11000000, LENGTH = 0x00200000
-  SRAM  (rwx) : ORIGIN = 0x31000000, LENGTH = 0x00400000
+  BRAM  (rwx) : ORIGIN = 0x11000000, LENGTH = 0x00100000
+  SRAM  (rwx) : ORIGIN = 0x31000000, LENGTH = 0x00200000
   DDR   (rwx) : ORIGIN = 0x70000000, LENGTH = 0x02000000
 
   /* Dynamic load regions declared for use by FVP only
diff --git a/source/application/hal/platforms/bare-metal/bsp/mem_layout/mps3-sse-300.sct b/source/application/hal/platforms/bare-metal/bsp/mem_layout/mps3-sse-300.sct
index 62dbbe5..f78dc25 100644
--- a/source/application/hal/platforms/bare-metal/bsp/mem_layout/mps3-sse-300.sct
+++ b/source/application/hal/platforms/bare-metal/bsp/mem_layout/mps3-sse-300.sct
@@ -60,17 +60,18 @@
     {}
 
     ;-----------------------------------------------------
-    ; SSE-300's internal SRAM of 4MiB - reserved for
-    ; activation buffers.
+    ; FPGA internal SRAM of 2MiB - reserved for activation
+    ; buffers.
     ; This region should have 3 cycle read latency from
     ; both Cortex-M55 and Ethos-U NPU
     ;-----------------------------------------------------
-    isram.bin       0x31000000  UNINIT ALIGN 16 0x00400000
+    isram.bin       0x31000000  UNINIT ALIGN 16 0x00200000
     {
         ; Cache area (if used)
         *.o (.bss.NoInit.ethos_u_cache)
 
-        ; activation buffers a.k.a tensor arena when memory mode sram only or shared sram
+        ; activation buffers a.k.a tensor arena when
+        ; memory mode sram only or shared sram
         *.o (.bss.NoInit.activation_buf_sram)
     }
 }
@@ -103,7 +104,7 @@
 
     ;-----------------------------------------------------
     ; First 256kiB of BRAM (FPGA SRAM) used for RO data.
-    ; Note: Total BRAM size available is 2MiB.
+    ; Note: Total BRAM size available is 1MiB.
     ;-----------------------------------------------------
     bram.bin        0x11000000          ALIGN 8 0x00040000
     {
@@ -112,10 +113,10 @@
     }
 
     ;-----------------------------------------------------
-    ; 960 KiB of remaining part of the 2MiB BRAM used as
-    ; heap space. 0x000F0000 of 0x0x001C0000 available.
+    ; 768 KiB of remaining part of the 1MiB BRAM used as
+    ; heap space.
     ;-----------------------------------------------------
-    ARM_LIB_HEAP    0x11040000 EMPTY ALIGN 8    0x000F0000
+    ARM_LIB_HEAP    0x11040000 EMPTY ALIGN 8    0x000C0000
     {}
 
     ;-----------------------------------------------------
diff --git a/source/application/hal/platforms/bare-metal/bsp/mem_layout/simple_platform.ld b/source/application/hal/platforms/bare-metal/bsp/mem_layout/simple_platform.ld
index e5b6bd9..82cb18e 100644
--- a/source/application/hal/platforms/bare-metal/bsp/mem_layout/simple_platform.ld
+++ b/source/application/hal/platforms/bare-metal/bsp/mem_layout/simple_platform.ld
@@ -16,15 +16,15 @@
  */
 
 __STACK_SIZE = 0x00060000;
-__HEAP_SIZE  = 0x000f0000;
+__HEAP_SIZE  = 0x000C0000;
 
 /* System memory brief */
 MEMORY
 {
   ITCM  (rx)  : ORIGIN = 0x00000000, LENGTH = 0x00080000
   DTCM  (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00080000
-  BRAM  (rwx) : ORIGIN = 0x11000000, LENGTH = 0x00200000
-  SRAM  (rwx) : ORIGIN = 0x31000000, LENGTH = 0x00400000
+  BRAM  (rwx) : ORIGIN = 0x11000000, LENGTH = 0x00100000
+  SRAM  (rwx) : ORIGIN = 0x31000000, LENGTH = 0x00200000
   DDR   (rwx) : ORIGIN = 0x70000000, LENGTH = 0x02000000
 }
 
diff --git a/source/application/hal/platforms/bare-metal/bsp/mem_layout/simple_platform.sct b/source/application/hal/platforms/bare-metal/bsp/mem_layout/simple_platform.sct
index e84d81e..5825d47 100644
--- a/source/application/hal/platforms/bare-metal/bsp/mem_layout/simple_platform.sct
+++ b/source/application/hal/platforms/bare-metal/bsp/mem_layout/simple_platform.sct
@@ -18,8 +18,9 @@
 ; *************************************************************
 ; Please see docs/sections/appendix.md for memory mapping information.
 ;
-; Note: Ethos-U NPU can access BRAM, internal SRAM and the DDR sections => activation buffers and
-;       the model should only be placed in those regions.
+; Note: Ethos-U NPU can access BRAM, internal SRAM and the DDR
+;       sections => activation buffers and the model should only
+;       be placed in those regions.
 ;
 ;---------------------------------------------------------
 ; First load region (ITCM)
@@ -60,17 +61,18 @@
     {}
 
     ;-----------------------------------------------------
-    ; SSE-300's internal SRAM of 4MiB - reserved for
+    ; SSE-300's internal SRAM of 2MiB - reserved for
     ; activation buffers.
     ; This region should have 3 cycle read latency from
     ; both Cortex-M55 and Ethos-U NPU
     ;-----------------------------------------------------
-    isram.bin       0x31000000  UNINIT ALIGN 16 0x00400000
+    isram.bin       0x31000000  UNINIT ALIGN 16 0x00200000
     {
         ; Cache area (if used)
         *.o (.bss.NoInit.ethos_u_cache)
 
-        ; activation buffers a.k.a tensor arena when memory mode sram only or shared sram
+        ; activation buffers a.k.a tensor arena when
+        ; memory mode sram only or shared sram
         *.o (.bss.NoInit.activation_buf_sram)
     }
 }
@@ -103,7 +105,7 @@
 
     ;-----------------------------------------------------
     ; First 256kiB of BRAM (FPGA SRAM) used for RO data.
-    ; Note: Total BRAM size available is 2MiB.
+    ; Note: Total BRAM size available is 1MiB.
     ;-----------------------------------------------------
     bram.bin        0x11000000          ALIGN 8 0x00040000
     {
@@ -112,9 +114,9 @@
     }
 
     ;-----------------------------------------------------
-    ; 960 KiB of remaining part of the 2MiB BRAM used as
-    ; heap space. 0x000F0000 of 0x0x001C0000 available.
+    ; 768 KiB of remaining part of the 1MiB BRAM used as
+    ; heap space.
     ;-----------------------------------------------------
-    ARM_LIB_HEAP    0x11040000 EMPTY ALIGN 8    0x000F0000
+    ARM_LIB_HEAP    0x11040000 EMPTY ALIGN 8    0x000C0000
     {}
 }
diff --git a/source/use_case/asr/usecase.cmake b/source/use_case/asr/usecase.cmake
index 89a131e..50e7e26 100644
--- a/source/use_case/asr/usecase.cmake
+++ b/source/use_case/asr/usecase.cmake
@@ -71,7 +71,7 @@
 
 
 USER_OPTION(${use_case}_ACTIVATION_BUF_SZ "Activation buffer size for the chosen model"
-    0x00400000
+    0x00200000
     STRING)
 
 if (ETHOS_U_NPU_ENABLED)
diff --git a/source/use_case/kws_asr/usecase.cmake b/source/use_case/kws_asr/usecase.cmake
index 5b179c6..d8629b6 100644
--- a/source/use_case/kws_asr/usecase.cmake
+++ b/source/use_case/kws_asr/usecase.cmake
@@ -55,7 +55,7 @@
 
 
 USER_OPTION(${use_case}_ACTIVATION_BUF_SZ "Activation buffer size for the chosen model"
-    0x00400000
+    0x00200000
     STRING)
 
 USER_OPTION(${use_case}_MODEL_SCORE_THRESHOLD_KWS "Specify the score threshold [0.0, 1.0) that must be applied to the KWS results for a label to be deemed valid."
diff --git a/source/use_case/noise_reduction/src/RNNoiseProcess.cc b/source/use_case/noise_reduction/src/RNNoiseProcess.cc
index 54b99f8..d5b577e 100644
--- a/source/use_case/noise_reduction/src/RNNoiseProcess.cc
+++ b/source/use_case/noise_reduction/src/RNNoiseProcess.cc
@@ -868,7 +868,7 @@
     }
 
     constexpr uint32_t numFFt = 2 * FRAME_SIZE;
-    static_assert(numFFt != 0);
+    static_assert(numFFt != 0, "numFFt cannot be 0!");
 
     vec1D32F fftOut = vec1D32F(x.size(), 0);
     math::MathUtils::FftF32(x,fftOut, m_fftInstCmplx);