diff --git a/source/application/hal/platforms/bare-metal/bsp/mem_layout/mps3-sse-300.sct b/source/application/hal/platforms/bare-metal/bsp/mem_layout/mps3-sse-300.sct
index 62dbbe5..f78dc25 100644
--- a/source/application/hal/platforms/bare-metal/bsp/mem_layout/mps3-sse-300.sct
+++ b/source/application/hal/platforms/bare-metal/bsp/mem_layout/mps3-sse-300.sct
@@ -60,17 +60,18 @@
     {}
 
     ;-----------------------------------------------------
-    ; SSE-300's internal SRAM of 4MiB - reserved for
-    ; activation buffers.
+    ; FPGA internal SRAM of 2MiB - reserved for activation
+    ; buffers.
     ; This region should have 3 cycle read latency from
     ; both Cortex-M55 and Ethos-U NPU
     ;-----------------------------------------------------
-    isram.bin       0x31000000  UNINIT ALIGN 16 0x00400000
+    isram.bin       0x31000000  UNINIT ALIGN 16 0x00200000
     {
         ; Cache area (if used)
         *.o (.bss.NoInit.ethos_u_cache)
 
-        ; activation buffers a.k.a tensor arena when memory mode sram only or shared sram
+        ; activation buffers a.k.a tensor arena when
+        ; memory mode sram only or shared sram
         *.o (.bss.NoInit.activation_buf_sram)
     }
 }
@@ -103,7 +104,7 @@
 
     ;-----------------------------------------------------
     ; First 256kiB of BRAM (FPGA SRAM) used for RO data.
-    ; Note: Total BRAM size available is 2MiB.
+    ; Note: Total BRAM size available is 1MiB.
     ;-----------------------------------------------------
     bram.bin        0x11000000          ALIGN 8 0x00040000
     {
@@ -112,10 +113,10 @@
     }
 
     ;-----------------------------------------------------
-    ; 960 KiB of remaining part of the 2MiB BRAM used as
-    ; heap space. 0x000F0000 of 0x0x001C0000 available.
+    ; 768 KiB of remaining part of the 1MiB BRAM used as
+    ; heap space.
     ;-----------------------------------------------------
-    ARM_LIB_HEAP    0x11040000 EMPTY ALIGN 8    0x000F0000
+    ARM_LIB_HEAP    0x11040000 EMPTY ALIGN 8    0x000C0000
     {}
 
     ;-----------------------------------------------------