diff --git a/source/application/hal/platforms/bare-metal/bsp/mem_layout/mps3-sse-300.ld b/source/application/hal/platforms/bare-metal/bsp/mem_layout/mps3-sse-300.ld
index bcbc81f..d369fa7 100644
--- a/source/application/hal/platforms/bare-metal/bsp/mem_layout/mps3-sse-300.ld
+++ b/source/application/hal/platforms/bare-metal/bsp/mem_layout/mps3-sse-300.ld
@@ -16,15 +16,15 @@
  */
 
 __STACK_SIZE = 0x00060000;
-__HEAP_SIZE  = 0x000f0000;
+__HEAP_SIZE  = 0x000C0000;
 
 /* System memory brief */
 MEMORY
 {
   ITCM  (rx)  : ORIGIN = 0x00000000, LENGTH = 0x00080000
   DTCM  (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00080000
-  BRAM  (rwx) : ORIGIN = 0x11000000, LENGTH = 0x00200000
-  SRAM  (rwx) : ORIGIN = 0x31000000, LENGTH = 0x00400000
+  BRAM  (rwx) : ORIGIN = 0x11000000, LENGTH = 0x00100000
+  SRAM  (rwx) : ORIGIN = 0x31000000, LENGTH = 0x00200000
   DDR   (rwx) : ORIGIN = 0x70000000, LENGTH = 0x02000000
 
   /* Dynamic load regions declared for use by FVP only
diff --git a/source/application/hal/platforms/bare-metal/bsp/mem_layout/mps3-sse-300.sct b/source/application/hal/platforms/bare-metal/bsp/mem_layout/mps3-sse-300.sct
index 62dbbe5..f78dc25 100644
--- a/source/application/hal/platforms/bare-metal/bsp/mem_layout/mps3-sse-300.sct
+++ b/source/application/hal/platforms/bare-metal/bsp/mem_layout/mps3-sse-300.sct
@@ -60,17 +60,18 @@
     {}
 
     ;-----------------------------------------------------
-    ; SSE-300's internal SRAM of 4MiB - reserved for
-    ; activation buffers.
+    ; FPGA internal SRAM of 2MiB - reserved for activation
+    ; buffers.
     ; This region should have 3 cycle read latency from
     ; both Cortex-M55 and Ethos-U NPU
     ;-----------------------------------------------------
-    isram.bin       0x31000000  UNINIT ALIGN 16 0x00400000
+    isram.bin       0x31000000  UNINIT ALIGN 16 0x00200000
     {
         ; Cache area (if used)
         *.o (.bss.NoInit.ethos_u_cache)
 
-        ; activation buffers a.k.a tensor arena when memory mode sram only or shared sram
+        ; activation buffers a.k.a tensor arena when
+        ; memory mode sram only or shared sram
         *.o (.bss.NoInit.activation_buf_sram)
     }
 }
@@ -103,7 +104,7 @@
 
     ;-----------------------------------------------------
     ; First 256kiB of BRAM (FPGA SRAM) used for RO data.
-    ; Note: Total BRAM size available is 2MiB.
+    ; Note: Total BRAM size available is 1MiB.
     ;-----------------------------------------------------
     bram.bin        0x11000000          ALIGN 8 0x00040000
     {
@@ -112,10 +113,10 @@
     }
 
     ;-----------------------------------------------------
-    ; 960 KiB of remaining part of the 2MiB BRAM used as
-    ; heap space. 0x000F0000 of 0x0x001C0000 available.
+    ; 768 KiB of remaining part of the 1MiB BRAM used as
+    ; heap space.
     ;-----------------------------------------------------
-    ARM_LIB_HEAP    0x11040000 EMPTY ALIGN 8    0x000F0000
+    ARM_LIB_HEAP    0x11040000 EMPTY ALIGN 8    0x000C0000
     {}
 
     ;-----------------------------------------------------
diff --git a/source/application/hal/platforms/bare-metal/bsp/mem_layout/simple_platform.ld b/source/application/hal/platforms/bare-metal/bsp/mem_layout/simple_platform.ld
index e5b6bd9..82cb18e 100644
--- a/source/application/hal/platforms/bare-metal/bsp/mem_layout/simple_platform.ld
+++ b/source/application/hal/platforms/bare-metal/bsp/mem_layout/simple_platform.ld
@@ -16,15 +16,15 @@
  */
 
 __STACK_SIZE = 0x00060000;
-__HEAP_SIZE  = 0x000f0000;
+__HEAP_SIZE  = 0x000C0000;
 
 /* System memory brief */
 MEMORY
 {
   ITCM  (rx)  : ORIGIN = 0x00000000, LENGTH = 0x00080000
   DTCM  (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00080000
-  BRAM  (rwx) : ORIGIN = 0x11000000, LENGTH = 0x00200000
-  SRAM  (rwx) : ORIGIN = 0x31000000, LENGTH = 0x00400000
+  BRAM  (rwx) : ORIGIN = 0x11000000, LENGTH = 0x00100000
+  SRAM  (rwx) : ORIGIN = 0x31000000, LENGTH = 0x00200000
   DDR   (rwx) : ORIGIN = 0x70000000, LENGTH = 0x02000000
 }
 
diff --git a/source/application/hal/platforms/bare-metal/bsp/mem_layout/simple_platform.sct b/source/application/hal/platforms/bare-metal/bsp/mem_layout/simple_platform.sct
index e84d81e..5825d47 100644
--- a/source/application/hal/platforms/bare-metal/bsp/mem_layout/simple_platform.sct
+++ b/source/application/hal/platforms/bare-metal/bsp/mem_layout/simple_platform.sct
@@ -18,8 +18,9 @@
 ; *************************************************************
 ; Please see docs/sections/appendix.md for memory mapping information.
 ;
-; Note: Ethos-U NPU can access BRAM, internal SRAM and the DDR sections => activation buffers and
-;       the model should only be placed in those regions.
+; Note: Ethos-U NPU can access BRAM, internal SRAM and the DDR
+;       sections => activation buffers and the model should only
+;       be placed in those regions.
 ;
 ;---------------------------------------------------------
 ; First load region (ITCM)
@@ -60,17 +61,18 @@
     {}
 
     ;-----------------------------------------------------
-    ; SSE-300's internal SRAM of 4MiB - reserved for
+    ; SSE-300's internal SRAM of 2MiB - reserved for
     ; activation buffers.
     ; This region should have 3 cycle read latency from
     ; both Cortex-M55 and Ethos-U NPU
     ;-----------------------------------------------------
-    isram.bin       0x31000000  UNINIT ALIGN 16 0x00400000
+    isram.bin       0x31000000  UNINIT ALIGN 16 0x00200000
     {
         ; Cache area (if used)
         *.o (.bss.NoInit.ethos_u_cache)
 
-        ; activation buffers a.k.a tensor arena when memory mode sram only or shared sram
+        ; activation buffers a.k.a tensor arena when
+        ; memory mode sram only or shared sram
         *.o (.bss.NoInit.activation_buf_sram)
     }
 }
@@ -103,7 +105,7 @@
 
     ;-----------------------------------------------------
     ; First 256kiB of BRAM (FPGA SRAM) used for RO data.
-    ; Note: Total BRAM size available is 2MiB.
+    ; Note: Total BRAM size available is 1MiB.
     ;-----------------------------------------------------
     bram.bin        0x11000000          ALIGN 8 0x00040000
     {
@@ -112,9 +114,9 @@
     }
 
     ;-----------------------------------------------------
-    ; 960 KiB of remaining part of the 2MiB BRAM used as
-    ; heap space. 0x000F0000 of 0x0x001C0000 available.
+    ; 768 KiB of remaining part of the 1MiB BRAM used as
+    ; heap space.
     ;-----------------------------------------------------
-    ARM_LIB_HEAP    0x11040000 EMPTY ALIGN 8    0x000F0000
+    ARM_LIB_HEAP    0x11040000 EMPTY ALIGN 8    0x000C0000
     {}
 }
diff --git a/source/use_case/asr/usecase.cmake b/source/use_case/asr/usecase.cmake
index 89a131e..50e7e26 100644
--- a/source/use_case/asr/usecase.cmake
+++ b/source/use_case/asr/usecase.cmake
@@ -71,7 +71,7 @@
 
 
 USER_OPTION(${use_case}_ACTIVATION_BUF_SZ "Activation buffer size for the chosen model"
-    0x00400000
+    0x00200000
     STRING)
 
 if (ETHOS_U_NPU_ENABLED)
diff --git a/source/use_case/kws_asr/usecase.cmake b/source/use_case/kws_asr/usecase.cmake
index 5b179c6..d8629b6 100644
--- a/source/use_case/kws_asr/usecase.cmake
+++ b/source/use_case/kws_asr/usecase.cmake
@@ -55,7 +55,7 @@
 
 
 USER_OPTION(${use_case}_ACTIVATION_BUF_SZ "Activation buffer size for the chosen model"
-    0x00400000
+    0x00200000
     STRING)
 
 USER_OPTION(${use_case}_MODEL_SCORE_THRESHOLD_KWS "Specify the score threshold [0.0, 1.0) that must be applied to the KWS results for a label to be deemed valid."
diff --git a/source/use_case/noise_reduction/src/RNNoiseProcess.cc b/source/use_case/noise_reduction/src/RNNoiseProcess.cc
index 54b99f8..d5b577e 100644
--- a/source/use_case/noise_reduction/src/RNNoiseProcess.cc
+++ b/source/use_case/noise_reduction/src/RNNoiseProcess.cc
@@ -868,7 +868,7 @@
     }
 
     constexpr uint32_t numFFt = 2 * FRAME_SIZE;
-    static_assert(numFFt != 0);
+    static_assert(numFFt != 0, "numFFt cannot be 0!");
 
     vec1D32F fftOut = vec1D32F(x.size(), 0);
     math::MathUtils::FftF32(x,fftOut, m_fftInstCmplx);