diff --git a/scripts/cmake/platforms/simple_platform/simple_platform.sct b/scripts/cmake/platforms/simple_platform/simple_platform.sct
index 5825d47..af639d6 100644
--- a/scripts/cmake/platforms/simple_platform/simple_platform.sct
+++ b/scripts/cmake/platforms/simple_platform/simple_platform.sct
@@ -16,11 +16,12 @@
 ; *************************************************************
 ; ***       Scatter-Loading Description File                ***
 ; *************************************************************
-; Please see docs/sections/appendix.md for memory mapping information.
+; Please see docs/sections/appendix.md for memory mapping
+; information.
 ;
 ; Note: Ethos-U NPU can access BRAM, internal SRAM and the DDR
-;       sections => activation buffers and the model should only
-;       be placed in those regions.
+;       sections => activation buffers and the model should
+;       only be placed in those regions.
 ;
 ;---------------------------------------------------------
 ; First load region (ITCM)
@@ -41,28 +42,28 @@
     }
 
     ;-----------------------------------------------------
-    ; 128kiB of 512kiB DTCM is used for any other RW or ZI
+    ; 384kiB of 512kiB DTCM is used for any other RW or ZI
     ; data. Note: this region is internal to the Cortex-M
     ; CPU.
     ;-----------------------------------------------------
-    dtcm.bin        0x20000000                  0x00020000
+    dtcm.bin        0x20000000                  0x00060000
     {
         ; Any R/W and/or zero initialised data
         .ANY(+RW +ZI)
     }
 
     ;-----------------------------------------------------
-    ; 384kiB of stack space within the DTCM region. See
+    ; 32 kiB of stack space within the DTCM region. See
     ; `dtcm.bin` for the first section. Note: by virtue of
     ; being part of DTCM, this region is only accessible
-    ; from Cortex-M55.
+    ; from Cortex-M55. We use the last DTCM bank
     ;-----------------------------------------------------
-    ARM_LIB_STACK   0x20020000 EMPTY ALIGN 8    0x00060000
+    ARM_LIB_STACK   0x20060000 EMPTY ALIGN 8    0x00008000
     {}
 
     ;-----------------------------------------------------
-    ; SSE-300's internal SRAM of 2MiB - reserved for
-    ; activation buffers.
+    ; FPGA internal SRAM of 2MiB - reserved for activation
+    ; buffers.
     ; This region should have 3 cycle read latency from
     ; both Cortex-M55 and Ethos-U NPU
     ;-----------------------------------------------------