diff --git a/docs/sections/building.md b/docs/sections/building.md
index 301d945..699667b 100644
--- a/docs/sections/building.md
+++ b/docs/sections/building.md
@@ -911,16 +911,7 @@
 These headers are generated using Python templates, that are located in `scripts/py/templates/*.template`:
 
 ```tree
-scripts/
-├── cmake
-│   ├── ...
-│   ├── subsystem-profiles
-│   │   └── corstone-sse-300.cmake
-│   ├── templates
-│   │   ├── mem_regions.h.template
-│   │   ├── peripheral_irqs.h.template
-│   │   └── peripheral_memmap.h.template
-│   └── ...
+scripts
 └── py
     ├── <generation scripts>
     ├── requirements.txt
@@ -1000,21 +991,10 @@
 > )
 > ```
 
-In addition to input file conversions, the correct platform, or system, profile is selected, in
-`scripts/cmake/subsystem-profiles/*.cmake`. It is based on `TARGET_SUBSYSTEM` build option and the variables set are
-used to generate memory region sizes, base addresses and IRQ numbers, respectively used to generate the `mem_region.h`,
-`peripheral_irqs.h`, and `peripheral_memmap.h` headers.
-
-Templates from `scripts/cmake/templates/*.template` are used to generate the header files.
-
 After the build, the files generated in the build folder are:
 
 ```tree
 build/generated/
-├── bsp
-│   ├── mem_regions.h
-│   ├── peripheral_irqs.h
-│   └── peripheral_memmap.h
 ├── <use_case_name1>
 │   ├── include
 │   │   ├── InputFiles.hpp
diff --git a/docs/sections/memory_considerations.md b/docs/sections/memory_considerations.md
index b67bbc5..b8d1c25 100644
--- a/docs/sections/memory_considerations.md
+++ b/docs/sections/memory_considerations.md
@@ -35,24 +35,18 @@
 
 ## Memory available on the target platform
 
-Embedded target platforms supported have a description in the form of CMake files. These files
-have definitions that describe the memory regions and the peripheral base addresses.
+All embedded target platforms supported have platform specific header files that contain memory and other definitions.
+For example, MPS3 target header files can be found under the HAL sources' platform subdirectory and contains the
+following definitions:
 
-See the example for Arm® *Corstone™-300* description file [corstone-sse-300.cmake](../../scripts/cmake/subsystem-profiles/corstone-sse-300.cmake). For the discussion on this page, it is useful to note the following definitions:
-
-```cmake
-set(ISRAM0_SIZE           "0x00100000" CACHE STRING "ISRAM0 size:       1 MiB")
-set(ISRAM1_SIZE           "0x00100000" CACHE STRING "ISRAM1 size:       1 MiB")
-...
-# SRAM size reserved for activation buffers
-math(EXPR ACTIVATION_BUF_SRAM_SZ "${ISRAM0_SIZE} + ${ISRAM1_SIZE}" OUTPUT_FORMAT HEXADECIMAL)
+```c
+#define ISRAM0_SIZE           (0x00100000)     /* ISRAM0 size */
+#define ISRAM1_SIZE           (0x00100000)     /* ISRAM1 size */
 ```
 
-This will set `ACTIVATION_BUF_SRAM_SZ` to be **2 MiB** for Arm® *Corstone™-300* target platform.
-As mentioned in the comments within the file, this size is directly linked to the size mentioned
-in the linker scripts, and therefore, it should not be changed without corresponding changes
-in the linker script too. For example, a snippet from the scatter file for Arm® *Corstone™-300*
-shows:
+As these SRAM banks are being used for holding the tensor arena, the total size should be limited to **2 MiB** for
+Arm® *Corstone™-300* target platform. This size is directly linked to the size mentioned in the linker scripts. See
+snippet from the scatter file for Arm® *Corstone™-300* below:
 
 ```log
 ;-----------------------------------------------------
@@ -67,8 +61,15 @@
 }
 ```
 
-If the usable size of the internal SRAM was to be increased/decreased, the change should be
-made in both the linker script as well as the `corstone-300.cmake` definition.
+When not using the Arm Ethos-U NPU at all or using only Arm Ethos-U55 in `Shared_Sram` or `Sram_Only` modes, the limit
+in the linker script (and the platform memory definition header file) is applicable.
+
+However, for `Dedicated_Sram` memory mode (applies only for Arm Ethos-U65), the tensor arena will not sit in this
+SRAM space and therefore, the use case can be allowed to have larger `${use_case}_ACTIVATION_BUF_SZ`. See next section
+for more details on this.
+
+For custom requirements (like always placing the tensor arena in DDR), the user can change the `BufAttributes.hpp` file
+along with the linker scripts.
 
 ### Parameters linked to SRAM size definitions
 
@@ -89,8 +90,8 @@
 
 - In every `usecase.cmake` file (present within each use case's source directory), there is
   a parameter called `${use_case}_ACTIVATION_BUF_SZ` set to a fixed value by default. This
-  default value should be less than the `ACTIVATION_BUF_SRAM_SZ` if the activation buffer needs
-  to be reserved in the target platform's SRAM region.
+  default value should be less than, or equal to, the available SRAM on the target platform if
+  the activation buffer needs to be reserved in the target platform's SRAM region.
 
 ## Understanding memory usage from Vela output
 
@@ -185,13 +186,8 @@
 Every use-case application has a corresponding `<use_case_name>_ACTIVATION_BUF_SZ` parameter that governs the maximum
 available size of the `activation buffer` for that particular use-case.
 
-The linker script is set up to place this memory region in SRAM for *Ethos-U55* and in flash for *Ethos-U65*.
-Every target platform has a profile definition in the form of a `CMake` file.
-
-For further information and an example, please refer to: [Corstone-300 profile](../../scripts/cmake/subsystem-profiles/corstone-sse-300.cmake).
-
-The parameter `ACTIVATION_BUF_SRAM_SZ` defines the maximum SRAM size available for the platform. This is propagated
-through the build system.
+The linker script is set up to place this memory region in SRAM for *Ethos-U55* or in flash for *Ethos-U65* (following
+the default memory modes of `Shared_Sram` and `Dedicated_Sram` respectively).
 
 The neural network model is always placed in the flash region (even in case of `Sram_Only` memory mode as mentioned earlier).
 
diff --git a/docs/use_cases/inference_runner.md b/docs/use_cases/inference_runner.md
index 1082c5c..8511fe1 100644
--- a/docs/use_cases/inference_runner.md
+++ b/docs/use_cases/inference_runner.md
@@ -291,9 +291,7 @@
 ```
 
 will build the application that will expect the neural network model and the IFM to be loaded into
-specific addresses. These addresses are defined in
-[corstone-sse-300.cmake](../../scripts/cmake/subsystem-profiles/corstone-sse-300.cmake) for the MPS3
-target.
+specific addresses. The default values for these addresses are defined in the use-case CMake file.
 
 ### Running the FVP with dynamic model loading
 
diff --git a/source/application/tensorflow-lite-micro/include/BufAttributes.hpp b/source/application/tensorflow-lite-micro/include/BufAttributes.hpp
index a3b5890..0146443 100644
--- a/source/application/tensorflow-lite-micro/include/BufAttributes.hpp
+++ b/source/application/tensorflow-lite-micro/include/BufAttributes.hpp
@@ -50,11 +50,6 @@
     #define ACTIVATION_BUF_SZ       0x00200000
 #endif  /* ACTIVATION_BUF_SZ */
 
-#ifndef ACTIVATION_BUF_SRAM_SZ
-    #warning  "ACTIVATION_BUF_SRAM_SZ needs to be defined. Using default value = 0"
-    #define ACTIVATION_BUF_SRAM_SZ  0x00000000
-#endif /* ACTIVATION_BUF_SRAM_SZ */
-
 /* IFM section name. */
 #define IFM_BUF_SECTION             section("ifm")
 
@@ -74,4 +69,4 @@
 
 #endif /* HAVE_ATTRIBUTE(aligned) || (defined(__GNUC__) && !defined(__clang__)) */
 
-#endif /* BUF_ATTRIBUTES_HPP */
\ No newline at end of file
+#endif /* BUF_ATTRIBUTES_HPP */
diff --git a/source/hal/source/components/npu/CMakeLists.txt b/source/hal/source/components/npu/CMakeLists.txt
index 729a297..c53dd02 100644
--- a/source/hal/source/components/npu/CMakeLists.txt
+++ b/source/hal/source/components/npu/CMakeLists.txt
@@ -33,6 +33,12 @@
 # For the driver, we need to provide the CMSIS_PATH variable
 set(CMSIS_PATH ${CMSIS_SRC_PATH} CACHE PATH "Path to CMSIS directory")
 
+# Definitions that will be set.
+set(ETHOS_U_BASE_ADDR    "0x58102000"    CACHE STRING "Ethos-U NPU base address")
+set(ETHOS_U_IRQN         "56"            CACHE STRING "Ethos-U NPU Interrupt")
+set(ETHOS_U_SEC_ENABLED  "1"             CACHE STRING "Ethos-U NPU Security enable")
+set(ETHOS_U_PRIV_ENABLED "1"             CACHE STRING "Ethos-U NPU Privilege enable")
+
 # Driver needs to know what MAC configuration to build for.
 if(ETHOS_U_NPU_CONFIG_ID MATCHES "^[A-Z]([0-9]+$)")
     set(ETHOSU_MACS ${CMAKE_MATCH_1})
@@ -145,7 +151,11 @@
 target_compile_definitions(${ETHOS_U_NPU_COMPONENT}
     PUBLIC
     ARM_NPU
-    ${ETHOS_U_NPU_MEMORY_MODE_FLAG})
+    ${ETHOS_U_NPU_MEMORY_MODE_FLAG}
+    ETHOS_U_BASE_ADDR=${ETHOS_U_BASE_ADDR}
+    ETHOS_U_IRQN=${ETHOS_U_IRQN}
+    ETHOS_U_SEC_ENABLED=${ETHOS_U_SEC_ENABLED}
+    ETHOS_U_PRIV_ENABLED=${ETHOS_U_PRIV_ENABLED})
 
 # Display status
 message(STATUS "CMAKE_CURRENT_SOURCE_DIR: " ${CMAKE_CURRENT_SOURCE_DIR})
diff --git a/source/hal/source/components/npu/ethosu_npu_init.c b/source/hal/source/components/npu/ethosu_npu_init.c
index 9ccd887..e24ddd9 100644
--- a/source/hal/source/components/npu/ethosu_npu_init.c
+++ b/source/hal/source/components/npu/ethosu_npu_init.c
@@ -18,8 +18,6 @@
 #include "ethosu_npu_init.h"
 
 #include "RTE_Components.h"         /* For CPU related defintiions */
-#include "peripheral_memmap.h"      /* Peripheral memory map definitions. */
-#include "peripheral_irqs.h"        /* IRQ numbers for this platform. */
 #include "log_macros.h"             /* Logging functions */
 
 #include "ethosu_mem_config.h"      /* Arm Ethos-U memory config */
@@ -62,7 +60,7 @@
  **/
 static void arm_ethosu_npu_irq_init(void)
 {
-    const IRQn_Type ethosu_irqnum = (IRQn_Type)EthosU_IRQn;
+    const IRQn_Type ethosu_irqnum = (IRQn_Type)ETHOS_U_IRQN;
 
     /* Register the EthosU IRQ handler in our vector table.
      * Note, this handler comes from the EthosU driver */
@@ -83,15 +81,15 @@
     arm_ethosu_npu_irq_init();
 
     /* Initialise Ethos-U device */
-    const void *ethosu_base_address = (void *)(SEC_ETHOS_U_NPU_BASE);
+    const void *ethosu_base_address = (void *)(ETHOS_U_BASE_ADDR);
 
     if (0 != (err = ethosu_init(
                   &ethosu_drv,            /* Ethos-U driver device pointer */
                   ethosu_base_address,    /* Ethos-U NPU's base address. */
                   get_cache_arena(),      /* Pointer to fast mem area - NULL for U55. */
                   get_cache_arena_size(), /* Fast mem region size. */
-                  1,                      /* Security enable. */
-                  1)))                    /* Privilege enable. */
+                  ETHOS_U_SEC_ENABLED,    /* Security enable. */
+                  ETHOS_U_PRIV_ENABLED))) /* Privilege enable. */
     {
         printf_err("failed to initialise Ethos-U device\n");
         return err;
diff --git a/source/hal/source/components/npu_ta/CMakeLists.txt b/source/hal/source/components/npu_ta/CMakeLists.txt
index fdda723..6f7dac5 100644
--- a/source/hal/source/components/npu_ta/CMakeLists.txt
+++ b/source/hal/source/components/npu_ta/CMakeLists.txt
@@ -31,6 +31,11 @@
     LANGUAGES       C CXX ASM)
 
 # Checks
+## Source generated Source path check
+if (NOT DEFINED SOURCE_GEN_DIR)
+    set(SOURCE_GEN_DIR ${CMAKE_BINARY_DIR}/generated/ta)
+endif()
+
 ## If a TA config file is provided, we generate a settings file
 if (DEFINED TA_CONFIG_FILE)
     include(${TA_CONFIG_FILE})
diff --git a/source/hal/source/platform/mps3/CMakeLists.txt b/source/hal/source/platform/mps3/CMakeLists.txt
index 8bd51dc..31cd004 100644
--- a/source/hal/source/platform/mps3/CMakeLists.txt
+++ b/source/hal/source/platform/mps3/CMakeLists.txt
@@ -30,39 +30,19 @@
     message(FATAL_ERROR "No ${PLATFORM_DRIVERS_TARGET} support for this target.")
 endif()
 
-# 2. Set the platform cmake descriptor file
-if (NOT DEFINED PLATFORM_CMAKE_DESCRIPTOR_FILE)
-    set(PLATFORM_CMAKE_DESCRIPTOR_FILE
-        cmake/subsystem-profiles/${TARGET_SUBSYSTEM}.cmake
-        CACHE PATH
-        "Platform's CMake descriptor file path")
-endif()
-
-## Include the platform cmake descriptor file
-include(${PLATFORM_CMAKE_DESCRIPTOR_FILE})
-
 # Define target specific base addresses here (before adding the components)
 if (TARGET_SUBSYSTEM STREQUAL sse-300)
     set(UART0_BASE          "0x49303000"    CACHE STRING "UART base address")
     set(UART0_BAUDRATE      "115200"        CACHE STRING "UART baudrate")
     set(SYSTEM_CORE_CLOCK   "25000000"      CACHE STRING "System peripheral clock (Hz)")
     set(CLCD_CONFIG_BASE    "0x4930A000"    CACHE STRING "LCD configuration base address")
+    set(ETHOS_U_BASE_ADDR   "0x58102000"    CACHE STRING "Ethos-U NPU base address")
+    set(ETHOS_U_IRQN        "56"            CACHE STRING "Ethos-U55 Interrupt")
+    set(ETHOS_U_SEC_ENABLED  "1"            CACHE STRING "Ethos-U NPU Security enable")
+    set(ETHOS_U_PRIV_ENABLED "1"            CACHE STRING "Ethos-U NPU Privilege enable")
 endif()
 
-# 3. Generate sources:
-if (NOT DEFINED SOURCE_GEN_DIR)
-    set(SOURCE_GEN_DIR ${CMAKE_BINARY_DIR}/generated/bsp)
-endif()
-
-set(MEM_PROFILE_TEMPLATE ${CMAKE_CURRENT_SOURCE_DIR}/cmake/templates/peripheral_memmap.h.template)
-set(IRQ_PROFILE_TEMPLATE ${CMAKE_CURRENT_SOURCE_DIR}/cmake/templates/peripheral_irqs.h.template)
-set(MEM_REGIONS_TEMPLATE ${CMAKE_CURRENT_SOURCE_DIR}/cmake/templates/mem_regions.h.template)
-
-configure_file("${MEM_PROFILE_TEMPLATE}" "${SOURCE_GEN_DIR}/peripheral_memmap.h")
-configure_file("${IRQ_PROFILE_TEMPLATE}" "${SOURCE_GEN_DIR}/peripheral_irqs.h")
-configure_file("${MEM_REGIONS_TEMPLATE}" "${SOURCE_GEN_DIR}/mem_regions.h")
-
-# Create static library
+# 2. Create static library
 add_library(${PLATFORM_DRIVERS_TARGET} STATIC)
 
 ## Include directories - private
@@ -74,7 +54,7 @@
 target_include_directories(${PLATFORM_DRIVERS_TARGET}
     PUBLIC
     include
-    ${SOURCE_GEN_DIR})
+    include/${TARGET_SUBSYSTEM})
 
 ## Platform sources
 target_sources(${PLATFORM_DRIVERS_TARGET}
@@ -82,11 +62,6 @@
     source/timer_mps3.c
     source/platform_drivers.c)
 
-## Compile definitions
-target_compile_definitions(${PLATFORM_DRIVERS_TARGET}
-    PUBLIC
-    ACTIVATION_BUF_SRAM_SZ=${ACTIVATION_BUF_SRAM_SZ})
-
 ## Directory for additional components required by MPS3:
 if (NOT DEFINED COMPONENTS_DIR)
     set(COMPONENTS_DIR ${CMAKE_CURRENT_SOURCE_DIR}/../../components)
@@ -130,7 +105,7 @@
 
 endif()
 
-# 5. Display status:
+# 3. Display status:
 message(STATUS "CMAKE_CURRENT_SOURCE_DIR: " ${CMAKE_CURRENT_SOURCE_DIR})
 message(STATUS "*******************************************************")
 message(STATUS "Library                                : " ${PLATFORM_DRIVERS_TARGET})
diff --git a/source/hal/source/platform/mps3/cmake/subsystem-profiles/sse-300.cmake b/source/hal/source/platform/mps3/cmake/subsystem-profiles/sse-300.cmake
deleted file mode 100644
index eec6fde..0000000
--- a/source/hal/source/platform/mps3/cmake/subsystem-profiles/sse-300.cmake
+++ /dev/null
@@ -1,319 +0,0 @@
-#----------------------------------------------------------------------------
-#  Copyright (c) 2021 Arm Limited. All rights reserved.
-#  SPDX-License-Identifier: Apache-2.0
-#
-#  Licensed under the Apache License, Version 2.0 (the "License");
-#  you may not use this file except in compliance with the License.
-#  You may obtain a copy of the License at
-#
-#      http://www.apache.org/licenses/LICENSE-2.0
-#
-#  Unless required by applicable law or agreed to in writing, software
-#  distributed under the License is distributed on an "AS IS" BASIS,
-#  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-#  See the License for the specific language governing permissions and
-#  limitations under the License.
-#----------------------------------------------------------------------------
-
-# CMake configuration file for peripheral memory map for MPS3 as per SSE-300 design
-###################################################################################################
-#                                         Mem sizes                                               #
-###################################################################################################
-set(ITCM_SIZE             "0x00080000" CACHE STRING "ITCM size:       512 kiB")
-set(DTCM_BLK_SIZE         "0x00020000" CACHE STRING "DTCM size:       128 kiB, 4 banks")
-set(BRAM_SIZE             "0x00100000" CACHE STRING "BRAM size:         1 MiB")
-set(ISRAM0_SIZE           "0x00100000" CACHE STRING "ISRAM0 size:       1 MiB")
-set(ISRAM1_SIZE           "0x00100000" CACHE STRING "ISRAM1 size:       1 MiB")
-set(QSPI_SRAM_SIZE        "0x00800000" CACHE STRING "QSPI Flash size:   8 MiB")
-set(DDR4_BLK_SIZE         "0x10000000" CACHE STRING "DDR4 block size: 256 MiB")
-
-###################################################################################################
-#                                Base addresses for memory regions                                #
-###################################################################################################
-set(ITCM_BASE_NS          "0x00000000" CACHE STRING "Instruction TCM Non-Secure base address")
-set(BRAM_BASE_NS          "0x01000000" CACHE STRING "CODE SRAM Non-Secure base address")
-set(DTCM0_BASE_NS         "0x20000000" CACHE STRING "Data TCM block 0 Non-Secure base address")
-set(DTCM1_BASE_NS         "0x20020000" CACHE STRING "Data TCM block 1 Non-Secure base address")
-set(DTCM2_BASE_NS         "0x20040000" CACHE STRING "Data TCM block 2 Non-Secure base address")
-set(DTCM3_BASE_NS         "0x20060000" CACHE STRING "Data TCM block 3 Non-Secure base address")
-set(ISRAM0_BASE_NS        "0x21000000" CACHE STRING "Internal SRAM Area Non-Secure base address")
-set(ISRAM1_BASE_NS        "0x21100000" CACHE STRING "Internal SRAM Area Non-Secure base address")
-set(QSPI_SRAM_BASE_NS     "0x28000000" CACHE STRING "QSPI SRAM Non-Secure base address")
-set(DDR4_BLK0_BASE_NS     "0x60000000" CACHE STRING "DDR4 block 0 Non-Secure base address")
-set(DDR4_BLK1_BASE_NS     "0x80000000" CACHE STRING "DDR4 block 1 Non-Secure base address")
-set(DDR4_BLK2_BASE_NS     "0xA0000000" CACHE STRING "DDR4 block 2 Non-Secure base address")
-set(DDR4_BLK3_BASE_NS     "0xC0000000" CACHE STRING "DDR4 block 3 Non-Secure base address")
-
-set(ITCM_BASE_S           "0x10000000" CACHE STRING "Instruction TCM Secure base address")
-set(BRAM_BASE_S           "0x11000000" CACHE STRING "CODE SRAM Secure base address")
-set(DTCM0_BASE_S          "0x30000000" CACHE STRING "Data TCM block 0 Secure base address")
-set(DTCM1_BASE_S          "0x30020000" CACHE STRING "Data TCM block 1 Secure base address")
-set(DTCM2_BASE_S          "0x30040000" CACHE STRING "Data TCM block 2 Secure base address")
-set(DTCM3_BASE_S          "0x30060000" CACHE STRING "Data TCM block 3 Secure base address")
-set(ISRAM0_BASE_S         "0x31000000" CACHE STRING "Internal SRAM Area Secure base address")
-set(ISRAM1_BASE_S         "0x31100000" CACHE STRING "Internal SRAM Area Secure base address")
-set(QSPI_SRAM_BASE_S      "0x38000000" CACHE STRING "QSPI SRAM Non-Secure base address")
-set(DDR4_BLK0_BASE_S      "0x70000000" CACHE STRING "DDR4 block 0 Secure base address")
-set(DDR4_BLK1_BASE_S      "0x90000000" CACHE STRING "DDR4 block 1 Secure base address")
-set(DDR4_BLK2_BASE_S      "0xB0000000" CACHE STRING "DDR4 block 2 Secure base address")
-set(DDR4_BLK3_BASE_S      "0xD0000000" CACHE STRING "DDR4 block 3 Secure base address")
-
-###################################################################################################
-#                              Application specific config                                        #
-###################################################################################################
-set(APP_NOTE               "AN552")
-set(DESIGN_NAME            "Arm Corstone-300 - ${APP_NOTE}" CACHE STRING "Design name")
-
-# The following parameter is based on the linker/scatter script for SSE-300.
-# Do not change this parameter in isolation.
-# SRAM size reserved for activation buffers
-math(EXPR ACTIVATION_BUF_SRAM_SZ "${ISRAM0_SIZE} + ${ISRAM1_SIZE}" OUTPUT_FORMAT HEXADECIMAL)
-
-###################################################################################################
-#           Base addresses for dynamic loads (to be used for FVP form only)                       #
-###################################################################################################
-# This parameter is also mentioned in the linker/scatter script for SSE-300. Do not change these
-# parameters in isolation.
-set(DYNAMIC_MODEL_BASE      "${DDR4_BLK1_BASE_S}" CACHE STRING
-                            "Region to be used for dynamic load of model into memory")
-set(DYNAMIC_MODEL_SIZE      "0x02000000" CACHE STRING "Size of the space reserved for the model")
-math(EXPR DYNAMIC_IFM_BASE  "${DYNAMIC_MODEL_BASE} + ${DYNAMIC_MODEL_SIZE}" OUTPUT_FORMAT HEXADECIMAL)
-set(DYNAMIC_IFM_SIZE        "0x01000000" CACHE STRING "Size of the space reserved for the IFM")
-math(EXPR DYNAMIC_OFM_BASE  "${DYNAMIC_IFM_BASE} + ${DYNAMIC_IFM_SIZE}" OUTPUT_FORMAT HEXADECIMAL)
-set(DYNAMIC_OFM_SIZE        "0x01000000" CACHE STRING "Size of the space reserved for the OFM")
-
-###################################################################################################
-#                     Base addresses for peripherals - non secure                                 #
-###################################################################################################
-set(CMSDK_GPIO0_BASE      "0x41100000" CACHE STRING "User GPIO 0 Base Address (4KB)")
-set(CMSDK_GPIO1_BASE      "0x41101000" CACHE STRING "User GPIO 1 Base Address (4KB)")
-set(CMSDK_GPIO2_BASE      "0x41102000" CACHE STRING "User GPIO 2 Base Address (4KB)")
-set(CMSDK_GPIO3_BASE      "0x41103000" CACHE STRING "User GPIO 3 Base Address (4KB)")
-set(FMC_CMDSK_GPIO_BASE0  "0x41104000" CACHE STRING "FMC CMDSK GPIO 0 Base Address (4KB)")
-set(FMC_CMDSK_GPIO_BASE1  "0x41105000" CACHE STRING "FMC CMDSK GPIO 1 Base Address (4KB)")
-set(FMC_CMDSK_GPIO_BASE2  "0x41106000" CACHE STRING "FMC CMDSK GPIO 2 Base Address (4KB)")
-set(FMC_USER_AHB_BASE     "0x41107000" CACHE STRING "FMC USER AHB Base Address (4KB)")
-set(DMA0_BASE             "0x41200000" CACHE STRING "DMA0 ExternalManager0 (4KB)")
-set(DMA1_BASE             "0x41201000" CACHE STRING "DMA1 ExternalManager1 (4KB)")
-set(DMA2_BASE             "0x41202000" CACHE STRING "DMA2 ExternalManager2 (4KB)")
-set(DMA3_BASE             "0x41203000" CACHE STRING "DMA3 ExternalManager3 (4KB)")
-
-set(SMSC9220_BASE         "0x41400000" CACHE STRING "Ethernet SMSC9220 Base Address (1MB)")
-set(USB_BASE              "0x41500000" CACHE STRING "USB Base Address (1MB)")
-
-set(USER_APB0_BASE        "0x41700000" CACHE STRING "User APB0")
-set(USER_APB1_BASE        "0x41701000" CACHE STRING "User APB1")
-set(USER_APB2_BASE        "0x41702000" CACHE STRING "User APB2")
-set(USER_APB3_BASE        "0x41703000" CACHE STRING "User APB3")
-
-set(QSPI_XIP_BASE         "0x41800000" CACHE STRING "QSPI XIP config Base Address ")
-set(QSPI_WRITE_BASE       "0x41801000" CACHE STRING "QSPI write config Base Address ")
-
-if (ETHOS_U_NPU_ENABLED)
-    set(ETHOS_U_NPU_BASE        "0x48102000" CACHE STRING "Ethos-U NPU base address")
-    set(ETHOS_U_NPU_TA0_BASE    "0x48103000" CACHE STRING "Ethos-U NPU's timing adapter 0 base address")
-    set(ETHOS_U_NPU_TA1_BASE    "0x48103200" CACHE STRING "Ethos-U NPU's timing adapter 1 base address")
-endif (ETHOS_U_NPU_ENABLED)
-
-set(MPS3_I2C0_BASE        "0x49200000" CACHE STRING "Touch Screen I2C Base Address ")
-set(MPS3_I2C1_BASE        "0x49201000" CACHE STRING "Audio Interface I2C Base Address ")
-set(MPS3_SSP2_BASE        "0x49202000" CACHE STRING "ADC SPI PL022 Base Address")
-set(MPS3_SSP3_BASE        "0x49203000" CACHE STRING "Shield 0 SPI PL022 Base Address")
-set(MPS3_SSP4_BASE        "0x49204000" CACHE STRING "Shield 1 SPI PL022 Base Address")
-set(MPS3_I2C2_BASE        "0x49205000" CACHE STRING "Shield 0 SBCon Base Address ")
-set(MPS3_I2C3_BASE        "0x49206000" CACHE STRING "Shield 1 SBCon Base Address ")
-
-set(USER_APB_BASE         "0x49207000" CACHE STRING "User APB")
-set(MPS3_I2C5_BASE        "0x49208000" CACHE STRING "DDR EPROM I2C SBCon Base Address ")
-
-set(MPS3_SCC_BASE         "0x49300000" CACHE STRING "SCC Base Address ")
-set(MPS3_AAIC_I2S_BASE    "0x49301000" CACHE STRING "Audio Interface I2S Base Address ")
-set(MPS3_FPGAIO_BASE      "0x49302000" CACHE STRING "FPGA IO Base Address ")
-
-set(CMSDK_UART0_BASE      "0x49303000" CACHE STRING "UART 0 Base Address ")
-set(CMSDK_UART1_BASE      "0x49304000" CACHE STRING "UART 1 Base Address ")
-set(CMSDK_UART2_BASE      "0x49305000" CACHE STRING "UART 2 Base Address ")
-set(CMSDK_UART3_BASE      "0x49306000" CACHE STRING "UART 3 Base Address Shield 0")
-set(CMSDK_UART4_BASE      "0x49307000" CACHE STRING "UART 4 Base Address Shield 1")
-set(CMSDK_UART5_BASE      "0x49308000" CACHE STRING "UART 5 Base Address ")
-
-set(CLCD_CONFIG_BASE      "0x4930A000" CACHE STRING "CLCD CONFIG Base Address ")
-set(RTC_BASE              "0x4930B000" CACHE STRING "RTC Base address ")
-
-###################################################################################################
-#                     Base addresses for peripherals - secure                                     #
-###################################################################################################
-set(SEC_CMSDK_GPIO0_BASE   "0x51100000" CACHE STRING "User GPIO 0 Base Address (4KB)")
-set(SEC_CMSDK_GPIO1_BASE   "0x51101000" CACHE STRING "User GPIO 1 Base Address (4KB)")
-set(SEC_CMSDK_GPIO2_BASE   "0x51102000" CACHE STRING "User GPIO 2 Base Address (4KB)")
-set(SEC_CMSDK_GPIO3_BASE   "0x51103000" CACHE STRING "User GPIO 3 Base Address (4KB)")
-
-set(SEC_AHB_USER0_BASE     "0x51104000" CACHE STRING "AHB USER 0 Base Address (4KB)")
-set(SEC_AHB_USER1_BASE     "0x51105000" CACHE STRING "AHB USER 1 Base Address (4KB)")
-set(SEC_AHB_USER2_BASE     "0x51106000" CACHE STRING "AHB USER 2 Base Address (4KB)")
-set(SEC_AHB_USER3_BASE     "0x51107000" CACHE STRING "AHB USER 3 Base Address (4KB)")
-
-set(SEC_DMA0_BASE          "0x51200000" CACHE STRING "DMA0 ExternalManager0 (4KB)")
-set(SEC_DMA1_BASE          "0x51201000" CACHE STRING "DMA1 ExternalManager1 (4KB)")
-set(SEC_DMA2_BASE          "0x51202000" CACHE STRING "DMA2 ExternalManager2 (4KB)")
-set(SEC_DMA3_BASE          "0x51203000" CACHE STRING "DMA3 ExternalManager3 (4KB)")
-
-set(SEC_SMSC9220_BASE      "0x51400000" CACHE STRING "Ethernet SMSC9220 Base Address (1MB)")
-set(SEC_USB_BASE           "0x51500000" CACHE STRING "USB Base Address (1MB)")
-
-set(SEC_USER_APB0_BASE     "0x51700000" CACHE STRING "User APB0 Base Address")
-set(SEC_USER_APB1_BASE     "0x51701000" CACHE STRING "User APB1 Base Address")
-set(SEC_USER_APB2_BASE     "0x51702000" CACHE STRING "User APB2 Base Address")
-set(SEC_USER_APB3_BASE     "0x51703000" CACHE STRING "User APB3 Base Address")
-
-set(SEC_QSPI_XIP_BASE      "0x51800000" CACHE STRING "QSPI XIP config Base Address ")
-set(SEC_QSPI_WRITE_BASE    "0x51801000" CACHE STRING "QSPI write config Base Address ")
-
-if (ETHOS_U_NPU_ENABLED)
-    set(SEC_ETHOS_U_NPU_BASE     "0x58102000" CACHE STRING "Ethos-U NPU base address")
-    set(SEC_ETHOS_U_NPU_TA0_BASE "0x58103000" CACHE STRING "Ethos-U NPU's timing adapter 0 base address")
-    set(SEC_ETHOS_U_NPU_TA1_BASE "0x58103200" CACHE STRING "Ethos-U NPU's timing adapter 1 base address")
-endif (ETHOS_U_NPU_ENABLED)
-
-set(SEC_MPS3_I2C0_BASE     "0x59200000" CACHE STRING "Touch Screen I2C Base Address ")
-set(SEC_MPS3_I2C1_BASE     "0x59201000" CACHE STRING "Audio Interface I2C Base Address ")
-set(SEC_MPS3_SSP2_BASE     "0x59202000" CACHE STRING "ADC SPI PL022 Base Address")
-set(SEC_MPS3_SSP3_BASE     "0x59203000" CACHE STRING "Shield 0 SPI PL022 Base Address")
-set(SEC_MPS3_SSP4_BASE     "0x59204000" CACHE STRING "Shield 1 SPI PL022 Base Address")
-set(SEC_MPS3_I2C2_BASE     "0x59205000" CACHE STRING "Shield 0 SBCon Base Address ")
-set(SEC_MPS3_I2C3_BASE     "0x59206000" CACHE STRING "Shield 1 SBCon Base Address ")
-set(SEC_USER_APB_BASE      "0x59207000" CACHE STRING "User APB Base Address")
-set(SEC_MPS3_I2C5_BASE     "0x59208000" CACHE STRING "DDR EPROM I2C SBCon Base Address ")
-
-set(SEC_MPS3_SCC_BASE         "0x59300000" CACHE STRING "SCC Base Address ")
-set(SEC_MPS3_AAIC_I2S_BASE    "0x59301000" CACHE STRING "Audio Interface I2S Base Address ")
-set(SEC_MPS3_FPGAIO_BASE      "0x59302000" CACHE STRING "FPGA IO Base Address ")
-
-set(SEC_CMSDK_UART0_BASE      "0x59303000" CACHE STRING "UART 0 Base Address ")
-set(SEC_CMSDK_UART1_BASE      "0x59304000" CACHE STRING "UART 1 Base Address ")
-set(SEC_CMSDK_UART2_BASE      "0x59305000" CACHE STRING "UART 2 Base Address ")
-set(SEC_CMSDK_UART3_BASE      "0x59306000" CACHE STRING "UART 3 Base Address Shield 0")
-set(SEC_CMSDK_UART4_BASE      "0x59307000" CACHE STRING "UART 4 Base Address Shield 1")
-set(SEC_CMSDK_UART5_BASE      "0x59308000" CACHE STRING "UART 5 Base Address ")
-
-set(SEC_CLCD_CONFIG_BASE      "0x5930A000" CACHE STRING "CLCD CONFIG Base Address ")
-set(SEC_RTC_BASE              "0x5930B000" CACHE STRING "RTC Base address ")
-
-###################################################################################################
-#                                           MPCs                                                  #
-###################################################################################################
-set(MPC_ISRAM0_BASE_S     "0x50083000" CACHE STRING "ISRAM0 Memory Protection Controller Secure base address")
-set(MPC_ISRAM1_BASE_S     "0x50084000" CACHE STRING "ISRAM1 Memory Protection Controller Secure base address")
-set(MPC_BRAM_BASE_S       "0x57000000" CACHE STRING "SRAM Memory Protection Controller Secure base address")
-set(MPC_QSPI_BASE_S       "0x57001000" CACHE STRING "QSPI Memory Protection Controller Secure base address")
-set(MPC_DDR4_BASE_S       "0x57002000" CACHE STRING "DDR4 Memory Protection Controller Secure base address")
-
-###################################################################################################
-#                                           IRQ numbers                                           #
-###################################################################################################
-set(NONSEC_WATCHDOG_RESET_IRQn    " 0" CACHE STRING " Non-Secure Watchdog Reset Interrupt")
-set(NONSEC_WATCHDOG_IRQn          " 1" CACHE STRING " Non-Secure Watchdog Interrupt         ")
-set(S32K_TIMER_IRQn               " 2" CACHE STRING " S32K SLOWCLK Timer Interrupt          ")
-set(TIMER0_IRQn                   " 3" CACHE STRING " TIMER 0 Interrupt                     ")
-set(TIMER1_IRQn                   " 4" CACHE STRING " TIMER 1 Interrupt                     ")
-set(TIMER2_IRQn                   " 5" CACHE STRING " TIMER 2 Interrupt                     ")
-set(MPC_IRQn                      " 9" CACHE STRING " MPC Combined (Secure) Interrupt       ")
-set(PPC_IRQn                      "10" CACHE STRING " PPC Combined (Secure) Interrupt       ")
-set(MSC_IRQn                      "11" CACHE STRING " MSC Combined (Secure) Interrput       ")
-set(BRIDGE_ERROR_IRQn             "12" CACHE STRING " Bridge Error Combined (Secure) Interrupt ")
-set(MGMT_PPU_IRQn                 "14" CACHE STRING " MGMT_PPU" )
-set(SYS_PPU_IRQn                  "15" CACHE STRING " SYS_PPU" )
-set(CPU0_PPU_IRQn                 "16" CACHE STRING " CPU0_PPU" )
-set(DEBUG_PPU_IRQn                "26" CACHE STRING " DEBUG_PPU" )
-set(TIMER3_AON_IRQn               "27" CACHE STRING " TIMER3_AON" )
-set(CPU0CTIIQ0_IRQn               "28" CACHE STRING " CPU0CTIIQ0" )
-set(CPU0CTIIQ01_IRQn              "29" CACHE STRING " CPU0CTIIQ01" )
-
-set(SYS_TSTAMP_COUNTER_IRQn       "32" CACHE STRING " System timestamp counter interrupt    ")
-set(UARTRX0_IRQn                  "33" CACHE STRING " UART 0 RX Interrupt                   ")
-set(UARTTX0_IRQn                  "34" CACHE STRING " UART 0 TX Interrupt                   ")
-set(UARTRX1_IRQn                  "35" CACHE STRING " UART 1 RX Interrupt                   ")
-set(UARTTX1_IRQn                  "36" CACHE STRING " UART 1 TX Interrupt                   ")
-set(UARTRX2_IRQn                  "37" CACHE STRING " UART 2 RX Interrupt                   ")
-set(UARTTX2_IRQn                  "38" CACHE STRING " UART 2 TX Interrupt                   ")
-set(UARTRX3_IRQn                  "39" CACHE STRING " UART 3 RX Interrupt                   ")
-set(UARTTX3_IRQn                  "40" CACHE STRING " UART 3 TX Interrupt                   ")
-set(UARTRX4_IRQn                  "41" CACHE STRING " UART 4 RX Interrupt                   ")
-set(UARTTX4_IRQn                  "42" CACHE STRING " UART 4 TX Interrupt                   ")
-set(UART0_IRQn                    "43" CACHE STRING " UART 0 combined Interrupt             ")
-set(UART1_IRQn                    "44" CACHE STRING " UART 1 combined Interrupt             ")
-set(UART2_IRQn                    "45" CACHE STRING " UART 2 combined Interrupt             ")
-set(UART3_IRQn                    "46" CACHE STRING " UART 3 combined Interrupt             ")
-set(UART4_IRQn                    "47" CACHE STRING " UART 4 combined Interrupt             ")
-set(UARTOVF_IRQn                  "48" CACHE STRING " UART 0,1,2,3,4 Overflow Interrupt     ")
-set(ETHERNET_IRQn                 "49" CACHE STRING " Ethernet Interrupt                    ")
-set(I2S_IRQn                      "50" CACHE STRING " Audio I2S Interrupt                   ")
-set(TSC_IRQn                      "51" CACHE STRING " Touch Screen Interrupt                ")
-set(USB_IRQn                      "52" CACHE STRING " USB Interrupt                         ")
-set(SPI2_IRQn                     "53" CACHE STRING " ADC (SPI) Interrupt                   ")
-set(SPI3_IRQn                     "54" CACHE STRING " SPI 3 Interrupt (Shield 0)            ")
-set(SPI4_IRQn                     "55" CACHE STRING " SPI 4 Interrupt (Sheild 1)            ")
-
-if (ETHOS_U_NPU_ENABLED)
-set(EthosU_IRQn                   "56" CACHE STRING " Ethos-U55 Interrupt                   ")
-endif ()
-
-set(GPIO0_IRQn                    "69" CACHE STRING " GPIO 0 Combined Interrupt             ")
-set(GPIO1_IRQn                    "70" CACHE STRING " GPIO 1 Combined Interrupt             ")
-set(GPIO2_IRQn                    "71" CACHE STRING " GPIO 2 Combined Interrupt             ")
-set(GPIO3_IRQn                    "72" CACHE STRING " GPIO 3 Combined Interrupt             ")
-set(GPIO0_0_IRQn                  "73" CACHE STRING "")
-set(GPIO0_1_IRQn                  "74" CACHE STRING "")
-set(GPIO0_2_IRQn                  "75" CACHE STRING "")
-set(GPIO0_3_IRQn                  "76" CACHE STRING "")
-set(GPIO0_4_IRQn                  "77" CACHE STRING "")
-set(GPIO0_5_IRQn                  "78" CACHE STRING "")
-set(GPIO0_6_IRQn                  "79" CACHE STRING "")
-set(GPIO0_7_IRQn                  "80" CACHE STRING "")
-set(GPIO0_8_IRQn                  "81" CACHE STRING "")
-set(GPIO0_9_IRQn                  "82" CACHE STRING "")
-set(GPIO0_10_IRQn                 "83" CACHE STRING "")
-set(GPIO0_11_IRQn                 "84" CACHE STRING "")
-set(GPIO0_12_IRQn                 "85" CACHE STRING "")
-set(GPIO0_13_IRQn                 "86" CACHE STRING "")
-set(GPIO0_14_IRQn                 "87" CACHE STRING "")
-set(GPIO0_15_IRQn                 "88" CACHE STRING "")
-set(GPIO1_0_IRQn                  "89" CACHE STRING "")
-set(GPIO1_1_IRQn                  "90" CACHE STRING "")
-set(GPIO1_2_IRQn                  "91" CACHE STRING "")
-set(GPIO1_3_IRQn                  "92" CACHE STRING "")
-set(GPIO1_4_IRQn                  "93" CACHE STRING "")
-set(GPIO1_5_IRQn                  "94" CACHE STRING "")
-set(GPIO1_6_IRQn                  "95" CACHE STRING "")
-set(GPIO1_7_IRQn                  "96" CACHE STRING "")
-set(GPIO1_8_IRQn                  "97" CACHE STRING "")
-set(GPIO1_9_IRQn                  "98" CACHE STRING "")
-set(GPIO1_10_IRQn                 "99" CACHE STRING "")
-set(GPIO1_11_IRQn                 "100" CACHE STRING "")
-set(GPIO1_12_IRQn                 "101" CACHE STRING "")
-set(GPIO1_13_IRQn                 "102" CACHE STRING "")
-set(GPIO1_14_IRQn                 "103" CACHE STRING "")
-set(GPIO1_15_IRQn                 "104" CACHE STRING "")
-set(GPIO2_0_IRQn                  "105" CACHE STRING "")
-set(GPIO2_1_IRQn                  "106" CACHE STRING "")
-set(GPIO2_2_IRQn                  "107" CACHE STRING "")
-set(GPIO2_3_IRQn                  "108" CACHE STRING "")
-set(GPIO2_4_IRQn                  "109" CACHE STRING "")
-set(GPIO2_5_IRQn                  "110" CACHE STRING "")
-set(GPIO2_6_IRQn                  "111" CACHE STRING "")
-set(GPIO2_7_IRQn                  "112" CACHE STRING "")
-set(GPIO2_8_IRQn                  "113" CACHE STRING "")
-set(GPIO2_9_IRQn                  "114" CACHE STRING "")
-set(GPIO2_10_IRQn                 "115" CACHE STRING "")
-set(GPIO2_11_IRQn                 "116" CACHE STRING "")
-set(GPIO2_12_IRQn                 "117" CACHE STRING "")
-set(GPIO2_13_IRQn                 "118" CACHE STRING "")
-set(GPIO2_14_IRQn                 "119" CACHE STRING "")
-set(GPIO2_15_IRQn                 "120" CACHE STRING "")
-set(GPIO3_0_IRQn                  "121" CACHE STRING "")
-set(GPIO3_1_IRQn                  "122" CACHE STRING "")
-set(GPIO3_2_IRQn                  "123" CACHE STRING "")
-set(GPIO3_3_IRQn                  "124" CACHE STRING "")
-set(UARTRX5_IRQn                  "125" CACHE STRING "UART 5 RX Interrupt")
-set(UARTTX5_IRQn                  "126" CACHE STRING "UART 5 TX Interrupt")
-set(UART5_IRQn                    "127" CACHE STRING "UART 5 combined Interrupt")
diff --git a/source/hal/source/platform/mps3/cmake/templates/mem_regions.h.template b/source/hal/source/platform/mps3/cmake/templates/mem_regions.h.template
deleted file mode 100644
index 72978ce..0000000
--- a/source/hal/source/platform/mps3/cmake/templates/mem_regions.h.template
+++ /dev/null
@@ -1,58 +0,0 @@
-/*
- * Copyright (c) 2021 Arm Limited. All rights reserved.
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-// Auto-generated file
-// ** DO NOT EDIT **
-
-#ifndef MEM_REGION_DEFS_H
-#define MEM_REGION_DEFS_H
-
-#cmakedefine ITCM_SIZE             (@ITCM_SIZE@)     /* ITCM size */
-#cmakedefine DTCM_BLK_SIZE         (@DTCM_BLK_SIZE@)     /* DTCM size, 4 banks of this size available */
-#cmakedefine BRAM_SIZE             (@BRAM_SIZE@)     /* BRAM size */
-#cmakedefine ISRAM0_SIZE           (@ISRAM0_SIZE@)     /* ISRAM0 size */
-#cmakedefine ISRAM1_SIZE           (@ISRAM1_SIZE@)     /* ISRAM1 size */
-#cmakedefine QSPI_SRAM_SIZE        (@QSPI_SRAM_SIZE@)     /* QSPI Flash size */
-#cmakedefine DDR4_BLK_SIZE         (@DDR4_BLK_SIZE@)     /* DDR4 block size */
-
-#cmakedefine ITCM_BASE_NS          (@ITCM_BASE_NS@)     /* Instruction TCM Non-Secure base address */
-#cmakedefine BRAM_BASE_NS          (@BRAM_BASE_NS@)     /* CODE SRAM Non-Secure base address */
-#cmakedefine DTCM0_BASE_NS         (@DTCM0_BASE_NS@)     /* Data TCM block 0 Non-Secure base address */
-#cmakedefine DTCM1_BASE_NS         (@DTCM1_BASE_NS@)     /* Data TCM block 1 Non-Secure base address */
-#cmakedefine DTCM2_BASE_NS         (@DTCM2_BASE_NS@)     /* Data TCM block 2 Non-Secure base address */
-#cmakedefine DTCM3_BASE_NS         (@DTCM3_BASE_NS@)     /* Data TCM block 3 Non-Secure base address */
-#cmakedefine ISRAM0_BASE_NS        (@ISRAM0_BASE_NS@)     /* Internal SRAM Area Non-Secure base address */
-#cmakedefine ISRAM1_BASE_NS        (@ISRAM1_BASE_NS@)     /* Internal SRAM Area Non-Secure base address */
-#cmakedefine QSPI_SRAM_BASE_NS     (@QSPI_SRAM_BASE_NS@)     /* QSPI SRAM Non-Secure base address */
-#cmakedefine DDR4_BLK0_BASE_NS     (@DDR4_BLK0_BASE_NS@)     /* DDR4 block 0 Non-Secure base address */
-#cmakedefine DDR4_BLK1_BASE_NS     (@DDR4_BLK1_BASE_NS@)     /* DDR4 block 1 Non-Secure base address */
-#cmakedefine DDR4_BLK2_BASE_NS     (@DDR4_BLK2_BASE_NS@)     /* DDR4 block 2 Non-Secure base address */
-#cmakedefine DDR4_BLK3_BASE_NS     (@DDR4_BLK3_BASE_NS@)     /* DDR4 block 3 Non-Secure base address */
-
-#cmakedefine ITCM_BASE_S           (@ITCM_BASE_S@)     /* Instruction TCM Secure base address */
-#cmakedefine BRAM_BASE_S           (@BRAM_BASE_S@)     /* CODE SRAM Secure base address */
-#cmakedefine DTCM0_BASE_S          (@DTCM0_BASE_S@)     /* Data TCM block 0 Secure base address */
-#cmakedefine DTCM1_BASE_S          (@DTCM1_BASE_S@)     /* Data TCM block 1 Secure base address */
-#cmakedefine DTCM2_BASE_S          (@DTCM2_BASE_S@)     /* Data TCM block 2 Secure base address */
-#cmakedefine DTCM3_BASE_S          (@DTCM3_BASE_S@)     /* Data TCM block 3 Secure base address */
-#cmakedefine ISRAM0_BASE_S         (@ISRAM0_BASE_S@)     /* Internal SRAM Area Secure base address */
-#cmakedefine ISRAM1_BASE_S         (@ISRAM1_BASE_S@)     /* Internal SRAM Area Secure base address */
-#cmakedefine DDR4_BLK0_BASE_S      (@DDR4_BLK0_BASE_S@)     /* DDR4 block 0 Secure base address */
-#cmakedefine DDR4_BLK1_BASE_S      (@DDR4_BLK1_BASE_S@)     /* DDR4 block 1 Secure base address */
-#cmakedefine DDR4_BLK2_BASE_S      (@DDR4_BLK2_BASE_S@)     /* DDR4 block 2 Secure base address */
-#cmakedefine DDR4_BLK3_BASE_S      (@DDR4_BLK3_BASE_S@)     /* DDR4 block 3 Secure base address */
-
-#endif /*  MEM_REGION_DEFS_H  */
diff --git a/source/hal/source/platform/mps3/cmake/templates/peripheral_irqs.h.template b/source/hal/source/platform/mps3/cmake/templates/peripheral_irqs.h.template
deleted file mode 100644
index 7696e13..0000000
--- a/source/hal/source/platform/mps3/cmake/templates/peripheral_irqs.h.template
+++ /dev/null
@@ -1,138 +0,0 @@
-/*
- * Copyright (c) 2021 Arm Limited. All rights reserved.
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-// Auto-generated file
-// ** DO NOT EDIT **
-
-#ifndef PERIPHERAL_IRQS_H
-#define PERIPHERAL_IRQS_H
-
-/******************************************************************************/
-/*                    Peripheral interrupt numbers                            */
-/******************************************************************************/
-
-/* -------------------  Cortex-M Processor Exceptions Numbers  -------------- */
-/*                 -14 to -1 should be defined by the system header           */
-/* ----------------------  Core Specific Interrupt Numbers  ------------------*/
-#cmakedefine NONSEC_WATCHDOG_RESET_IRQn (@NONSEC_WATCHDOG_RESET_IRQn@)  /* Non-Secure Watchdog Reset Interrupt   */
-#cmakedefine NONSEC_WATCHDOG_IRQn       (@NONSEC_WATCHDOG_IRQn@)  /* Non-Secure Watchdog Interrupt         */
-#cmakedefine S32K_TIMER_IRQn            (@S32K_TIMER_IRQn@)  /* S32K Timer Interrupt                  */
-#cmakedefine TIMER0_IRQn                (@TIMER0_IRQn@)  /* TIMER 0 Interrupt                     */
-#cmakedefine TIMER1_IRQn                (@TIMER1_IRQn@)  /* TIMER 1 Interrupt                     */
-#cmakedefine TIMER2_IRQn                (@TIMER2_IRQn@)  /* TIMER 2 Interrupt                    */
-#cmakedefine MPC_IRQn                   (@MPC_IRQn@)  /* MPC Combined (@Secure@) Interrupt       */
-#cmakedefine PPC_IRQn                   (@PPC_IRQn@)  /* PPC Combined (@Secure@) Interrupt       */
-#cmakedefine MSC_IRQn                   (@MSC_IRQn@)  /* MSC Combined (@Secure@) Interrput       */
-#cmakedefine BRIDGE_ERROR_IRQn          (@BRIDGE_ERROR_IRQn@)  /* Bridge Error Combined (@Secure@) Interrupt */
-#cmakedefine MGMT_PPU_IRQn              (@MGMT_PPU_IRQn@)  /* MGMT_PPU */
-#cmakedefine SYS_PPU_IRQn               (@SYS_PPU_IRQn@)  /* SYS_PPU */
-#cmakedefine CPU0_PPU_IRQn              (@CPU0_PPU_IRQn@)  /* CPU0_PPU */
-#cmakedefine DEBUG_PPU_IRQn             (@DEBUG_PPU_IRQn@)  /* DEBUG_PPU */
-#cmakedefine TIMER3_AON_IRQn            (@TIMER3_AON_IRQn@)  /* TIMER3_AON */
-#cmakedefine CPU0CTIIQ0_IRQn            (@CPU0CTIIQ0_IRQn@)  /* CPU0CTIIQ0 */
-#cmakedefine CPU0CTIIQ01_IRQn           (@CPU0CTIIQ01_IRQn@)  /* CPU0CTIIQ01 */
-
-#cmakedefine SYS_TSTAMP_COUNTER_IRQn    (@SYS_TSTAMP_COUNTER_IRQn@)  /* System timestamp counter interrupt */
-
-/* ----------------------  CMSDK Specific Interrupt Numbers  ----------------- */
-#cmakedefine UARTRX0_IRQn               (@UARTRX0_IRQn@)  /* UART 0 RX Interrupt                   */
-#cmakedefine UARTTX0_IRQn               (@UARTTX0_IRQn@)  /* UART 0 TX Interrupt                   */
-#cmakedefine UARTRX1_IRQn               (@UARTRX1_IRQn@)  /* UART 1 RX Interrupt                   */
-#cmakedefine UARTTX1_IRQn               (@UARTTX1_IRQn@)  /* UART 1 TX Interrupt                   */
-#cmakedefine UARTRX2_IRQn               (@UARTRX2_IRQn@)  /* UART 2 RX Interrupt                   */
-#cmakedefine UARTTX2_IRQn               (@UARTTX2_IRQn@)  /* UART 2 TX Interrupt                   */
-#cmakedefine UARTRX3_IRQn               (@UARTRX3_IRQn@)  /* UART 3 RX Interrupt                   */
-#cmakedefine UARTTX3_IRQn               (@UARTTX3_IRQn@)  /* UART 3 TX Interrupt                   */
-#cmakedefine UARTRX4_IRQn               (@UARTRX4_IRQn@)  /* UART 4 RX Interrupt                   */
-#cmakedefine UARTTX4_IRQn               (@UARTTX4_IRQn@)  /* UART 4 TX Interrupt                   */
-#cmakedefine UART0_IRQn                 (@UART0_IRQn@)  /* UART 0 combined Interrupt             */
-#cmakedefine UART1_IRQn                 (@UART1_IRQn@)  /* UART 1 combined Interrupt             */
-#cmakedefine UART2_IRQn                 (@UART2_IRQn@)  /* UART 2 combined Interrupt             */
-#cmakedefine UART3_IRQn                 (@UART3_IRQn@)  /* UART 3 combined Interrupt             */
-#cmakedefine UART4_IRQn                 (@UART4_IRQn@)  /* UART 4 combined Interrupt             */
-#cmakedefine UARTOVF_IRQn               (@UARTOVF_IRQn@)  /* UART 0,1,2,3 and 4 Overflow Interrupt */
-#cmakedefine ETHERNET_IRQn              (@ETHERNET_IRQn@)  /* Ethernet Interrupt                    */
-#cmakedefine I2S_IRQn                   (@I2S_IRQn@)  /* I2S Interrupt                         */
-#cmakedefine TSC_IRQn                   (@TSC_IRQn@)  /* Touch Screen Interrupt                */
-#cmakedefine SPI2_IRQn                  (@SPI2_IRQn@)  /* SPI 2 Interrupt                       */
-#cmakedefine SPI3_IRQn                  (@SPI3_IRQn@)  /* SPI 3 Interrupt                       */
-#cmakedefine SPI4_IRQn                  (@SPI4_IRQn@)  /* SPI 4 Interrupt                       */
-
-#cmakedefine EthosU_IRQn                (@EthosU_IRQn@)   /* Ethos-Uxx Interrupt */
-
-#cmakedefine GPIO0_IRQn                 (@GPIO0_IRQn@)  /* GPIO 0 Combined Interrupt             */
-#cmakedefine GPIO1_IRQn                 (@GPIO1_IRQn@)  /* GPIO 1 Combined Interrupt             */
-#cmakedefine GPIO2_IRQn                 (@GPIO2_IRQn@)  /* GPIO 2 Combined Interrupt             */
-#cmakedefine GPIO3_IRQn                 (@GPIO3_IRQn@)  /* GPIO 3 Combined Interrupt             */
-
-#cmakedefine GPIO0_0_IRQn               (@GPIO0_0_IRQn@)  /* All P0 I/O pins used as irq source    */
-#cmakedefine GPIO0_1_IRQn               (@GPIO0_1_IRQn@)  /* There are 16 pins in total            */
-#cmakedefine GPIO0_2_IRQn               (@GPIO0_2_IRQn@)
-#cmakedefine GPIO0_3_IRQn               (@GPIO0_3_IRQn@)
-#cmakedefine GPIO0_4_IRQn               (@GPIO0_4_IRQn@)
-#cmakedefine GPIO0_5_IRQn               (@GPIO0_5_IRQn@)
-#cmakedefine GPIO0_6_IRQn               (@GPIO0_6_IRQn@)
-#cmakedefine GPIO0_7_IRQn               (@GPIO0_7_IRQn@)
-#cmakedefine GPIO0_8_IRQn               (@GPIO0_8_IRQn@)
-#cmakedefine GPIO0_9_IRQn               (@GPIO0_9_IRQn@)
-#cmakedefine GPIO0_10_IRQn              (@GPIO0_10_IRQn@)
-#cmakedefine GPIO0_11_IRQn              (@GPIO0_11_IRQn@)
-#cmakedefine GPIO0_12_IRQn              (@GPIO0_12_IRQn@)
-#cmakedefine GPIO0_13_IRQn              (@GPIO0_13_IRQn@)
-#cmakedefine GPIO0_14_IRQn              (@GPIO0_14_IRQn@)
-#cmakedefine GPIO0_15_IRQn              (@GPIO0_15_IRQn@)
-#cmakedefine GPIO1_0_IRQn               (@GPIO1_0_IRQn@)  /* All P1 I/O pins used as irq source    */
-#cmakedefine GPIO1_1_IRQn               (@GPIO1_1_IRQn@)  /* There are 16 pins in total            */
-#cmakedefine GPIO1_2_IRQn               (@GPIO1_2_IRQn@)
-#cmakedefine GPIO1_3_IRQn               (@GPIO1_3_IRQn@)
-#cmakedefine GPIO1_4_IRQn               (@GPIO1_4_IRQn@)
-#cmakedefine GPIO1_5_IRQn               (@GPIO1_5_IRQn@)
-#cmakedefine GPIO1_6_IRQn               (@GPIO1_6_IRQn@)
-#cmakedefine GPIO1_7_IRQn               (@GPIO1_7_IRQn@)
-#cmakedefine GPIO1_8_IRQn               (@GPIO1_8_IRQn@)
-#cmakedefine GPIO1_9_IRQn               (@GPIO1_9_IRQn@)
-#cmakedefine GPIO1_10_IRQn              (@GPIO1_10_IRQn@)
-#cmakedefine GPIO1_11_IRQn              (@GPIO1_11_IRQn@)
-#cmakedefine GPIO1_12_IRQn              (@GPIO1_12_IRQn@)
-#cmakedefine GPIO1_13_IRQn              (@GPIO1_13_IRQn@)
-#cmakedefine GPIO1_14_IRQn              (@GPIO1_14_IRQn@)
-#cmakedefine GPIO1_15_IRQn              (@GPIO1_15_IRQn@)
-#cmakedefine GPIO2_0_IRQn               (@GPIO2_0_IRQn@)  /* All P2 I/O pins used as irq source    */
-#cmakedefine GPIO2_1_IRQn               (@GPIO2_1_IRQn@)  /* There are 15 pins in total            */
-#cmakedefine GPIO2_2_IRQn               (@GPIO2_2_IRQn@)
-#cmakedefine GPIO2_3_IRQn               (@GPIO2_3_IRQn@)
-#cmakedefine GPIO2_4_IRQn               (@GPIO2_4_IRQn@)
-#cmakedefine GPIO2_5_IRQn               (@GPIO2_5_IRQn@)
-#cmakedefine GPIO2_6_IRQn               (@GPIO2_6_IRQn@)
-#cmakedefine GPIO2_7_IRQn               (@GPIO2_7_IRQn@)
-#cmakedefine GPIO2_8_IRQn               (@GPIO2_8_IRQn@)
-#cmakedefine GPIO2_9_IRQn               (@GPIO2_9_IRQn@)
-#cmakedefine GPIO2_10_IRQn              (@GPIO2_10_IRQn@)
-#cmakedefine GPIO2_11_IRQn              (@GPIO2_11_IRQn@)
-#cmakedefine GPIO2_12_IRQn              (@GPIO2_12_IRQn@)
-#cmakedefine GPIO2_13_IRQn              (@GPIO2_13_IRQn@)
-#cmakedefine GPIO2_14_IRQn              (@GPIO2_14_IRQn@)
-#cmakedefine GPIO2_15_IRQn              (@GPIO2_15_IRQn@)
-#cmakedefine GPIO3_0_IRQn               (@GPIO3_0_IRQn@)  /* All P3 I/O pins used as irq source    */
-#cmakedefine GPIO3_1_IRQn               (@GPIO3_1_IRQn@)  /* There are 4 pins in total             */
-#cmakedefine GPIO3_2_IRQn               (@GPIO3_2_IRQn@)
-#cmakedefine GPIO3_3_IRQn               (@GPIO3_3_IRQn@)
-#cmakedefine UARTRX5_IRQn               (@UARTRX5_IRQn@)  /* UART 5 RX Interrupt                   */
-#cmakedefine UARTTX5_IRQn               (@UARTTX5_IRQn@)  /* UART 5 TX Interrupt                   */
-#cmakedefine UART5_IRQn                 (@UART5_IRQn@)  /* UART 5 combined Interrupt             */
-#cmakedefine HDCLCD_IRQn                (@HDCLCD_IRQn@)  /* HDCLCD Interrupt                      */
-
-#endif /* PERIPHERAL_IRQS_H */
diff --git a/source/hal/source/platform/mps3/cmake/templates/peripheral_memmap.h.template b/source/hal/source/platform/mps3/cmake/templates/peripheral_memmap.h.template
deleted file mode 100644
index d7f0b3a..0000000
--- a/source/hal/source/platform/mps3/cmake/templates/peripheral_memmap.h.template
+++ /dev/null
@@ -1,162 +0,0 @@
-/*
- * Copyright (c) 2021 Arm Limited. All rights reserved.
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-// Auto-generated file
-// ** DO NOT EDIT **
-
-#ifndef PERIPHERAL_MEMMAP_H
-#define PERIPHERAL_MEMMAP_H
-
-#cmakedefine DESIGN_NAME              "@DESIGN_NAME@"
-
-/******************************************************************************/
-/*                         Peripheral memory map                              */
-/******************************************************************************/
-
-#cmakedefine CMSDK_GPIO0_BASE         (@CMSDK_GPIO0_BASE@)       /* User GPIO 0 Base Address   */
-#cmakedefine CMSDK_GPIO1_BASE         (@CMSDK_GPIO1_BASE@)       /* User GPIO 1 Base Address   */
-#cmakedefine CMSDK_GPIO2_BASE         (@CMSDK_GPIO2_BASE@)       /* User GPIO 2 Base Address   */
-#cmakedefine CMSDK_GPIO3_BASE         (@CMSDK_GPIO3_BASE@)       /* User GPIO 3 Base Address   */
-
-#cmakedefine FMC_CMDSK_GPIO_BASE0        (@FMC_CMDSK_GPIO_BASE0@)       /* FMC_CMDSK_GPIO_BASE 0 Base Address (4KB) */
-#cmakedefine FMC_CMDSK_GPIO_BASE1        (@FMC_CMDSK_GPIO_BASE1@)       /* FMC_CMDSK_GPIO_BASE 1 Base Address (4KB)*/
-#cmakedefine FMC_CMDSK_GPIO_BASE2        (@FMC_CMDSK_GPIO_BASE2@)       /* FMC_CMDSK_GPIO_BASE 2 Base Address (4KB)*/
-#cmakedefine FMC_USER_AHB_BASE           (@FMC_USER_AHB_BASE@)          /* FMC_USER_AHB_BASE     Base Address (4KB)*/
-
-#cmakedefine DMA0_BASE                (@DMA0_BASE@)       /* DMA0 (4KB) */
-#cmakedefine DMA1_BASE                (@DMA1_BASE@)       /* DMA1 (4KB) */
-#cmakedefine DMA2_BASE                (@DMA2_BASE@)       /* DMA2 (4KB) */
-#cmakedefine DMA3_BASE                (@DMA3_BASE@)       /* DMA3 (4KB) */
-
-#cmakedefine USER_APB0_BASE           (@USER_APB0_BASE@)       /* User APB0 */
-#cmakedefine USER_APB1_BASE           (@USER_APB1_BASE@)       /* User APB1 */
-#cmakedefine USER_APB2_BASE           (@USER_APB2_BASE@)       /* User APB2 */
-#cmakedefine USER_APB3_BASE           (@USER_APB3_BASE@)       /* User APB3 */
-
-#cmakedefine MPS3_I2C0_BASE           (@MPS3_I2C0_BASE@)       /* Touch Screen I2C Base Address */
-#cmakedefine MPS3_I2C1_BASE           (@MPS3_I2C1_BASE@)       /* Audio Interface I2C Base Address */
-#cmakedefine MPS3_SSP2_BASE           (@MPS3_SSP2_BASE@)       /* ADC SPI PL022 Base Address   */
-#cmakedefine MPS3_SSP3_BASE           (@MPS3_SSP3_BASE@)       /* Shield 0 SPI PL022 Base Address   */
-
-#cmakedefine MPS3_SSP4_BASE           (@MPS3_SSP4_BASE@)       /* Shield 1 SPI PL022 Base Address   */
-#cmakedefine MPS3_I2C2_BASE           (@MPS3_I2C2_BASE@)       /* Shield 0 SBCon Base Address */
-#cmakedefine MPS3_I2C3_BASE           (@MPS3_I2C3_BASE@)       /* Shield 1 SBCon Base Address */
-
-#cmakedefine USER_APB_BASE            (@USER_APB_BASE@)       /* User APB Base Address */
-#cmakedefine MPS3_I2C4_BASE           (@MPS3_I2C4_BASE@)       /* HDMI I2C SBCon Base Address */
-#cmakedefine MPS3_I2C5_BASE           (@MPS3_I2C5_BASE@)       /* DDR EPROM I2C SBCon Base Address */
-#cmakedefine MPS3_SCC_BASE            (@MPS3_SCC_BASE@)       /* SCC Base Address    */
-#cmakedefine MPS3_AAIC_I2S_BASE       (@MPS3_AAIC_I2S_BASE@)       /* Audio Interface I2S Base Address */
-#cmakedefine MPS3_FPGAIO_BASE         (@MPS3_FPGAIO_BASE@)       /* FPGA IO Base Address */
-#cmakedefine PL011_UART0_BASE         (@PL011_UART0_BASE@)       /* PL011 UART0 Base Address */
-#cmakedefine CMSDK_UART0_BASE         (@CMSDK_UART0_BASE@)       /* UART 0 Base Address */
-#cmakedefine CMSDK_UART1_BASE         (@CMSDK_UART1_BASE@)       /* UART 1 Base Address */
-#cmakedefine CMSDK_UART2_BASE         (@CMSDK_UART2_BASE@)       /* UART 2 Base Address */
-#cmakedefine CMSDK_UART3_BASE         (@CMSDK_UART3_BASE@)       /* UART 3 Base Address Shield 0*/
-
-#cmakedefine ETHOS_U_NPU_BASE           (@ETHOS_U_NPU_BASE@)    /* Ethos-U NPU base address*/
-#cmakedefine ETHOS_U_NPU_TA0_BASE       (@ETHOS_U_NPU_TA0_BASE@)    /* Ethos-U NPU's timing adapter 0 base address */
-#cmakedefine ETHOS_U_NPU_TA1_BASE       (@ETHOS_U_NPU_TA1_BASE@)    /* Ethos-U NPU's timing adapter 1 base address */
-
-#cmakedefine CMSDK_UART4_BASE         (@CMSDK_UART4_BASE@)       /* UART 4 Base Address Shield 1*/
-#cmakedefine CMSDK_UART5_BASE         (@CMSDK_UART5_BASE@)       /* UART 5 Base Address */
-#cmakedefine HDMI_AUDIO_BASE          (@HDMI_AUDIO_BASE@)       /* HDMI AUDIO Base Address */
-#cmakedefine CLCD_CONFIG_BASE         (@CLCD_CONFIG_BASE@)       /* CLCD CONFIG Base Address */
-#cmakedefine RTC_BASE                 (@RTC_BASE@)       /* RTC Base address */
-#cmakedefine SMSC9220_BASE            (@SMSC9220_BASE@)       /* Ethernet SMSC9220 Base Address */
-#cmakedefine USB_BASE                 (@USB_BASE@)       /* USB Base Address */
-#cmakedefine CMSDK_SDIO_BASE          (@CMSDK_SDIO_BASE@)       /* User SDIO Base Address   */
-#cmakedefine MPS3_CLCD_BASE           (@MPS3_CLCD_BASE@)       /* HDLCD Base Address   */
-#cmakedefine MPS3_eMMC_BASE           (@MPS3_eMMC_BASE@)       /* User eMMC Base Address   */
-#cmakedefine USER_BASE                (@USER_BASE@)       /* User ? Base Address */
-
-#cmakedefine QSPI_XIP_BASE            (@QSPI_XIP_BASE@)       /* QSPI XIP config Base Address */
-#cmakedefine QSPI_WRITE_BASE          (@QSPI_WRITE_BASE@)       /* QSPI write config Base Address */
-
-/******************************************************************************/
-/*                      Secure Peripheral memory map                          */
-/******************************************************************************/
-
-#cmakedefine MPC_ISRAM0_BASE_S        (@MPC_ISRAM0_BASE_S@)       /* ISRAM0 Memory Protection Controller Secure base address */
-#cmakedefine MPC_ISRAM1_BASE_S        (@MPC_ISRAM1_BASE_S@)       /* ISRAM1 Memory Protection Controller Secure base address */
-
-#cmakedefine SEC_CMSDK_GPIO0_BASE     (@SEC_CMSDK_GPIO0_BASE@)       /* User GPIO 0 Base Address   */
-#cmakedefine SEC_CMSDK_GPIO1_BASE     (@SEC_CMSDK_GPIO1_BASE@)       /* User GPIO 0 Base Address   */
-#cmakedefine SEC_CMSDK_GPIO2_BASE     (@SEC_CMSDK_GPIO2_BASE@)       /* User GPIO 0 Base Address   */
-#cmakedefine SEC_CMSDK_GPIO3_BASE     (@SEC_CMSDK_GPIO3_BASE@)       /* User GPIO 0 Base Address   */
-
-#cmakedefine SEC_AHB_USER0_BASE       (@SEC_AHB_USER0_BASE@)       /* AHB USER 0 Base Address (4KB) */
-#cmakedefine SEC_AHB_USER1_BASE       (@SEC_AHB_USER1_BASE@)       /* AHB USER 1 Base Address (4KB)*/
-#cmakedefine SEC_AHB_USER2_BASE       (@SEC_AHB_USER2_BASE@)       /* AHB USER 2 Base Address (4KB)*/
-#cmakedefine SEC_AHB_USER3_BASE       (@SEC_AHB_USER3_BASE@)       /* AHB USER 3 Base Address (4KB)*/
-
-#cmakedefine SEC_DMA0_BASE            (@SEC_DMA0_BASE@)       /* DMA0 (4KB) */
-#cmakedefine SEC_DMA1_BASE            (@SEC_DMA1_BASE@)       /* DMA1 (4KB) */
-#cmakedefine SEC_DMA2_BASE            (@SEC_DMA2_BASE@)       /* DMA2 (4KB) */
-#cmakedefine SEC_DMA3_BASE            (@SEC_DMA3_BASE@)       /* DMA3 (4KB) */
-
-#cmakedefine SEC_USER_APB0_BASE       (@SEC_USER_APB0_BASE@)       /* User APB0 */
-#cmakedefine SEC_USER_APB1_BASE       (@SEC_USER_APB1_BASE@)       /* User APB1 */
-#cmakedefine SEC_USER_APB2_BASE       (@SEC_USER_APB2_BASE@)       /* User APB2 */
-#cmakedefine SEC_USER_APB3_BASE       (@SEC_USER_APB3_BASE@)       /* User APB3 */
-
-#cmakedefine SEC_MPS3_I2C0_BASE       (@SEC_MPS3_I2C0_BASE@)       /* Touch Screen I2C Base Address */
-#cmakedefine SEC_MPS3_I2C1_BASE       (@SEC_MPS3_I2C1_BASE@)       /* Audio Interface I2C Base Address */
-#cmakedefine SEC_MPS3_SSP2_BASE       (@SEC_MPS3_SSP2_BASE@)       /* ADC SPI PL022 Base Address   */
-#cmakedefine SEC_MPS3_SSP3_BASE       (@SEC_MPS3_SSP3_BASE@)       /* Shield 0 SPI PL022 Base Address   */
-
-#cmakedefine SEC_MPS3_SSP4_BASE       (@SEC_MPS3_SSP4_BASE@)       /* Shield 1 SPI PL022 Base Address   */
-#cmakedefine SEC_MPS3_I2C2_BASE       (@SEC_MPS3_I2C2_BASE@)       /* Shield 0 SBCon Base Address */
-#cmakedefine SEC_MPS3_I2C3_BASE       (@SEC_MPS3_I2C3_BASE@)       /* Shield 1 SBCon Base Address */
-
-#cmakedefine SEC_MPS3_I2C4_BASE       (@SEC_MPS3_I2C4_BASE@)       /* HDMI I2C SBCon Base Address */
-#cmakedefine SEC_MPS3_I2C5_BASE       (@SEC_MPS3_I2C5_BASE@)       /* DDR EPROM I2C SBCon Base Address */
-#cmakedefine SEC_MPS3_SCC_BASE        (@SEC_MPS3_SCC_BASE@)       /* SCC Base Address    */
-#cmakedefine SEC_MPS3_AAIC_I2S_BASE   (@SEC_MPS3_AAIC_I2S_BASE@)       /* Audio Interface I2S Base Address */
-#cmakedefine SEC_MPS3_FPGAIO_BASE     (@SEC_MPS3_FPGAIO_BASE@)       /* FPGA IO Base Address */
-#cmakedefine SEC_CMSDK_UART0_BASE     (@SEC_CMSDK_UART0_BASE@)       /* UART 0 Base Address */
-#cmakedefine SEC_CMSDK_UART1_BASE     (@SEC_CMSDK_UART1_BASE@)       /* UART 1 Base Address */
-#cmakedefine SEC_CMSDK_UART2_BASE     (@SEC_CMSDK_UART2_BASE@)       /* UART 2 Base Address */
-#cmakedefine SEC_CMSDK_UART3_BASE     (@SEC_CMSDK_UART3_BASE@)       /* UART 3 Base Address Shield 0*/
-
-#cmakedefine SEC_CMSDK_UART4_BASE     (@SEC_CMSDK_UART4_BASE@)       /* UART 4 Base Address Shield 1*/
-#cmakedefine SEC_CMSDK_UART5_BASE     (@SEC_CMSDK_UART5_BASE@)       /* UART 5 Base Address */
-#cmakedefine SEC_HDMI_AUDIO_BASE      (@SEC_HDMI_AUDIO_BASE@)       /* HDMI AUDIO Base Address */
-#cmakedefine SEC_CLCD_CONFIG_BASE     (@SEC_CLCD_CONFIG_BASE@)       /* CLCD CONFIG Base Address */
-#cmakedefine SEC_RTC_BASE             (@SEC_RTC_BASE@)       /* RTC Base address */
-#cmakedefine SEC_SMSC9220_BASE        (@SEC_SMSC9220_BASE@)       /* Ethernet SMSC9220 Base Address */
-#cmakedefine SEC_USB_BASE             (@SEC_USB_BASE@)       /* USB Base Address */
-
-#cmakedefine SEC_ETHOS_U_NPU_BASE       (@SEC_ETHOS_U_NPU_BASE@)   /* Ethos-U NPU base address*/
-#cmakedefine SEC_ETHOS_U_NPU_TA0_BASE   (@SEC_ETHOS_U_NPU_TA0_BASE@)   /* Ethos-U NPU's timing adapter 0 base address */
-#cmakedefine SEC_ETHOS_U_NPU_TA1_BASE   (@SEC_ETHOS_U_NPU_TA1_BASE@)   /* Ethos-U NPU's timing adapter 1 base address */
-
-#cmakedefine SEC_USER_BASE            (@SEC_USER_BASE@)       /* User ? Base Address */
-
-#cmakedefine SEC_QSPI_XIP_BASE        (@SEC_QSPI_XIP_BASE@)       /* QSPI XIP config Base Address */
-#cmakedefine SEC_QSPI_WRITE_BASE      (@SEC_QSPI_WRITE_BASE@)       /* QSPI write config Base Address */
-
-/******************************************************************************/
-/*                                  MPCs                                      */
-/******************************************************************************/
-
-#cmakedefine MPC_ISRAM0_BASE_S        (@MPC_ISRAM0_BASE_S@)       /* Internal SRAM 0 MPC */
-#cmakedefine MPC_ISRAM1_BASE_S        (@MPC_ISRAM1_BASE_S@)       /* Internal SRAM 1 MPC */
-#cmakedefine MPC_BRAM_BASE_S          (@MPC_BRAM_BASE_S@)       /* SRAM Memory Protection Controller Secure base address */
-#cmakedefine MPC_QSPI_BASE_S          (@MPC_QSPI_BASE_S@)       /* QSPI Memory Protection Controller Secure base address */
-#cmakedefine MPC_DDR4_BASE_S          (@MPC_DDR4_BASE_S@)       /* DDR4 Memory Protection Controller Secure base address */
-
-#endif /* PERIPHERAL_MEMMAP_H */
diff --git a/source/hal/source/platform/mps3/cmake/templates/timing_adapter_settings.template b/source/hal/source/platform/mps3/cmake/templates/timing_adapter_settings.template
deleted file mode 100644
index d5e202a..0000000
--- a/source/hal/source/platform/mps3/cmake/templates/timing_adapter_settings.template
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
- * Copyright (c) 2021 Arm Limited. All rights reserved.
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-// Auto-generated file
-// ** DO NOT EDIT **
-
-#ifndef TIMING_ADAPTER_SETTINGS_H
-#define TIMING_ADAPTER_SETTINGS_H
-
-#cmakedefine TA0_BASE       (@TA0_BASE@)
-#cmakedefine TA1_BASE       (@TA1_BASE@)
-
-/* Timing adapter settings for AXI0 */
-#if defined(TA0_BASE)
-
-#define TA0_MAXR           (@TA0_MAXR@)
-#define TA0_MAXW           (@TA0_MAXW@)
-#define TA0_MAXRW          (@TA0_MAXRW@)
-#define TA0_RLATENCY       (@TA0_RLATENCY@)
-#define TA0_WLATENCY       (@TA0_WLATENCY@)
-#define TA0_PULSE_ON       (@TA0_PULSE_ON@)
-#define TA0_PULSE_OFF      (@TA0_PULSE_OFF@)
-#define TA0_BWCAP          (@TA0_BWCAP@)
-#define TA0_PERFCTRL       (@TA0_PERFCTRL@)
-#define TA0_PERFCNT        (@TA0_PERFCNT@)
-#define TA0_MODE           (@TA0_MODE@)
-#define TA0_HISTBIN        (@TA0_HISTBIN@)
-#define TA0_HISTCNT        (@TA0_HISTCNT@)
-
-#endif /* defined(TA0_BASE) */
-
-/* Timing adapter settings for AXI1 */
-#if defined(TA1_BASE)
-
-#define TA1_MAXR           (@TA1_MAXR@)
-#define TA1_MAXW           (@TA1_MAXW@)
-#define TA1_MAXRW          (@TA1_MAXRW@)
-#define TA1_RLATENCY       (@TA1_RLATENCY@)
-#define TA1_WLATENCY       (@TA1_WLATENCY@)
-#define TA1_PULSE_ON       (@TA1_PULSE_ON@)
-#define TA1_PULSE_OFF      (@TA1_PULSE_OFF@)
-#define TA1_BWCAP          (@TA1_BWCAP@)
-#define TA1_PERFCTRL       (@TA1_PERFCTRL@)
-#define TA1_PERFCNT        (@TA1_PERFCNT@)
-#define TA1_MODE           (@TA1_MODE@)
-#define TA1_HISTBIN        (@TA1_HISTBIN@)
-#define TA1_HISTCNT        (@TA1_HISTCNT@)
-
-#endif /* defined(TA1_BASE) */
-
-#endif /* TIMING_ADAPTER_SETTINGS_H */
\ No newline at end of file
diff --git a/source/hal/source/platform/mps3/include/sse-300/mem_regions.h b/source/hal/source/platform/mps3/include/sse-300/mem_regions.h
new file mode 100644
index 0000000..c88ae3c
--- /dev/null
+++ b/source/hal/source/platform/mps3/include/sse-300/mem_regions.h
@@ -0,0 +1,56 @@
+/*
+ * Copyright (c) 2022 Arm Limited. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef MEM_REGION_DEFS_H
+#define MEM_REGION_DEFS_H
+
+#define ITCM_SIZE             (0x00080000)     /* ITCM size */
+#define DTCM_BLK_SIZE         (0x00020000)     /* DTCM size, 4 banks of this size available */
+#define BRAM_SIZE             (0x00100000)     /* BRAM size */
+#define ISRAM0_SIZE           (0x00100000)     /* ISRAM0 size */
+#define ISRAM1_SIZE           (0x00100000)     /* ISRAM1 size */
+#define QSPI_SRAM_SIZE        (0x00800000)     /* QSPI Flash size */
+#define DDR4_BLK_SIZE         (0x10000000)     /* DDR4 block size */
+
+#define ITCM_BASE_NS          (0x00000000)     /* Instruction TCM Non-Secure base address */
+#define BRAM_BASE_NS          (0x01000000)     /* CODE SRAM Non-Secure base address */
+#define DTCM0_BASE_NS         (0x20000000)     /* Data TCM block 0 Non-Secure base address */
+#define DTCM1_BASE_NS         (0x20020000)     /* Data TCM block 1 Non-Secure base address */
+#define DTCM2_BASE_NS         (0x20040000)     /* Data TCM block 2 Non-Secure base address */
+#define DTCM3_BASE_NS         (0x20060000)     /* Data TCM block 3 Non-Secure base address */
+#define ISRAM0_BASE_NS        (0x21000000)     /* Internal SRAM Area Non-Secure base address */
+#define ISRAM1_BASE_NS        (0x21100000)     /* Internal SRAM Area Non-Secure base address */
+#define QSPI_SRAM_BASE_NS     (0x28000000)     /* QSPI SRAM Non-Secure base address */
+#define DDR4_BLK0_BASE_NS     (0x60000000)     /* DDR4 block 0 Non-Secure base address */
+#define DDR4_BLK1_BASE_NS     (0x80000000)     /* DDR4 block 1 Non-Secure base address */
+#define DDR4_BLK2_BASE_NS     (0xA0000000)     /* DDR4 block 2 Non-Secure base address */
+#define DDR4_BLK3_BASE_NS     (0xC0000000)     /* DDR4 block 3 Non-Secure base address */
+
+#define ITCM_BASE_S           (0x10000000)     /* Instruction TCM Secure base address */
+#define BRAM_BASE_S           (0x11000000)     /* CODE SRAM Secure base address */
+#define DTCM0_BASE_S          (0x30000000)     /* Data TCM block 0 Secure base address */
+#define DTCM1_BASE_S          (0x30020000)     /* Data TCM block 1 Secure base address */
+#define DTCM2_BASE_S          (0x30040000)     /* Data TCM block 2 Secure base address */
+#define DTCM3_BASE_S          (0x30060000)     /* Data TCM block 3 Secure base address */
+#define ISRAM0_BASE_S         (0x31000000)     /* Internal SRAM Area Secure base address */
+#define ISRAM1_BASE_S         (0x31100000)     /* Internal SRAM Area Secure base address */
+#define DDR4_BLK0_BASE_S      (0x70000000)     /* DDR4 block 0 Secure base address */
+#define DDR4_BLK1_BASE_S      (0x90000000)     /* DDR4 block 1 Secure base address */
+#define DDR4_BLK2_BASE_S      (0xB0000000)     /* DDR4 block 2 Secure base address */
+#define DDR4_BLK3_BASE_S      (0xD0000000)     /* DDR4 block 3 Secure base address */
+
+#endif /*  MEM_REGION_DEFS_H  */
diff --git a/source/hal/source/platform/mps3/include/sse-300/peripheral_irqs.h b/source/hal/source/platform/mps3/include/sse-300/peripheral_irqs.h
new file mode 100644
index 0000000..431710b
--- /dev/null
+++ b/source/hal/source/platform/mps3/include/sse-300/peripheral_irqs.h
@@ -0,0 +1,136 @@
+/*
+ * Copyright (c) 2022 Arm Limited. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef PERIPHERAL_IRQS_H
+#define PERIPHERAL_IRQS_H
+
+/******************************************************************************/
+/*                    Peripheral interrupt numbers                            */
+/******************************************************************************/
+
+/* -------------------  Cortex-M Processor Exceptions Numbers  -------------- */
+/*                 -14 to -1 should be defined by the system header           */
+/* ----------------------  Core Specific Interrupt Numbers  ------------------*/
+#define NONSEC_WATCHDOG_RESET_IRQn ( 0)  /* Non-Secure Watchdog Reset Interrupt   */
+#define NONSEC_WATCHDOG_IRQn       ( 1)  /* Non-Secure Watchdog Interrupt         */
+#define S32K_TIMER_IRQn            ( 2)  /* S32K Timer Interrupt                  */
+#define TIMER0_IRQn                ( 3)  /* TIMER 0 Interrupt                     */
+#define TIMER1_IRQn                ( 4)  /* TIMER 1 Interrupt                     */
+#define TIMER2_IRQn                ( 5)  /* TIMER 2 Interrupt                    */
+#define MPC_IRQn                   ( 9)  /* MPC Combined () Interrupt       */
+#define PPC_IRQn                   (10)  /* PPC Combined () Interrupt       */
+#define MSC_IRQn                   (11)  /* MSC Combined () Interrput       */
+#define BRIDGE_ERROR_IRQn          (12)  /* Bridge Error Combined () Interrupt */
+#define MGMT_PPU_IRQn              (14)  /* MGMT_PPU */
+#define SYS_PPU_IRQn               (15)  /* SYS_PPU */
+#define CPU0_PPU_IRQn              (16)  /* CPU0_PPU */
+#define DEBUG_PPU_IRQn             (26)  /* DEBUG_PPU */
+#define TIMER3_AON_IRQn            (27)  /* TIMER3_AON */
+#define CPU0CTIIQ0_IRQn            (28)  /* CPU0CTIIQ0 */
+#define CPU0CTIIQ01_IRQn           (29)  /* CPU0CTIIQ01 */
+
+#define SYS_TSTAMP_COUNTER_IRQn    (32)  /* System timestamp counter interrupt */
+
+/* ----------------------  CMSDK Specific Interrupt Numbers  ----------------- */
+#define UARTRX0_IRQn               (33)  /* UART 0 RX Interrupt                   */
+#define UARTTX0_IRQn               (34)  /* UART 0 TX Interrupt                   */
+#define UARTRX1_IRQn               (35)  /* UART 1 RX Interrupt                   */
+#define UARTTX1_IRQn               (36)  /* UART 1 TX Interrupt                   */
+#define UARTRX2_IRQn               (37)  /* UART 2 RX Interrupt                   */
+#define UARTTX2_IRQn               (38)  /* UART 2 TX Interrupt                   */
+#define UARTRX3_IRQn               (39)  /* UART 3 RX Interrupt                   */
+#define UARTTX3_IRQn               (40)  /* UART 3 TX Interrupt                   */
+#define UARTRX4_IRQn               (41)  /* UART 4 RX Interrupt                   */
+#define UARTTX4_IRQn               (42)  /* UART 4 TX Interrupt                   */
+#define UART0_IRQn                 (43)  /* UART 0 combined Interrupt             */
+#define UART1_IRQn                 (44)  /* UART 1 combined Interrupt             */
+#define UART2_IRQn                 (45)  /* UART 2 combined Interrupt             */
+#define UART3_IRQn                 (46)  /* UART 3 combined Interrupt             */
+#define UART4_IRQn                 (47)  /* UART 4 combined Interrupt             */
+#define UARTOVF_IRQn               (48)  /* UART 0,1,2,3 and 4 Overflow Interrupt */
+#define ETHERNET_IRQn              (49)  /* Ethernet Interrupt                    */
+#define I2S_IRQn                   (50)  /* I2S Interrupt                         */
+#define TSC_IRQn                   (51)  /* Touch Screen Interrupt                */
+#define SPI2_IRQn                  (53)  /* SPI 2 Interrupt                       */
+#define SPI3_IRQn                  (54)  /* SPI 3 Interrupt                       */
+#define SPI4_IRQn                  (55)  /* SPI 4 Interrupt                       */
+
+#define EthosU_IRQn                (56)   /* Ethos-Uxx Interrupt */
+
+#define GPIO0_IRQn                 (69)  /* GPIO 0 Combined Interrupt             */
+#define GPIO1_IRQn                 (70)  /* GPIO 1 Combined Interrupt             */
+#define GPIO2_IRQn                 (71)  /* GPIO 2 Combined Interrupt             */
+#define GPIO3_IRQn                 (72)  /* GPIO 3 Combined Interrupt             */
+
+#define GPIO0_0_IRQn               (73)  /* All P0 I/O pins used as irq source    */
+#define GPIO0_1_IRQn               (74)  /* There are 16 pins in total            */
+#define GPIO0_2_IRQn               (75)
+#define GPIO0_3_IRQn               (76)
+#define GPIO0_4_IRQn               (77)
+#define GPIO0_5_IRQn               (78)
+#define GPIO0_6_IRQn               (79)
+#define GPIO0_7_IRQn               (80)
+#define GPIO0_8_IRQn               (81)
+#define GPIO0_9_IRQn               (82)
+#define GPIO0_10_IRQn              (83)
+#define GPIO0_11_IRQn              (84)
+#define GPIO0_12_IRQn              (85)
+#define GPIO0_13_IRQn              (86)
+#define GPIO0_14_IRQn              (87)
+#define GPIO0_15_IRQn              (88)
+#define GPIO1_0_IRQn               (89)  /* All P1 I/O pins used as irq source    */
+#define GPIO1_1_IRQn               (90)  /* There are 16 pins in total            */
+#define GPIO1_2_IRQn               (91)
+#define GPIO1_3_IRQn               (92)
+#define GPIO1_4_IRQn               (93)
+#define GPIO1_5_IRQn               (94)
+#define GPIO1_6_IRQn               (95)
+#define GPIO1_7_IRQn               (96)
+#define GPIO1_8_IRQn               (97)
+#define GPIO1_9_IRQn               (98)
+#define GPIO1_10_IRQn              (99)
+#define GPIO1_11_IRQn              (100)
+#define GPIO1_12_IRQn              (101)
+#define GPIO1_13_IRQn              (102)
+#define GPIO1_14_IRQn              (103)
+#define GPIO1_15_IRQn              (104)
+#define GPIO2_0_IRQn               (105)  /* All P2 I/O pins used as irq source    */
+#define GPIO2_1_IRQn               (106)  /* There are 15 pins in total            */
+#define GPIO2_2_IRQn               (107)
+#define GPIO2_3_IRQn               (108)
+#define GPIO2_4_IRQn               (109)
+#define GPIO2_5_IRQn               (110)
+#define GPIO2_6_IRQn               (111)
+#define GPIO2_7_IRQn               (112)
+#define GPIO2_8_IRQn               (113)
+#define GPIO2_9_IRQn               (114)
+#define GPIO2_10_IRQn              (115)
+#define GPIO2_11_IRQn              (116)
+#define GPIO2_12_IRQn              (117)
+#define GPIO2_13_IRQn              (118)
+#define GPIO2_14_IRQn              (119)
+#define GPIO2_15_IRQn              (120)
+#define GPIO3_0_IRQn               (121)  /* All P3 I/O pins used as irq source    */
+#define GPIO3_1_IRQn               (122)  /* There are 4 pins in total             */
+#define GPIO3_2_IRQn               (123)
+#define GPIO3_3_IRQn               (124)
+#define UARTRX5_IRQn               (125)  /* UART 5 RX Interrupt                   */
+#define UARTTX5_IRQn               (126)  /* UART 5 TX Interrupt                   */
+#define UART5_IRQn                 (127)  /* UART 5 combined Interrupt             */
+/* #undef HDCLCD_IRQn */
+
+#endif /* PERIPHERAL_IRQS_H */
diff --git a/source/hal/source/platform/mps3/include/sse-300/peripheral_memmap.h b/source/hal/source/platform/mps3/include/sse-300/peripheral_memmap.h
new file mode 100644
index 0000000..e291d99
--- /dev/null
+++ b/source/hal/source/platform/mps3/include/sse-300/peripheral_memmap.h
@@ -0,0 +1,160 @@
+/*
+ * Copyright (c) 2022 Arm Limited. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef PERIPHERAL_MEMMAP_H
+#define PERIPHERAL_MEMMAP_H
+
+#define DESIGN_NAME              "Arm Corstone-300 - AN552"
+
+/******************************************************************************/
+/*                         Peripheral memory map                              */
+/******************************************************************************/
+
+#define CMSDK_GPIO0_BASE         (0x41100000)       /* User GPIO 0 Base Address   */
+#define CMSDK_GPIO1_BASE         (0x41101000)       /* User GPIO 1 Base Address   */
+#define CMSDK_GPIO2_BASE         (0x41102000)       /* User GPIO 2 Base Address   */
+#define CMSDK_GPIO3_BASE         (0x41103000)       /* User GPIO 3 Base Address   */
+
+#define FMC_CMDSK_GPIO_BASE0        (0x41104000)       /* FMC_CMDSK_GPIO_BASE 0 Base Address (4KB) */
+#define FMC_CMDSK_GPIO_BASE1        (0x41105000)       /* FMC_CMDSK_GPIO_BASE 1 Base Address (4KB)*/
+#define FMC_CMDSK_GPIO_BASE2        (0x41106000)       /* FMC_CMDSK_GPIO_BASE 2 Base Address (4KB)*/
+#define FMC_USER_AHB_BASE           (0x41107000)          /* FMC_USER_AHB_BASE     Base Address (4KB)*/
+
+#define DMA0_BASE                (0x41200000)       /* DMA0 (4KB) */
+#define DMA1_BASE                (0x41201000)       /* DMA1 (4KB) */
+#define DMA2_BASE                (0x41202000)       /* DMA2 (4KB) */
+#define DMA3_BASE                (0x41203000)       /* DMA3 (4KB) */
+
+#define USER_APB0_BASE           (0x41700000)       /* User APB0 */
+#define USER_APB1_BASE           (0x41701000)       /* User APB1 */
+#define USER_APB2_BASE           (0x41702000)       /* User APB2 */
+#define USER_APB3_BASE           (0x41703000)       /* User APB3 */
+
+#define MPS3_I2C0_BASE           (0x49200000)       /* Touch Screen I2C Base Address */
+#define MPS3_I2C1_BASE           (0x49201000)       /* Audio Interface I2C Base Address */
+#define MPS3_SSP2_BASE           (0x49202000)       /* ADC SPI PL022 Base Address   */
+#define MPS3_SSP3_BASE           (0x49203000)       /* Shield 0 SPI PL022 Base Address   */
+
+#define MPS3_SSP4_BASE           (0x49204000)       /* Shield 1 SPI PL022 Base Address   */
+#define MPS3_I2C2_BASE           (0x49205000)       /* Shield 0 SBCon Base Address */
+#define MPS3_I2C3_BASE           (0x49206000)       /* Shield 1 SBCon Base Address */
+
+#define USER_APB_BASE            (0x49207000)       /* User APB Base Address */
+/* #undef MPS3_I2C4_BASE */
+#define MPS3_I2C5_BASE           (0x49208000)       /* DDR EPROM I2C SBCon Base Address */
+#define MPS3_SCC_BASE            (0x49300000)       /* SCC Base Address    */
+#define MPS3_AAIC_I2S_BASE       (0x49301000)       /* Audio Interface I2S Base Address */
+#define MPS3_FPGAIO_BASE         (0x49302000)       /* FPGA IO Base Address */
+/* #undef PL011_UART0_BASE */
+#define CMSDK_UART0_BASE         (0x49303000)       /* UART 0 Base Address */
+#define CMSDK_UART1_BASE         (0x49304000)       /* UART 1 Base Address */
+#define CMSDK_UART2_BASE         (0x49305000)       /* UART 2 Base Address */
+#define CMSDK_UART3_BASE         (0x49306000)       /* UART 3 Base Address Shield 0*/
+
+#define ETHOS_U_NPU_BASE           (0x48102000)    /* Ethos-U NPU base address*/
+#define ETHOS_U_NPU_TA0_BASE       (0x48103000)    /* Ethos-U NPU's timing adapter 0 base address */
+#define ETHOS_U_NPU_TA1_BASE       (0x48103200)    /* Ethos-U NPU's timing adapter 1 base address */
+
+#define CMSDK_UART4_BASE         (0x49307000)       /* UART 4 Base Address Shield 1*/
+#define CMSDK_UART5_BASE         (0x49308000)       /* UART 5 Base Address */
+/* #undef HDMI_AUDIO_BASE */
+#define CLCD_CONFIG_BASE         (0x4930A000)       /* CLCD CONFIG Base Address */
+#define RTC_BASE                 (0x4930B000)       /* RTC Base address */
+#define SMSC9220_BASE            (0x41400000)       /* Ethernet SMSC9220 Base Address */
+#define USB_BASE                 (0x41500000)       /* USB Base Address */
+/* #undef CMSDK_SDIO_BASE */
+/* #undef MPS3_CLCD_BASE */
+/* #undef MPS3_eMMC_BASE */
+/* #undef USER_BASE */
+
+#define QSPI_XIP_BASE            (0x41800000)       /* QSPI XIP config Base Address */
+#define QSPI_WRITE_BASE          (0x41801000)       /* QSPI write config Base Address */
+
+/******************************************************************************/
+/*                      Secure Peripheral memory map                          */
+/******************************************************************************/
+
+#define MPC_ISRAM0_BASE_S        (0x50083000)       /* ISRAM0 Memory Protection Controller Secure base address */
+#define MPC_ISRAM1_BASE_S        (0x50084000)       /* ISRAM1 Memory Protection Controller Secure base address */
+
+#define SEC_CMSDK_GPIO0_BASE     (0x51100000)       /* User GPIO 0 Base Address   */
+#define SEC_CMSDK_GPIO1_BASE     (0x51101000)       /* User GPIO 0 Base Address   */
+#define SEC_CMSDK_GPIO2_BASE     (0x51102000)       /* User GPIO 0 Base Address   */
+#define SEC_CMSDK_GPIO3_BASE     (0x51103000)       /* User GPIO 0 Base Address   */
+
+#define SEC_AHB_USER0_BASE       (0x51104000)       /* AHB USER 0 Base Address (4KB) */
+#define SEC_AHB_USER1_BASE       (0x51105000)       /* AHB USER 1 Base Address (4KB)*/
+#define SEC_AHB_USER2_BASE       (0x51106000)       /* AHB USER 2 Base Address (4KB)*/
+#define SEC_AHB_USER3_BASE       (0x51107000)       /* AHB USER 3 Base Address (4KB)*/
+
+#define SEC_DMA0_BASE            (0x51200000)       /* DMA0 (4KB) */
+#define SEC_DMA1_BASE            (0x51201000)       /* DMA1 (4KB) */
+#define SEC_DMA2_BASE            (0x51202000)       /* DMA2 (4KB) */
+#define SEC_DMA3_BASE            (0x51203000)       /* DMA3 (4KB) */
+
+#define SEC_USER_APB0_BASE       (0x51700000)       /* User APB0 */
+#define SEC_USER_APB1_BASE       (0x51701000)       /* User APB1 */
+#define SEC_USER_APB2_BASE       (0x51702000)       /* User APB2 */
+#define SEC_USER_APB3_BASE       (0x51703000)       /* User APB3 */
+
+#define SEC_MPS3_I2C0_BASE       (0x59200000)       /* Touch Screen I2C Base Address */
+#define SEC_MPS3_I2C1_BASE       (0x59201000)       /* Audio Interface I2C Base Address */
+#define SEC_MPS3_SSP2_BASE       (0x59202000)       /* ADC SPI PL022 Base Address   */
+#define SEC_MPS3_SSP3_BASE       (0x59203000)       /* Shield 0 SPI PL022 Base Address   */
+
+#define SEC_MPS3_SSP4_BASE       (0x59204000)       /* Shield 1 SPI PL022 Base Address   */
+#define SEC_MPS3_I2C2_BASE       (0x59205000)       /* Shield 0 SBCon Base Address */
+#define SEC_MPS3_I2C3_BASE       (0x59206000)       /* Shield 1 SBCon Base Address */
+
+/* #undef SEC_MPS3_I2C4_BASE */
+#define SEC_MPS3_I2C5_BASE       (0x59208000)       /* DDR EPROM I2C SBCon Base Address */
+#define SEC_MPS3_SCC_BASE        (0x59300000)       /* SCC Base Address    */
+#define SEC_MPS3_AAIC_I2S_BASE   (0x59301000)       /* Audio Interface I2S Base Address */
+#define SEC_MPS3_FPGAIO_BASE     (0x59302000)       /* FPGA IO Base Address */
+#define SEC_CMSDK_UART0_BASE     (0x59303000)       /* UART 0 Base Address */
+#define SEC_CMSDK_UART1_BASE     (0x59304000)       /* UART 1 Base Address */
+#define SEC_CMSDK_UART2_BASE     (0x59305000)       /* UART 2 Base Address */
+#define SEC_CMSDK_UART3_BASE     (0x59306000)       /* UART 3 Base Address Shield 0*/
+
+#define SEC_CMSDK_UART4_BASE     (0x59307000)       /* UART 4 Base Address Shield 1*/
+#define SEC_CMSDK_UART5_BASE     (0x59308000)       /* UART 5 Base Address */
+/* #undef SEC_HDMI_AUDIO_BASE */
+#define SEC_CLCD_CONFIG_BASE     (0x5930A000)       /* CLCD CONFIG Base Address */
+#define SEC_RTC_BASE             (0x5930B000)       /* RTC Base address */
+#define SEC_SMSC9220_BASE        (0x51400000)       /* Ethernet SMSC9220 Base Address */
+#define SEC_USB_BASE             (0x51500000)       /* USB Base Address */
+
+#define SEC_ETHOS_U_NPU_BASE       (0x58102000)   /* Ethos-U NPU base address*/
+#define SEC_ETHOS_U_NPU_TA0_BASE   (0x58103000)   /* Ethos-U NPU's timing adapter 0 base address */
+#define SEC_ETHOS_U_NPU_TA1_BASE   (0x58103200)   /* Ethos-U NPU's timing adapter 1 base address */
+
+/* #undef SEC_USER_BASE */
+
+#define SEC_QSPI_XIP_BASE        (0x51800000)       /* QSPI XIP config Base Address */
+#define SEC_QSPI_WRITE_BASE      (0x51801000)       /* QSPI write config Base Address */
+
+/******************************************************************************/
+/*                                  MPCs                                      */
+/******************************************************************************/
+
+#define MPC_ISRAM0_BASE_S        (0x50083000)       /* Internal SRAM 0 MPC */
+#define MPC_ISRAM1_BASE_S        (0x50084000)       /* Internal SRAM 1 MPC */
+#define MPC_BRAM_BASE_S          (0x57000000)       /* SRAM Memory Protection Controller Secure base address */
+#define MPC_QSPI_BASE_S          (0x57001000)       /* QSPI Memory Protection Controller Secure base address */
+#define MPC_DDR4_BASE_S          (0x57002000)       /* DDR4 Memory Protection Controller Secure base address */
+
+#endif /* PERIPHERAL_MEMMAP_H */
diff --git a/source/hal/source/platform/mps3/source/platform_drivers.c b/source/hal/source/platform/mps3/source/platform_drivers.c
index 5de41c2..17ccdf2 100644
--- a/source/hal/source/platform/mps3/source/platform_drivers.c
+++ b/source/hal/source/platform/mps3/source/platform_drivers.c
@@ -30,6 +30,14 @@
 #include "ethosu_ta_init.h"
 #endif /* ETHOS_U_NPU_TIMING_ADAPTER_ENABLED */
 
+#if defined(ETHOS_U_BASE_ADDR)
+    #if (ETHOS_U_NPU_BASE != ETHOS_U_BASE_ADDR) && (SEC_ETHOS_U_NPU_BASE != ETHOS_U_BASE_ADDR)
+        #error "NPU component configured with incorrect NPU base address."
+    #endif /* (ETHOS_U_NPU_BASE != ETHOS_U_BASE_ADDR) && (SEC_ETHOS_U_NPU_BASE == ETHOS_U_BASE_ADDR) */
+#else
+    #error "ETHOS_U_BASE_ADDR should have been defined by the NPU component."
+#endif /* defined(ETHOS_U_BASE_ADDR) */
+
 #endif /* ARM_NPU */
 
 /**
diff --git a/source/hal/source/platform/native/CMakeLists.txt b/source/hal/source/platform/native/CMakeLists.txt
index fef5d5e..9673fef 100644
--- a/source/hal/source/platform/native/CMakeLists.txt
+++ b/source/hal/source/platform/native/CMakeLists.txt
@@ -45,11 +45,6 @@
     PRIVATE
     source/platform_drivers.c)
 
-## Platform definitions:
-target_compile_definitions(${PLATFORM_DRIVERS_TARGET}
-    PUBLIC
-    ACTIVATION_BUF_SRAM_SZ=0)
-
 ## Platform component directory
 if (NOT DEFINED COMPONENTS_DIR)
     set(COMPONENTS_DIR ${CMAKE_CURRENT_SOURCE_DIR}/../../components)
diff --git a/source/hal/source/platform/simple/CMakeLists.txt b/source/hal/source/platform/simple/CMakeLists.txt
index c8d4953..e11d9a9 100644
--- a/source/hal/source/platform/simple/CMakeLists.txt
+++ b/source/hal/source/platform/simple/CMakeLists.txt
@@ -30,42 +30,22 @@
     message(FATAL_ERROR "No ${PLATFORM_DRIVERS_TARGET} support for this target.")
 endif()
 
-# 2. Set the platform cmake descriptor file
-if (NOT DEFINED PLATFORM_CMAKE_DESCRIPTOR_FILE)
-    set(PLATFORM_CMAKE_DESCRIPTOR_FILE
-        ${CMAKE_CURRENT_SOURCE_DIR}/cmake/subsystem-profiles/simple_platform.cmake)
-endif()
-
-## Include the platform cmake descriptor file
-include(${PLATFORM_CMAKE_DESCRIPTOR_FILE})
-
 # Define target specific values here (before adding the components)
 set(UART0_BASE          "0x49303000"    CACHE STRING "UART base address")
 set(UART0_BAUDRATE      "115200"        CACHE STRING "UART baudrate")
 set(SYSTEM_CORE_CLOCK   "25000000"      CACHE STRING "System peripheral clock (Hz)")
-set(ACTIVATION_BUF_SRAM_SZ  "0x200000"  CACHE STRING "Maximum SRAM size for activation buffers")
+set(ETHOS_U_BASE_ADDR   "0x58102000"    CACHE STRING "Ethos-U NPU base address")
+set(ETHOS_U_IRQN        "56"            CACHE STRING "Ethos-U55 Interrupt")
+set(ETHOS_U_SEC_ENABLED  "1"            CACHE STRING "Ethos-U NPU Security enable")
+set(ETHOS_U_PRIV_ENABLED "1"            CACHE STRING "Ethos-U NPU Privilege enable")
 
-# 3. Generate sources:
-if (NOT DEFINED SOURCE_GEN_DIR)
-    set(SOURCE_GEN_DIR ${CMAKE_BINARY_DIR}/generated/bsp)
-endif()
-
-set(MEM_PROFILE_TEMPLATE ${CMAKE_CURRENT_SOURCE_DIR}/cmake/templates/peripheral_memmap.h.template)
-set(IRQ_PROFILE_TEMPLATE ${CMAKE_CURRENT_SOURCE_DIR}/cmake/templates/peripheral_irqs.h.template)
-set(MEM_REGIONS_TEMPLATE ${CMAKE_CURRENT_SOURCE_DIR}/cmake/templates/mem_regions.h.template)
-
-configure_file("${MEM_PROFILE_TEMPLATE}" "${SOURCE_GEN_DIR}/peripheral_memmap.h")
-configure_file("${IRQ_PROFILE_TEMPLATE}" "${SOURCE_GEN_DIR}/peripheral_irqs.h")
-configure_file("${MEM_REGIONS_TEMPLATE}" "${SOURCE_GEN_DIR}/mem_regions.h")
-
-# 4. Create static library
+# 2. Create static library
 add_library(${PLATFORM_DRIVERS_TARGET} STATIC)
 
 ## Include directories - public
 target_include_directories(${PLATFORM_DRIVERS_TARGET}
     PUBLIC
-    include
-    ${SOURCE_GEN_DIR})
+    include)
 
 ## Platform sources
 target_sources(${PLATFORM_DRIVERS_TARGET}
@@ -89,11 +69,6 @@
 ## Platform component: lcd
 add_subdirectory(${COMPONENTS_DIR}/lcd ${CMAKE_BINARY_DIR}/lcd)
 
-## Compile defs
-target_compile_definitions(${PLATFORM_DRIVERS_TARGET}
-    PUBLIC
-    ACTIVATION_BUF_SRAM_SZ=${ACTIVATION_BUF_SRAM_SZ})
-
 # Add dependencies:
 target_link_libraries(${PLATFORM_DRIVERS_TARGET}  PUBLIC
         cmsis_device
@@ -122,7 +97,7 @@
 
 endif()
 
-# 5. Display status:
+# 3. Display status:
 message(STATUS "CMAKE_CURRENT_SOURCE_DIR: " ${CMAKE_CURRENT_SOURCE_DIR})
 message(STATUS "*******************************************************")
 message(STATUS "Library                                : " ${PLATFORM_DRIVERS_TARGET})
diff --git a/source/hal/source/platform/simple/cmake/subsystem-profiles/simple_platform.cmake b/source/hal/source/platform/simple/cmake/subsystem-profiles/simple_platform.cmake
deleted file mode 100644
index e6cfef3..0000000
--- a/source/hal/source/platform/simple/cmake/subsystem-profiles/simple_platform.cmake
+++ /dev/null
@@ -1,93 +0,0 @@
-#----------------------------------------------------------------------------
-#  Copyright (c) 2021 Arm Limited. All rights reserved.
-#  SPDX-License-Identifier: Apache-2.0
-#
-#  Licensed under the Apache License, Version 2.0 (the "License");
-#  you may not use this file except in compliance with the License.
-#  You may obtain a copy of the License at
-#
-#      http://www.apache.org/licenses/LICENSE-2.0
-#
-#  Unless required by applicable law or agreed to in writing, software
-#  distributed under the License is distributed on an "AS IS" BASIS,
-#  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-#  See the License for the specific language governing permissions and
-#  limitations under the License.
-#----------------------------------------------------------------------------
-
-# CMake configuration file for peripheral memory map for simple platform. This is a stripped down
-# version of Arm Corstone-300 platform with minimal peripherals to be able to use Ethos-U55. However,
-# for ease of integration with Arm FastModel Tools, it uses PL011 as the UART component instead of
-# the CMSDK UART block used by the MPS3 FPGA and FVP implementations.
-###################################################################################################
-#                                         Mem sizes                                               #
-###################################################################################################
-set(ITCM_SIZE             "0x00080000" CACHE STRING "ITCM size:       512 kiB")
-set(DTCM_BLK_SIZE         "0x00020000" CACHE STRING "DTCM size:       128 kiB, 4 banks")
-set(BRAM_SIZE             "0x00100000" CACHE STRING "BRAM size:         1 MiB")
-set(ISRAM0_SIZE           "0x00100000" CACHE STRING "ISRAM0 size:       1 MiB")
-set(ISRAM1_SIZE           "0x00100000" CACHE STRING "ISRAM1 size:       1 MiB")
-set(DDR4_BLK_SIZE         "0x10000000" CACHE STRING "DDR4 block size: 256 MiB")
-
-###################################################################################################
-#                                Base addresses for memory regions                                #
-###################################################################################################
-set(ITCM_BASE_NS          "0x00000000" CACHE STRING "Instruction TCM Non-Secure base address")
-set(BRAM_BASE_NS          "0x01000000" CACHE STRING "CODE SRAM Non-Secure base address")
-set(DTCM0_BASE_NS         "0x20000000" CACHE STRING "Data TCM block 0 Non-Secure base address")
-set(DTCM1_BASE_NS         "0x20020000" CACHE STRING "Data TCM block 1 Non-Secure base address")
-set(DTCM2_BASE_NS         "0x20040000" CACHE STRING "Data TCM block 2 Non-Secure base address")
-set(DTCM3_BASE_NS         "0x20060000" CACHE STRING "Data TCM block 3 Non-Secure base address")
-set(ISRAM0_BASE_NS        "0x21000000" CACHE STRING "Internal SRAM Area Non-Secure base address")
-set(ISRAM1_BASE_NS        "0x21100000" CACHE STRING "Internal SRAM Area Non-Secure base address")
-set(QSPI_SRAM_BASE_NS     "0x28000000" CACHE STRING "QSPI SRAM Non-Secure base address")
-set(DDR4_BLK0_BASE_NS     "0x60000000" CACHE STRING "DDR4 block 0 Non-Secure base address")
-set(DDR4_BLK1_BASE_NS     "0x80000000" CACHE STRING "DDR4 block 1 Non-Secure base address")
-set(DDR4_BLK2_BASE_NS     "0xA0000000" CACHE STRING "DDR4 block 2 Non-Secure base address")
-set(DDR4_BLK3_BASE_NS     "0xC0000000" CACHE STRING "DDR4 block 3 Non-Secure base address")
-
-set(ITCM_BASE_S           "0x10000000" CACHE STRING "Instruction TCM Secure base address")
-set(BRAM_BASE_S           "0x11000000" CACHE STRING "CODE SRAM Secure base address")
-set(DTCM0_BASE_S          "0x30000000" CACHE STRING "Data TCM block 0 Secure base address")
-set(DTCM1_BASE_S          "0x30020000" CACHE STRING "Data TCM block 1 Secure base address")
-set(DTCM2_BASE_S          "0x30040000" CACHE STRING "Data TCM block 2 Secure base address")
-set(DTCM3_BASE_S          "0x30060000" CACHE STRING "Data TCM block 3 Secure base address")
-set(ISRAM0_BASE_S         "0x31000000" CACHE STRING "Internal SRAM Area Secure base address")
-set(ISRAM1_BASE_S         "0x31100000" CACHE STRING "Internal SRAM Area Secure base address")
-set(DDR4_BLK0_BASE_S      "0x70000000" CACHE STRING "DDR4 block 0 Secure base address")
-set(DDR4_BLK1_BASE_S      "0x90000000" CACHE STRING "DDR4 block 1 Secure base address")
-set(DDR4_BLK2_BASE_S      "0xB0000000" CACHE STRING "DDR4 block 2 Secure base address")
-set(DDR4_BLK3_BASE_S      "0xD0000000" CACHE STRING "DDR4 block 3 Secure base address")
-
-###################################################################################################
-#                              Application specific config                                        #
-###################################################################################################
-
-# This parameter is based on the linker/scatter script for simple platform. Do not change this
-# parameter in isolation.
-set(DESIGN_NAME            "Simple platform" CACHE STRING "Design name")
-
-# SRAM size reserved for activation buffers
-math(EXPR ACTIVATION_BUF_SRAM_SZ "${ISRAM0_SIZE} + ${ISRAM1_SIZE}" OUTPUT_FORMAT HEXADECIMAL)
-
-
-###################################################################################################
-#                                         Base addresses                                          #
-###################################################################################################
-set(PL011_UART0_BASE            "0x49303000" CACHE STRING "PL011 UART 0 Base Address")
-
-if (ETHOS_U_NPU_ENABLED)
-    set(ETHOS_U_NPU_BASE          "0x48102000" CACHE STRING "Ethos-U NPU base address")
-    set(ETHOS_U_NPU_TA0_BASE      "0x48103000" CACHE STRING "Ethos-U NPU's timing adapter 0 base address")
-    set(ETHOS_U_NPU_TA1_BASE      "0x48103200" CACHE STRING "Ethos-U NPU's timing adapter 1 base address")
-    set(SEC_ETHOS_U_NPU_BASE      "0x58102000" CACHE STRING "Ethos-U NPU base address")
-    set(SEC_ETHOS_U_NPU_TA0_BASE  "0x58103000" CACHE STRING "Ethos-U NPU's timing adapter 0 base address")
-    set(SEC_ETHOS_U_NPU_TA1_BASE  "0x58103200" CACHE STRING "Ethos-U NPU's timing adapter 1 base address")
-endif ()
-
-###################################################################################################
-#                                           IRQ numbers                                           #
-###################################################################################################
-if (ETHOS_U_NPU_ENABLED)
-    set(EthosU_IRQn             "56"         CACHE STRING "Ethos-U NPU Interrupt")
-endif ()
diff --git a/source/hal/source/platform/simple/cmake/templates/mem_regions.h.template b/source/hal/source/platform/simple/cmake/templates/mem_regions.h.template
deleted file mode 100644
index 72978ce..0000000
--- a/source/hal/source/platform/simple/cmake/templates/mem_regions.h.template
+++ /dev/null
@@ -1,58 +0,0 @@
-/*
- * Copyright (c) 2021 Arm Limited. All rights reserved.
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-// Auto-generated file
-// ** DO NOT EDIT **
-
-#ifndef MEM_REGION_DEFS_H
-#define MEM_REGION_DEFS_H
-
-#cmakedefine ITCM_SIZE             (@ITCM_SIZE@)     /* ITCM size */
-#cmakedefine DTCM_BLK_SIZE         (@DTCM_BLK_SIZE@)     /* DTCM size, 4 banks of this size available */
-#cmakedefine BRAM_SIZE             (@BRAM_SIZE@)     /* BRAM size */
-#cmakedefine ISRAM0_SIZE           (@ISRAM0_SIZE@)     /* ISRAM0 size */
-#cmakedefine ISRAM1_SIZE           (@ISRAM1_SIZE@)     /* ISRAM1 size */
-#cmakedefine QSPI_SRAM_SIZE        (@QSPI_SRAM_SIZE@)     /* QSPI Flash size */
-#cmakedefine DDR4_BLK_SIZE         (@DDR4_BLK_SIZE@)     /* DDR4 block size */
-
-#cmakedefine ITCM_BASE_NS          (@ITCM_BASE_NS@)     /* Instruction TCM Non-Secure base address */
-#cmakedefine BRAM_BASE_NS          (@BRAM_BASE_NS@)     /* CODE SRAM Non-Secure base address */
-#cmakedefine DTCM0_BASE_NS         (@DTCM0_BASE_NS@)     /* Data TCM block 0 Non-Secure base address */
-#cmakedefine DTCM1_BASE_NS         (@DTCM1_BASE_NS@)     /* Data TCM block 1 Non-Secure base address */
-#cmakedefine DTCM2_BASE_NS         (@DTCM2_BASE_NS@)     /* Data TCM block 2 Non-Secure base address */
-#cmakedefine DTCM3_BASE_NS         (@DTCM3_BASE_NS@)     /* Data TCM block 3 Non-Secure base address */
-#cmakedefine ISRAM0_BASE_NS        (@ISRAM0_BASE_NS@)     /* Internal SRAM Area Non-Secure base address */
-#cmakedefine ISRAM1_BASE_NS        (@ISRAM1_BASE_NS@)     /* Internal SRAM Area Non-Secure base address */
-#cmakedefine QSPI_SRAM_BASE_NS     (@QSPI_SRAM_BASE_NS@)     /* QSPI SRAM Non-Secure base address */
-#cmakedefine DDR4_BLK0_BASE_NS     (@DDR4_BLK0_BASE_NS@)     /* DDR4 block 0 Non-Secure base address */
-#cmakedefine DDR4_BLK1_BASE_NS     (@DDR4_BLK1_BASE_NS@)     /* DDR4 block 1 Non-Secure base address */
-#cmakedefine DDR4_BLK2_BASE_NS     (@DDR4_BLK2_BASE_NS@)     /* DDR4 block 2 Non-Secure base address */
-#cmakedefine DDR4_BLK3_BASE_NS     (@DDR4_BLK3_BASE_NS@)     /* DDR4 block 3 Non-Secure base address */
-
-#cmakedefine ITCM_BASE_S           (@ITCM_BASE_S@)     /* Instruction TCM Secure base address */
-#cmakedefine BRAM_BASE_S           (@BRAM_BASE_S@)     /* CODE SRAM Secure base address */
-#cmakedefine DTCM0_BASE_S          (@DTCM0_BASE_S@)     /* Data TCM block 0 Secure base address */
-#cmakedefine DTCM1_BASE_S          (@DTCM1_BASE_S@)     /* Data TCM block 1 Secure base address */
-#cmakedefine DTCM2_BASE_S          (@DTCM2_BASE_S@)     /* Data TCM block 2 Secure base address */
-#cmakedefine DTCM3_BASE_S          (@DTCM3_BASE_S@)     /* Data TCM block 3 Secure base address */
-#cmakedefine ISRAM0_BASE_S         (@ISRAM0_BASE_S@)     /* Internal SRAM Area Secure base address */
-#cmakedefine ISRAM1_BASE_S         (@ISRAM1_BASE_S@)     /* Internal SRAM Area Secure base address */
-#cmakedefine DDR4_BLK0_BASE_S      (@DDR4_BLK0_BASE_S@)     /* DDR4 block 0 Secure base address */
-#cmakedefine DDR4_BLK1_BASE_S      (@DDR4_BLK1_BASE_S@)     /* DDR4 block 1 Secure base address */
-#cmakedefine DDR4_BLK2_BASE_S      (@DDR4_BLK2_BASE_S@)     /* DDR4 block 2 Secure base address */
-#cmakedefine DDR4_BLK3_BASE_S      (@DDR4_BLK3_BASE_S@)     /* DDR4 block 3 Secure base address */
-
-#endif /*  MEM_REGION_DEFS_H  */
diff --git a/source/hal/source/platform/simple/cmake/templates/peripheral_memmap.h.template b/source/hal/source/platform/simple/cmake/templates/peripheral_memmap.h.template
deleted file mode 100644
index 2bfaafc..0000000
--- a/source/hal/source/platform/simple/cmake/templates/peripheral_memmap.h.template
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * Copyright (c) 2021 Arm Limited. All rights reserved.
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-// Auto-generated file
-// ** DO NOT EDIT **
-
-#ifndef PERIPHERAL_MEMMAP_H
-#define PERIPHERAL_MEMMAP_H
-
-#cmakedefine DESIGN_NAME              "@DESIGN_NAME@"
-
-/******************************************************************************/
-/*                         Peripheral memory map                              */
-/******************************************************************************/
-#cmakedefine PL011_UART0_BASE         (@PL011_UART0_BASE@)       /* PL011 UART0 Base Address */
-
-#cmakedefine ETHOS_U_NPU_BASE           (@ETHOS_U_NPU_BASE@)    /* Ethos-U NPU base address*/
-#cmakedefine ETHOS_U_NPU_TA0_BASE       (@ETHOS_U_NPU_TA0_BASE@)    /* Ethos-U NPU's timing adapter 0 base address */
-#cmakedefine ETHOS_U_NPU_TA1_BASE       (@ETHOS_U_NPU_TA1_BASE@)    /* Ethos-U NPU's timing adapter 1 base address */
-
-/******************************************************************************/
-/*                      Secure Peripheral memory map                          */
-/******************************************************************************/
-
-#cmakedefine SEC_ETHOS_U_NPU_BASE       (@SEC_ETHOS_U_NPU_BASE@)   /* Ethos-U NPU base address*/
-#cmakedefine SEC_ETHOS_U_NPU_TA0_BASE   (@SEC_ETHOS_U_NPU_TA0_BASE@)   /* Ethos-U NPU's timing adapter 0 base address */
-#cmakedefine SEC_ETHOS_U_NPU_TA1_BASE   (@SEC_ETHOS_U_NPU_TA1_BASE@)   /* Ethos-U NPU's timing adapter 1 base address */
-
-#endif /* PERIPHERAL_MEMMAP_H */
diff --git a/source/hal/source/platform/simple/cmake/templates/timing_adapter_settings.template b/source/hal/source/platform/simple/cmake/templates/timing_adapter_settings.template
deleted file mode 100644
index d5e202a..0000000
--- a/source/hal/source/platform/simple/cmake/templates/timing_adapter_settings.template
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
- * Copyright (c) 2021 Arm Limited. All rights reserved.
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-// Auto-generated file
-// ** DO NOT EDIT **
-
-#ifndef TIMING_ADAPTER_SETTINGS_H
-#define TIMING_ADAPTER_SETTINGS_H
-
-#cmakedefine TA0_BASE       (@TA0_BASE@)
-#cmakedefine TA1_BASE       (@TA1_BASE@)
-
-/* Timing adapter settings for AXI0 */
-#if defined(TA0_BASE)
-
-#define TA0_MAXR           (@TA0_MAXR@)
-#define TA0_MAXW           (@TA0_MAXW@)
-#define TA0_MAXRW          (@TA0_MAXRW@)
-#define TA0_RLATENCY       (@TA0_RLATENCY@)
-#define TA0_WLATENCY       (@TA0_WLATENCY@)
-#define TA0_PULSE_ON       (@TA0_PULSE_ON@)
-#define TA0_PULSE_OFF      (@TA0_PULSE_OFF@)
-#define TA0_BWCAP          (@TA0_BWCAP@)
-#define TA0_PERFCTRL       (@TA0_PERFCTRL@)
-#define TA0_PERFCNT        (@TA0_PERFCNT@)
-#define TA0_MODE           (@TA0_MODE@)
-#define TA0_HISTBIN        (@TA0_HISTBIN@)
-#define TA0_HISTCNT        (@TA0_HISTCNT@)
-
-#endif /* defined(TA0_BASE) */
-
-/* Timing adapter settings for AXI1 */
-#if defined(TA1_BASE)
-
-#define TA1_MAXR           (@TA1_MAXR@)
-#define TA1_MAXW           (@TA1_MAXW@)
-#define TA1_MAXRW          (@TA1_MAXRW@)
-#define TA1_RLATENCY       (@TA1_RLATENCY@)
-#define TA1_WLATENCY       (@TA1_WLATENCY@)
-#define TA1_PULSE_ON       (@TA1_PULSE_ON@)
-#define TA1_PULSE_OFF      (@TA1_PULSE_OFF@)
-#define TA1_BWCAP          (@TA1_BWCAP@)
-#define TA1_PERFCTRL       (@TA1_PERFCTRL@)
-#define TA1_PERFCNT        (@TA1_PERFCNT@)
-#define TA1_MODE           (@TA1_MODE@)
-#define TA1_HISTBIN        (@TA1_HISTBIN@)
-#define TA1_HISTCNT        (@TA1_HISTCNT@)
-
-#endif /* defined(TA1_BASE) */
-
-#endif /* TIMING_ADAPTER_SETTINGS_H */
\ No newline at end of file
diff --git a/source/hal/source/platform/simple/include/mem_regions.h b/source/hal/source/platform/simple/include/mem_regions.h
new file mode 100644
index 0000000..4d835a2
--- /dev/null
+++ b/source/hal/source/platform/simple/include/mem_regions.h
@@ -0,0 +1,55 @@
+/*
+ * Copyright (c) 2022 Arm Limited. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef MEM_REGION_DEFS_H
+#define MEM_REGION_DEFS_H
+
+#define ITCM_SIZE             (0x00080000)     /* ITCM size */
+#define DTCM_BLK_SIZE         (0x00020000)     /* DTCM size, 4 banks of this size available */
+#define BRAM_SIZE             (0x00100000)     /* BRAM size */
+#define ISRAM0_SIZE           (0x00100000)     /* ISRAM0 size */
+#define ISRAM1_SIZE           (0x00100000)     /* ISRAM1 size */
+#define DDR4_BLK_SIZE         (0x10000000)     /* DDR4 block size */
+
+#define ITCM_BASE_NS          (0x00000000)     /* Instruction TCM Non-Secure base address */
+#define BRAM_BASE_NS          (0x01000000)     /* CODE SRAM Non-Secure base address */
+#define DTCM0_BASE_NS         (0x20000000)     /* Data TCM block 0 Non-Secure base address */
+#define DTCM1_BASE_NS         (0x20020000)     /* Data TCM block 1 Non-Secure base address */
+#define DTCM2_BASE_NS         (0x20040000)     /* Data TCM block 2 Non-Secure base address */
+#define DTCM3_BASE_NS         (0x20060000)     /* Data TCM block 3 Non-Secure base address */
+#define ISRAM0_BASE_NS        (0x21000000)     /* Internal SRAM Area Non-Secure base address */
+#define ISRAM1_BASE_NS        (0x21100000)     /* Internal SRAM Area Non-Secure base address */
+#define QSPI_SRAM_BASE_NS     (0x28000000)     /* QSPI SRAM Non-Secure base address */
+#define DDR4_BLK0_BASE_NS     (0x60000000)     /* DDR4 block 0 Non-Secure base address */
+#define DDR4_BLK1_BASE_NS     (0x80000000)     /* DDR4 block 1 Non-Secure base address */
+#define DDR4_BLK2_BASE_NS     (0xA0000000)     /* DDR4 block 2 Non-Secure base address */
+#define DDR4_BLK3_BASE_NS     (0xC0000000)     /* DDR4 block 3 Non-Secure base address */
+
+#define ITCM_BASE_S           (0x10000000)     /* Instruction TCM Secure base address */
+#define BRAM_BASE_S           (0x11000000)     /* CODE SRAM Secure base address */
+#define DTCM0_BASE_S          (0x30000000)     /* Data TCM block 0 Secure base address */
+#define DTCM1_BASE_S          (0x30020000)     /* Data TCM block 1 Secure base address */
+#define DTCM2_BASE_S          (0x30040000)     /* Data TCM block 2 Secure base address */
+#define DTCM3_BASE_S          (0x30060000)     /* Data TCM block 3 Secure base address */
+#define ISRAM0_BASE_S         (0x31000000)     /* Internal SRAM Area Secure base address */
+#define ISRAM1_BASE_S         (0x31100000)     /* Internal SRAM Area Secure base address */
+#define DDR4_BLK0_BASE_S      (0x70000000)     /* DDR4 block 0 Secure base address */
+#define DDR4_BLK1_BASE_S      (0x90000000)     /* DDR4 block 1 Secure base address */
+#define DDR4_BLK2_BASE_S      (0xB0000000)     /* DDR4 block 2 Secure base address */
+#define DDR4_BLK3_BASE_S      (0xD0000000)     /* DDR4 block 3 Secure base address */
+
+#endif /*  MEM_REGION_DEFS_H  */
diff --git a/source/hal/source/platform/simple/cmake/templates/peripheral_irqs.h.template b/source/hal/source/platform/simple/include/peripheral_irqs.h
similarity index 82%
rename from source/hal/source/platform/simple/cmake/templates/peripheral_irqs.h.template
rename to source/hal/source/platform/simple/include/peripheral_irqs.h
index 8126cb4..9ffc675 100644
--- a/source/hal/source/platform/simple/cmake/templates/peripheral_irqs.h.template
+++ b/source/hal/source/platform/simple/include/peripheral_irqs.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2021 Arm Limited. All rights reserved.
+ * Copyright (c) 2022 Arm Limited. All rights reserved.
  * SPDX-License-Identifier: Apache-2.0
  *
  * Licensed under the Apache License, Version 2.0 (the "License");
@@ -14,8 +14,6 @@
  * See the License for the specific language governing permissions and
  * limitations under the License.
  */
-// Auto-generated file
-// ** DO NOT EDIT **
 
 #ifndef PERIPHERAL_IRQS_H
 #define PERIPHERAL_IRQS_H
@@ -24,6 +22,6 @@
 /*                    Peripheral interrupt numbers                            */
 /******************************************************************************/
 
-#cmakedefine EthosU_IRQn                (@EthosU_IRQn@)   /* Ethos-Uxx Interrupt */
+#define EthosU_IRQn                (56)   /* Ethos-Uxx Interrupt */
 
 #endif /* PERIPHERAL_IRQS_H */
diff --git a/source/hal/source/platform/simple/include/peripheral_memmap.h b/source/hal/source/platform/simple/include/peripheral_memmap.h
new file mode 100644
index 0000000..21f7765
--- /dev/null
+++ b/source/hal/source/platform/simple/include/peripheral_memmap.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2022 Arm Limited. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef PERIPHERAL_MEMMAP_H
+#define PERIPHERAL_MEMMAP_H
+
+#define DESIGN_NAME              "Simple platform"
+
+/******************************************************************************/
+/*                         Peripheral memory map                              */
+/******************************************************************************/
+#define PL011_UART0_BASE           (0x49303000)    /* PL011 UART0 Base Address */
+
+#define ETHOS_U_NPU_BASE           (0x48102000)    /* Ethos-U NPU base address*/
+#define ETHOS_U_NPU_TA0_BASE       (0x48103000)    /* Ethos-U NPU's timing adapter 0 base address */
+#define ETHOS_U_NPU_TA1_BASE       (0x48103200)    /* Ethos-U NPU's timing adapter 1 base address */
+
+/******************************************************************************/
+/*                      Secure Peripheral memory map                          */
+/******************************************************************************/
+
+#define SEC_ETHOS_U_NPU_BASE       (0x58102000)   /* Ethos-U NPU base address*/
+#define SEC_ETHOS_U_NPU_TA0_BASE   (0x58103000)   /* Ethos-U NPU's timing adapter 0 base address */
+#define SEC_ETHOS_U_NPU_TA1_BASE   (0x58103200)   /* Ethos-U NPU's timing adapter 1 base address */
+
+#endif /* PERIPHERAL_MEMMAP_H */
diff --git a/source/hal/source/platform/simple/source/platform_drivers.c b/source/hal/source/platform/simple/source/platform_drivers.c
index 19c0057..177ba70 100644
--- a/source/hal/source/platform/simple/source/platform_drivers.c
+++ b/source/hal/source/platform/simple/source/platform_drivers.c
@@ -30,6 +30,14 @@
 #include "ethosu_ta_init.h"
 #endif /* ETHOS_U_NPU_TIMING_ADAPTER_ENABLED */
 
+#if defined(ETHOS_U_BASE_ADDR)
+    #if (ETHOS_U_NPU_BASE != ETHOS_U_BASE_ADDR) && (SEC_ETHOS_U_NPU_BASE != ETHOS_U_BASE_ADDR)
+        #error "NPU component configured with incorrect NPU base address."
+    #endif /* (ETHOS_U_NPU_BASE != ETHOS_U_BASE_ADDR) && (SEC_ETHOS_U_NPU_BASE == ETHOS_U_BASE_ADDR) */
+#else
+    #error "ETHOS_U_BASE_ADDR should have been defined by the NPU component."
+#endif /* defined(ETHOS_U_BASE_ADDR) */
+
 #endif /* ARM_NPU */
 
 int platform_init(void)