MLECO-2917 Replacing platform CMake definitions with headers
Moving away from CMake description of targets and generation of
platform header files (for memory addresses and IRQ numbers).
Instead these headers are part of the repository under their
respective platform-driver packages under HAL sources.
Change-Id: I9bd3e68eb17385f8b93eb3d8d76b212ce0e1a6d5
Signed-off-by: Kshitij Sisodia <kshitij.sisodia@arm.com>
diff --git a/source/hal/source/platform/mps3/include/sse-300/mem_regions.h b/source/hal/source/platform/mps3/include/sse-300/mem_regions.h
new file mode 100644
index 0000000..c88ae3c
--- /dev/null
+++ b/source/hal/source/platform/mps3/include/sse-300/mem_regions.h
@@ -0,0 +1,56 @@
+/*
+ * Copyright (c) 2022 Arm Limited. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef MEM_REGION_DEFS_H
+#define MEM_REGION_DEFS_H
+
+#define ITCM_SIZE (0x00080000) /* ITCM size */
+#define DTCM_BLK_SIZE (0x00020000) /* DTCM size, 4 banks of this size available */
+#define BRAM_SIZE (0x00100000) /* BRAM size */
+#define ISRAM0_SIZE (0x00100000) /* ISRAM0 size */
+#define ISRAM1_SIZE (0x00100000) /* ISRAM1 size */
+#define QSPI_SRAM_SIZE (0x00800000) /* QSPI Flash size */
+#define DDR4_BLK_SIZE (0x10000000) /* DDR4 block size */
+
+#define ITCM_BASE_NS (0x00000000) /* Instruction TCM Non-Secure base address */
+#define BRAM_BASE_NS (0x01000000) /* CODE SRAM Non-Secure base address */
+#define DTCM0_BASE_NS (0x20000000) /* Data TCM block 0 Non-Secure base address */
+#define DTCM1_BASE_NS (0x20020000) /* Data TCM block 1 Non-Secure base address */
+#define DTCM2_BASE_NS (0x20040000) /* Data TCM block 2 Non-Secure base address */
+#define DTCM3_BASE_NS (0x20060000) /* Data TCM block 3 Non-Secure base address */
+#define ISRAM0_BASE_NS (0x21000000) /* Internal SRAM Area Non-Secure base address */
+#define ISRAM1_BASE_NS (0x21100000) /* Internal SRAM Area Non-Secure base address */
+#define QSPI_SRAM_BASE_NS (0x28000000) /* QSPI SRAM Non-Secure base address */
+#define DDR4_BLK0_BASE_NS (0x60000000) /* DDR4 block 0 Non-Secure base address */
+#define DDR4_BLK1_BASE_NS (0x80000000) /* DDR4 block 1 Non-Secure base address */
+#define DDR4_BLK2_BASE_NS (0xA0000000) /* DDR4 block 2 Non-Secure base address */
+#define DDR4_BLK3_BASE_NS (0xC0000000) /* DDR4 block 3 Non-Secure base address */
+
+#define ITCM_BASE_S (0x10000000) /* Instruction TCM Secure base address */
+#define BRAM_BASE_S (0x11000000) /* CODE SRAM Secure base address */
+#define DTCM0_BASE_S (0x30000000) /* Data TCM block 0 Secure base address */
+#define DTCM1_BASE_S (0x30020000) /* Data TCM block 1 Secure base address */
+#define DTCM2_BASE_S (0x30040000) /* Data TCM block 2 Secure base address */
+#define DTCM3_BASE_S (0x30060000) /* Data TCM block 3 Secure base address */
+#define ISRAM0_BASE_S (0x31000000) /* Internal SRAM Area Secure base address */
+#define ISRAM1_BASE_S (0x31100000) /* Internal SRAM Area Secure base address */
+#define DDR4_BLK0_BASE_S (0x70000000) /* DDR4 block 0 Secure base address */
+#define DDR4_BLK1_BASE_S (0x90000000) /* DDR4 block 1 Secure base address */
+#define DDR4_BLK2_BASE_S (0xB0000000) /* DDR4 block 2 Secure base address */
+#define DDR4_BLK3_BASE_S (0xD0000000) /* DDR4 block 3 Secure base address */
+
+#endif /* MEM_REGION_DEFS_H */
diff --git a/source/hal/source/platform/mps3/include/sse-300/peripheral_irqs.h b/source/hal/source/platform/mps3/include/sse-300/peripheral_irqs.h
new file mode 100644
index 0000000..431710b
--- /dev/null
+++ b/source/hal/source/platform/mps3/include/sse-300/peripheral_irqs.h
@@ -0,0 +1,136 @@
+/*
+ * Copyright (c) 2022 Arm Limited. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef PERIPHERAL_IRQS_H
+#define PERIPHERAL_IRQS_H
+
+/******************************************************************************/
+/* Peripheral interrupt numbers */
+/******************************************************************************/
+
+/* ------------------- Cortex-M Processor Exceptions Numbers -------------- */
+/* -14 to -1 should be defined by the system header */
+/* ---------------------- Core Specific Interrupt Numbers ------------------*/
+#define NONSEC_WATCHDOG_RESET_IRQn ( 0) /* Non-Secure Watchdog Reset Interrupt */
+#define NONSEC_WATCHDOG_IRQn ( 1) /* Non-Secure Watchdog Interrupt */
+#define S32K_TIMER_IRQn ( 2) /* S32K Timer Interrupt */
+#define TIMER0_IRQn ( 3) /* TIMER 0 Interrupt */
+#define TIMER1_IRQn ( 4) /* TIMER 1 Interrupt */
+#define TIMER2_IRQn ( 5) /* TIMER 2 Interrupt */
+#define MPC_IRQn ( 9) /* MPC Combined () Interrupt */
+#define PPC_IRQn (10) /* PPC Combined () Interrupt */
+#define MSC_IRQn (11) /* MSC Combined () Interrput */
+#define BRIDGE_ERROR_IRQn (12) /* Bridge Error Combined () Interrupt */
+#define MGMT_PPU_IRQn (14) /* MGMT_PPU */
+#define SYS_PPU_IRQn (15) /* SYS_PPU */
+#define CPU0_PPU_IRQn (16) /* CPU0_PPU */
+#define DEBUG_PPU_IRQn (26) /* DEBUG_PPU */
+#define TIMER3_AON_IRQn (27) /* TIMER3_AON */
+#define CPU0CTIIQ0_IRQn (28) /* CPU0CTIIQ0 */
+#define CPU0CTIIQ01_IRQn (29) /* CPU0CTIIQ01 */
+
+#define SYS_TSTAMP_COUNTER_IRQn (32) /* System timestamp counter interrupt */
+
+/* ---------------------- CMSDK Specific Interrupt Numbers ----------------- */
+#define UARTRX0_IRQn (33) /* UART 0 RX Interrupt */
+#define UARTTX0_IRQn (34) /* UART 0 TX Interrupt */
+#define UARTRX1_IRQn (35) /* UART 1 RX Interrupt */
+#define UARTTX1_IRQn (36) /* UART 1 TX Interrupt */
+#define UARTRX2_IRQn (37) /* UART 2 RX Interrupt */
+#define UARTTX2_IRQn (38) /* UART 2 TX Interrupt */
+#define UARTRX3_IRQn (39) /* UART 3 RX Interrupt */
+#define UARTTX3_IRQn (40) /* UART 3 TX Interrupt */
+#define UARTRX4_IRQn (41) /* UART 4 RX Interrupt */
+#define UARTTX4_IRQn (42) /* UART 4 TX Interrupt */
+#define UART0_IRQn (43) /* UART 0 combined Interrupt */
+#define UART1_IRQn (44) /* UART 1 combined Interrupt */
+#define UART2_IRQn (45) /* UART 2 combined Interrupt */
+#define UART3_IRQn (46) /* UART 3 combined Interrupt */
+#define UART4_IRQn (47) /* UART 4 combined Interrupt */
+#define UARTOVF_IRQn (48) /* UART 0,1,2,3 and 4 Overflow Interrupt */
+#define ETHERNET_IRQn (49) /* Ethernet Interrupt */
+#define I2S_IRQn (50) /* I2S Interrupt */
+#define TSC_IRQn (51) /* Touch Screen Interrupt */
+#define SPI2_IRQn (53) /* SPI 2 Interrupt */
+#define SPI3_IRQn (54) /* SPI 3 Interrupt */
+#define SPI4_IRQn (55) /* SPI 4 Interrupt */
+
+#define EthosU_IRQn (56) /* Ethos-Uxx Interrupt */
+
+#define GPIO0_IRQn (69) /* GPIO 0 Combined Interrupt */
+#define GPIO1_IRQn (70) /* GPIO 1 Combined Interrupt */
+#define GPIO2_IRQn (71) /* GPIO 2 Combined Interrupt */
+#define GPIO3_IRQn (72) /* GPIO 3 Combined Interrupt */
+
+#define GPIO0_0_IRQn (73) /* All P0 I/O pins used as irq source */
+#define GPIO0_1_IRQn (74) /* There are 16 pins in total */
+#define GPIO0_2_IRQn (75)
+#define GPIO0_3_IRQn (76)
+#define GPIO0_4_IRQn (77)
+#define GPIO0_5_IRQn (78)
+#define GPIO0_6_IRQn (79)
+#define GPIO0_7_IRQn (80)
+#define GPIO0_8_IRQn (81)
+#define GPIO0_9_IRQn (82)
+#define GPIO0_10_IRQn (83)
+#define GPIO0_11_IRQn (84)
+#define GPIO0_12_IRQn (85)
+#define GPIO0_13_IRQn (86)
+#define GPIO0_14_IRQn (87)
+#define GPIO0_15_IRQn (88)
+#define GPIO1_0_IRQn (89) /* All P1 I/O pins used as irq source */
+#define GPIO1_1_IRQn (90) /* There are 16 pins in total */
+#define GPIO1_2_IRQn (91)
+#define GPIO1_3_IRQn (92)
+#define GPIO1_4_IRQn (93)
+#define GPIO1_5_IRQn (94)
+#define GPIO1_6_IRQn (95)
+#define GPIO1_7_IRQn (96)
+#define GPIO1_8_IRQn (97)
+#define GPIO1_9_IRQn (98)
+#define GPIO1_10_IRQn (99)
+#define GPIO1_11_IRQn (100)
+#define GPIO1_12_IRQn (101)
+#define GPIO1_13_IRQn (102)
+#define GPIO1_14_IRQn (103)
+#define GPIO1_15_IRQn (104)
+#define GPIO2_0_IRQn (105) /* All P2 I/O pins used as irq source */
+#define GPIO2_1_IRQn (106) /* There are 15 pins in total */
+#define GPIO2_2_IRQn (107)
+#define GPIO2_3_IRQn (108)
+#define GPIO2_4_IRQn (109)
+#define GPIO2_5_IRQn (110)
+#define GPIO2_6_IRQn (111)
+#define GPIO2_7_IRQn (112)
+#define GPIO2_8_IRQn (113)
+#define GPIO2_9_IRQn (114)
+#define GPIO2_10_IRQn (115)
+#define GPIO2_11_IRQn (116)
+#define GPIO2_12_IRQn (117)
+#define GPIO2_13_IRQn (118)
+#define GPIO2_14_IRQn (119)
+#define GPIO2_15_IRQn (120)
+#define GPIO3_0_IRQn (121) /* All P3 I/O pins used as irq source */
+#define GPIO3_1_IRQn (122) /* There are 4 pins in total */
+#define GPIO3_2_IRQn (123)
+#define GPIO3_3_IRQn (124)
+#define UARTRX5_IRQn (125) /* UART 5 RX Interrupt */
+#define UARTTX5_IRQn (126) /* UART 5 TX Interrupt */
+#define UART5_IRQn (127) /* UART 5 combined Interrupt */
+/* #undef HDCLCD_IRQn */
+
+#endif /* PERIPHERAL_IRQS_H */
diff --git a/source/hal/source/platform/mps3/include/sse-300/peripheral_memmap.h b/source/hal/source/platform/mps3/include/sse-300/peripheral_memmap.h
new file mode 100644
index 0000000..e291d99
--- /dev/null
+++ b/source/hal/source/platform/mps3/include/sse-300/peripheral_memmap.h
@@ -0,0 +1,160 @@
+/*
+ * Copyright (c) 2022 Arm Limited. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef PERIPHERAL_MEMMAP_H
+#define PERIPHERAL_MEMMAP_H
+
+#define DESIGN_NAME "Arm Corstone-300 - AN552"
+
+/******************************************************************************/
+/* Peripheral memory map */
+/******************************************************************************/
+
+#define CMSDK_GPIO0_BASE (0x41100000) /* User GPIO 0 Base Address */
+#define CMSDK_GPIO1_BASE (0x41101000) /* User GPIO 1 Base Address */
+#define CMSDK_GPIO2_BASE (0x41102000) /* User GPIO 2 Base Address */
+#define CMSDK_GPIO3_BASE (0x41103000) /* User GPIO 3 Base Address */
+
+#define FMC_CMDSK_GPIO_BASE0 (0x41104000) /* FMC_CMDSK_GPIO_BASE 0 Base Address (4KB) */
+#define FMC_CMDSK_GPIO_BASE1 (0x41105000) /* FMC_CMDSK_GPIO_BASE 1 Base Address (4KB)*/
+#define FMC_CMDSK_GPIO_BASE2 (0x41106000) /* FMC_CMDSK_GPIO_BASE 2 Base Address (4KB)*/
+#define FMC_USER_AHB_BASE (0x41107000) /* FMC_USER_AHB_BASE Base Address (4KB)*/
+
+#define DMA0_BASE (0x41200000) /* DMA0 (4KB) */
+#define DMA1_BASE (0x41201000) /* DMA1 (4KB) */
+#define DMA2_BASE (0x41202000) /* DMA2 (4KB) */
+#define DMA3_BASE (0x41203000) /* DMA3 (4KB) */
+
+#define USER_APB0_BASE (0x41700000) /* User APB0 */
+#define USER_APB1_BASE (0x41701000) /* User APB1 */
+#define USER_APB2_BASE (0x41702000) /* User APB2 */
+#define USER_APB3_BASE (0x41703000) /* User APB3 */
+
+#define MPS3_I2C0_BASE (0x49200000) /* Touch Screen I2C Base Address */
+#define MPS3_I2C1_BASE (0x49201000) /* Audio Interface I2C Base Address */
+#define MPS3_SSP2_BASE (0x49202000) /* ADC SPI PL022 Base Address */
+#define MPS3_SSP3_BASE (0x49203000) /* Shield 0 SPI PL022 Base Address */
+
+#define MPS3_SSP4_BASE (0x49204000) /* Shield 1 SPI PL022 Base Address */
+#define MPS3_I2C2_BASE (0x49205000) /* Shield 0 SBCon Base Address */
+#define MPS3_I2C3_BASE (0x49206000) /* Shield 1 SBCon Base Address */
+
+#define USER_APB_BASE (0x49207000) /* User APB Base Address */
+/* #undef MPS3_I2C4_BASE */
+#define MPS3_I2C5_BASE (0x49208000) /* DDR EPROM I2C SBCon Base Address */
+#define MPS3_SCC_BASE (0x49300000) /* SCC Base Address */
+#define MPS3_AAIC_I2S_BASE (0x49301000) /* Audio Interface I2S Base Address */
+#define MPS3_FPGAIO_BASE (0x49302000) /* FPGA IO Base Address */
+/* #undef PL011_UART0_BASE */
+#define CMSDK_UART0_BASE (0x49303000) /* UART 0 Base Address */
+#define CMSDK_UART1_BASE (0x49304000) /* UART 1 Base Address */
+#define CMSDK_UART2_BASE (0x49305000) /* UART 2 Base Address */
+#define CMSDK_UART3_BASE (0x49306000) /* UART 3 Base Address Shield 0*/
+
+#define ETHOS_U_NPU_BASE (0x48102000) /* Ethos-U NPU base address*/
+#define ETHOS_U_NPU_TA0_BASE (0x48103000) /* Ethos-U NPU's timing adapter 0 base address */
+#define ETHOS_U_NPU_TA1_BASE (0x48103200) /* Ethos-U NPU's timing adapter 1 base address */
+
+#define CMSDK_UART4_BASE (0x49307000) /* UART 4 Base Address Shield 1*/
+#define CMSDK_UART5_BASE (0x49308000) /* UART 5 Base Address */
+/* #undef HDMI_AUDIO_BASE */
+#define CLCD_CONFIG_BASE (0x4930A000) /* CLCD CONFIG Base Address */
+#define RTC_BASE (0x4930B000) /* RTC Base address */
+#define SMSC9220_BASE (0x41400000) /* Ethernet SMSC9220 Base Address */
+#define USB_BASE (0x41500000) /* USB Base Address */
+/* #undef CMSDK_SDIO_BASE */
+/* #undef MPS3_CLCD_BASE */
+/* #undef MPS3_eMMC_BASE */
+/* #undef USER_BASE */
+
+#define QSPI_XIP_BASE (0x41800000) /* QSPI XIP config Base Address */
+#define QSPI_WRITE_BASE (0x41801000) /* QSPI write config Base Address */
+
+/******************************************************************************/
+/* Secure Peripheral memory map */
+/******************************************************************************/
+
+#define MPC_ISRAM0_BASE_S (0x50083000) /* ISRAM0 Memory Protection Controller Secure base address */
+#define MPC_ISRAM1_BASE_S (0x50084000) /* ISRAM1 Memory Protection Controller Secure base address */
+
+#define SEC_CMSDK_GPIO0_BASE (0x51100000) /* User GPIO 0 Base Address */
+#define SEC_CMSDK_GPIO1_BASE (0x51101000) /* User GPIO 0 Base Address */
+#define SEC_CMSDK_GPIO2_BASE (0x51102000) /* User GPIO 0 Base Address */
+#define SEC_CMSDK_GPIO3_BASE (0x51103000) /* User GPIO 0 Base Address */
+
+#define SEC_AHB_USER0_BASE (0x51104000) /* AHB USER 0 Base Address (4KB) */
+#define SEC_AHB_USER1_BASE (0x51105000) /* AHB USER 1 Base Address (4KB)*/
+#define SEC_AHB_USER2_BASE (0x51106000) /* AHB USER 2 Base Address (4KB)*/
+#define SEC_AHB_USER3_BASE (0x51107000) /* AHB USER 3 Base Address (4KB)*/
+
+#define SEC_DMA0_BASE (0x51200000) /* DMA0 (4KB) */
+#define SEC_DMA1_BASE (0x51201000) /* DMA1 (4KB) */
+#define SEC_DMA2_BASE (0x51202000) /* DMA2 (4KB) */
+#define SEC_DMA3_BASE (0x51203000) /* DMA3 (4KB) */
+
+#define SEC_USER_APB0_BASE (0x51700000) /* User APB0 */
+#define SEC_USER_APB1_BASE (0x51701000) /* User APB1 */
+#define SEC_USER_APB2_BASE (0x51702000) /* User APB2 */
+#define SEC_USER_APB3_BASE (0x51703000) /* User APB3 */
+
+#define SEC_MPS3_I2C0_BASE (0x59200000) /* Touch Screen I2C Base Address */
+#define SEC_MPS3_I2C1_BASE (0x59201000) /* Audio Interface I2C Base Address */
+#define SEC_MPS3_SSP2_BASE (0x59202000) /* ADC SPI PL022 Base Address */
+#define SEC_MPS3_SSP3_BASE (0x59203000) /* Shield 0 SPI PL022 Base Address */
+
+#define SEC_MPS3_SSP4_BASE (0x59204000) /* Shield 1 SPI PL022 Base Address */
+#define SEC_MPS3_I2C2_BASE (0x59205000) /* Shield 0 SBCon Base Address */
+#define SEC_MPS3_I2C3_BASE (0x59206000) /* Shield 1 SBCon Base Address */
+
+/* #undef SEC_MPS3_I2C4_BASE */
+#define SEC_MPS3_I2C5_BASE (0x59208000) /* DDR EPROM I2C SBCon Base Address */
+#define SEC_MPS3_SCC_BASE (0x59300000) /* SCC Base Address */
+#define SEC_MPS3_AAIC_I2S_BASE (0x59301000) /* Audio Interface I2S Base Address */
+#define SEC_MPS3_FPGAIO_BASE (0x59302000) /* FPGA IO Base Address */
+#define SEC_CMSDK_UART0_BASE (0x59303000) /* UART 0 Base Address */
+#define SEC_CMSDK_UART1_BASE (0x59304000) /* UART 1 Base Address */
+#define SEC_CMSDK_UART2_BASE (0x59305000) /* UART 2 Base Address */
+#define SEC_CMSDK_UART3_BASE (0x59306000) /* UART 3 Base Address Shield 0*/
+
+#define SEC_CMSDK_UART4_BASE (0x59307000) /* UART 4 Base Address Shield 1*/
+#define SEC_CMSDK_UART5_BASE (0x59308000) /* UART 5 Base Address */
+/* #undef SEC_HDMI_AUDIO_BASE */
+#define SEC_CLCD_CONFIG_BASE (0x5930A000) /* CLCD CONFIG Base Address */
+#define SEC_RTC_BASE (0x5930B000) /* RTC Base address */
+#define SEC_SMSC9220_BASE (0x51400000) /* Ethernet SMSC9220 Base Address */
+#define SEC_USB_BASE (0x51500000) /* USB Base Address */
+
+#define SEC_ETHOS_U_NPU_BASE (0x58102000) /* Ethos-U NPU base address*/
+#define SEC_ETHOS_U_NPU_TA0_BASE (0x58103000) /* Ethos-U NPU's timing adapter 0 base address */
+#define SEC_ETHOS_U_NPU_TA1_BASE (0x58103200) /* Ethos-U NPU's timing adapter 1 base address */
+
+/* #undef SEC_USER_BASE */
+
+#define SEC_QSPI_XIP_BASE (0x51800000) /* QSPI XIP config Base Address */
+#define SEC_QSPI_WRITE_BASE (0x51801000) /* QSPI write config Base Address */
+
+/******************************************************************************/
+/* MPCs */
+/******************************************************************************/
+
+#define MPC_ISRAM0_BASE_S (0x50083000) /* Internal SRAM 0 MPC */
+#define MPC_ISRAM1_BASE_S (0x50084000) /* Internal SRAM 1 MPC */
+#define MPC_BRAM_BASE_S (0x57000000) /* SRAM Memory Protection Controller Secure base address */
+#define MPC_QSPI_BASE_S (0x57001000) /* QSPI Memory Protection Controller Secure base address */
+#define MPC_DDR4_BASE_S (0x57002000) /* DDR4 Memory Protection Controller Secure base address */
+
+#endif /* PERIPHERAL_MEMMAP_H */