MLECO-2917 Replacing platform CMake definitions with headers
Moving away from CMake description of targets and generation of
platform header files (for memory addresses and IRQ numbers).
Instead these headers are part of the repository under their
respective platform-driver packages under HAL sources.
Change-Id: I9bd3e68eb17385f8b93eb3d8d76b212ce0e1a6d5
Signed-off-by: Kshitij Sisodia <kshitij.sisodia@arm.com>
diff --git a/source/hal/source/platform/simple/CMakeLists.txt b/source/hal/source/platform/simple/CMakeLists.txt
index c8d4953..e11d9a9 100644
--- a/source/hal/source/platform/simple/CMakeLists.txt
+++ b/source/hal/source/platform/simple/CMakeLists.txt
@@ -30,42 +30,22 @@
message(FATAL_ERROR "No ${PLATFORM_DRIVERS_TARGET} support for this target.")
endif()
-# 2. Set the platform cmake descriptor file
-if (NOT DEFINED PLATFORM_CMAKE_DESCRIPTOR_FILE)
- set(PLATFORM_CMAKE_DESCRIPTOR_FILE
- ${CMAKE_CURRENT_SOURCE_DIR}/cmake/subsystem-profiles/simple_platform.cmake)
-endif()
-
-## Include the platform cmake descriptor file
-include(${PLATFORM_CMAKE_DESCRIPTOR_FILE})
-
# Define target specific values here (before adding the components)
set(UART0_BASE "0x49303000" CACHE STRING "UART base address")
set(UART0_BAUDRATE "115200" CACHE STRING "UART baudrate")
set(SYSTEM_CORE_CLOCK "25000000" CACHE STRING "System peripheral clock (Hz)")
-set(ACTIVATION_BUF_SRAM_SZ "0x200000" CACHE STRING "Maximum SRAM size for activation buffers")
+set(ETHOS_U_BASE_ADDR "0x58102000" CACHE STRING "Ethos-U NPU base address")
+set(ETHOS_U_IRQN "56" CACHE STRING "Ethos-U55 Interrupt")
+set(ETHOS_U_SEC_ENABLED "1" CACHE STRING "Ethos-U NPU Security enable")
+set(ETHOS_U_PRIV_ENABLED "1" CACHE STRING "Ethos-U NPU Privilege enable")
-# 3. Generate sources:
-if (NOT DEFINED SOURCE_GEN_DIR)
- set(SOURCE_GEN_DIR ${CMAKE_BINARY_DIR}/generated/bsp)
-endif()
-
-set(MEM_PROFILE_TEMPLATE ${CMAKE_CURRENT_SOURCE_DIR}/cmake/templates/peripheral_memmap.h.template)
-set(IRQ_PROFILE_TEMPLATE ${CMAKE_CURRENT_SOURCE_DIR}/cmake/templates/peripheral_irqs.h.template)
-set(MEM_REGIONS_TEMPLATE ${CMAKE_CURRENT_SOURCE_DIR}/cmake/templates/mem_regions.h.template)
-
-configure_file("${MEM_PROFILE_TEMPLATE}" "${SOURCE_GEN_DIR}/peripheral_memmap.h")
-configure_file("${IRQ_PROFILE_TEMPLATE}" "${SOURCE_GEN_DIR}/peripheral_irqs.h")
-configure_file("${MEM_REGIONS_TEMPLATE}" "${SOURCE_GEN_DIR}/mem_regions.h")
-
-# 4. Create static library
+# 2. Create static library
add_library(${PLATFORM_DRIVERS_TARGET} STATIC)
## Include directories - public
target_include_directories(${PLATFORM_DRIVERS_TARGET}
PUBLIC
- include
- ${SOURCE_GEN_DIR})
+ include)
## Platform sources
target_sources(${PLATFORM_DRIVERS_TARGET}
@@ -89,11 +69,6 @@
## Platform component: lcd
add_subdirectory(${COMPONENTS_DIR}/lcd ${CMAKE_BINARY_DIR}/lcd)
-## Compile defs
-target_compile_definitions(${PLATFORM_DRIVERS_TARGET}
- PUBLIC
- ACTIVATION_BUF_SRAM_SZ=${ACTIVATION_BUF_SRAM_SZ})
-
# Add dependencies:
target_link_libraries(${PLATFORM_DRIVERS_TARGET} PUBLIC
cmsis_device
@@ -122,7 +97,7 @@
endif()
-# 5. Display status:
+# 3. Display status:
message(STATUS "CMAKE_CURRENT_SOURCE_DIR: " ${CMAKE_CURRENT_SOURCE_DIR})
message(STATUS "*******************************************************")
message(STATUS "Library : " ${PLATFORM_DRIVERS_TARGET})
diff --git a/source/hal/source/platform/simple/cmake/subsystem-profiles/simple_platform.cmake b/source/hal/source/platform/simple/cmake/subsystem-profiles/simple_platform.cmake
deleted file mode 100644
index e6cfef3..0000000
--- a/source/hal/source/platform/simple/cmake/subsystem-profiles/simple_platform.cmake
+++ /dev/null
@@ -1,93 +0,0 @@
-#----------------------------------------------------------------------------
-# Copyright (c) 2021 Arm Limited. All rights reserved.
-# SPDX-License-Identifier: Apache-2.0
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-# See the License for the specific language governing permissions and
-# limitations under the License.
-#----------------------------------------------------------------------------
-
-# CMake configuration file for peripheral memory map for simple platform. This is a stripped down
-# version of Arm Corstone-300 platform with minimal peripherals to be able to use Ethos-U55. However,
-# for ease of integration with Arm FastModel Tools, it uses PL011 as the UART component instead of
-# the CMSDK UART block used by the MPS3 FPGA and FVP implementations.
-###################################################################################################
-# Mem sizes #
-###################################################################################################
-set(ITCM_SIZE "0x00080000" CACHE STRING "ITCM size: 512 kiB")
-set(DTCM_BLK_SIZE "0x00020000" CACHE STRING "DTCM size: 128 kiB, 4 banks")
-set(BRAM_SIZE "0x00100000" CACHE STRING "BRAM size: 1 MiB")
-set(ISRAM0_SIZE "0x00100000" CACHE STRING "ISRAM0 size: 1 MiB")
-set(ISRAM1_SIZE "0x00100000" CACHE STRING "ISRAM1 size: 1 MiB")
-set(DDR4_BLK_SIZE "0x10000000" CACHE STRING "DDR4 block size: 256 MiB")
-
-###################################################################################################
-# Base addresses for memory regions #
-###################################################################################################
-set(ITCM_BASE_NS "0x00000000" CACHE STRING "Instruction TCM Non-Secure base address")
-set(BRAM_BASE_NS "0x01000000" CACHE STRING "CODE SRAM Non-Secure base address")
-set(DTCM0_BASE_NS "0x20000000" CACHE STRING "Data TCM block 0 Non-Secure base address")
-set(DTCM1_BASE_NS "0x20020000" CACHE STRING "Data TCM block 1 Non-Secure base address")
-set(DTCM2_BASE_NS "0x20040000" CACHE STRING "Data TCM block 2 Non-Secure base address")
-set(DTCM3_BASE_NS "0x20060000" CACHE STRING "Data TCM block 3 Non-Secure base address")
-set(ISRAM0_BASE_NS "0x21000000" CACHE STRING "Internal SRAM Area Non-Secure base address")
-set(ISRAM1_BASE_NS "0x21100000" CACHE STRING "Internal SRAM Area Non-Secure base address")
-set(QSPI_SRAM_BASE_NS "0x28000000" CACHE STRING "QSPI SRAM Non-Secure base address")
-set(DDR4_BLK0_BASE_NS "0x60000000" CACHE STRING "DDR4 block 0 Non-Secure base address")
-set(DDR4_BLK1_BASE_NS "0x80000000" CACHE STRING "DDR4 block 1 Non-Secure base address")
-set(DDR4_BLK2_BASE_NS "0xA0000000" CACHE STRING "DDR4 block 2 Non-Secure base address")
-set(DDR4_BLK3_BASE_NS "0xC0000000" CACHE STRING "DDR4 block 3 Non-Secure base address")
-
-set(ITCM_BASE_S "0x10000000" CACHE STRING "Instruction TCM Secure base address")
-set(BRAM_BASE_S "0x11000000" CACHE STRING "CODE SRAM Secure base address")
-set(DTCM0_BASE_S "0x30000000" CACHE STRING "Data TCM block 0 Secure base address")
-set(DTCM1_BASE_S "0x30020000" CACHE STRING "Data TCM block 1 Secure base address")
-set(DTCM2_BASE_S "0x30040000" CACHE STRING "Data TCM block 2 Secure base address")
-set(DTCM3_BASE_S "0x30060000" CACHE STRING "Data TCM block 3 Secure base address")
-set(ISRAM0_BASE_S "0x31000000" CACHE STRING "Internal SRAM Area Secure base address")
-set(ISRAM1_BASE_S "0x31100000" CACHE STRING "Internal SRAM Area Secure base address")
-set(DDR4_BLK0_BASE_S "0x70000000" CACHE STRING "DDR4 block 0 Secure base address")
-set(DDR4_BLK1_BASE_S "0x90000000" CACHE STRING "DDR4 block 1 Secure base address")
-set(DDR4_BLK2_BASE_S "0xB0000000" CACHE STRING "DDR4 block 2 Secure base address")
-set(DDR4_BLK3_BASE_S "0xD0000000" CACHE STRING "DDR4 block 3 Secure base address")
-
-###################################################################################################
-# Application specific config #
-###################################################################################################
-
-# This parameter is based on the linker/scatter script for simple platform. Do not change this
-# parameter in isolation.
-set(DESIGN_NAME "Simple platform" CACHE STRING "Design name")
-
-# SRAM size reserved for activation buffers
-math(EXPR ACTIVATION_BUF_SRAM_SZ "${ISRAM0_SIZE} + ${ISRAM1_SIZE}" OUTPUT_FORMAT HEXADECIMAL)
-
-
-###################################################################################################
-# Base addresses #
-###################################################################################################
-set(PL011_UART0_BASE "0x49303000" CACHE STRING "PL011 UART 0 Base Address")
-
-if (ETHOS_U_NPU_ENABLED)
- set(ETHOS_U_NPU_BASE "0x48102000" CACHE STRING "Ethos-U NPU base address")
- set(ETHOS_U_NPU_TA0_BASE "0x48103000" CACHE STRING "Ethos-U NPU's timing adapter 0 base address")
- set(ETHOS_U_NPU_TA1_BASE "0x48103200" CACHE STRING "Ethos-U NPU's timing adapter 1 base address")
- set(SEC_ETHOS_U_NPU_BASE "0x58102000" CACHE STRING "Ethos-U NPU base address")
- set(SEC_ETHOS_U_NPU_TA0_BASE "0x58103000" CACHE STRING "Ethos-U NPU's timing adapter 0 base address")
- set(SEC_ETHOS_U_NPU_TA1_BASE "0x58103200" CACHE STRING "Ethos-U NPU's timing adapter 1 base address")
-endif ()
-
-###################################################################################################
-# IRQ numbers #
-###################################################################################################
-if (ETHOS_U_NPU_ENABLED)
- set(EthosU_IRQn "56" CACHE STRING "Ethos-U NPU Interrupt")
-endif ()
diff --git a/source/hal/source/platform/simple/cmake/templates/mem_regions.h.template b/source/hal/source/platform/simple/cmake/templates/mem_regions.h.template
deleted file mode 100644
index 72978ce..0000000
--- a/source/hal/source/platform/simple/cmake/templates/mem_regions.h.template
+++ /dev/null
@@ -1,58 +0,0 @@
-/*
- * Copyright (c) 2021 Arm Limited. All rights reserved.
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-// Auto-generated file
-// ** DO NOT EDIT **
-
-#ifndef MEM_REGION_DEFS_H
-#define MEM_REGION_DEFS_H
-
-#cmakedefine ITCM_SIZE (@ITCM_SIZE@) /* ITCM size */
-#cmakedefine DTCM_BLK_SIZE (@DTCM_BLK_SIZE@) /* DTCM size, 4 banks of this size available */
-#cmakedefine BRAM_SIZE (@BRAM_SIZE@) /* BRAM size */
-#cmakedefine ISRAM0_SIZE (@ISRAM0_SIZE@) /* ISRAM0 size */
-#cmakedefine ISRAM1_SIZE (@ISRAM1_SIZE@) /* ISRAM1 size */
-#cmakedefine QSPI_SRAM_SIZE (@QSPI_SRAM_SIZE@) /* QSPI Flash size */
-#cmakedefine DDR4_BLK_SIZE (@DDR4_BLK_SIZE@) /* DDR4 block size */
-
-#cmakedefine ITCM_BASE_NS (@ITCM_BASE_NS@) /* Instruction TCM Non-Secure base address */
-#cmakedefine BRAM_BASE_NS (@BRAM_BASE_NS@) /* CODE SRAM Non-Secure base address */
-#cmakedefine DTCM0_BASE_NS (@DTCM0_BASE_NS@) /* Data TCM block 0 Non-Secure base address */
-#cmakedefine DTCM1_BASE_NS (@DTCM1_BASE_NS@) /* Data TCM block 1 Non-Secure base address */
-#cmakedefine DTCM2_BASE_NS (@DTCM2_BASE_NS@) /* Data TCM block 2 Non-Secure base address */
-#cmakedefine DTCM3_BASE_NS (@DTCM3_BASE_NS@) /* Data TCM block 3 Non-Secure base address */
-#cmakedefine ISRAM0_BASE_NS (@ISRAM0_BASE_NS@) /* Internal SRAM Area Non-Secure base address */
-#cmakedefine ISRAM1_BASE_NS (@ISRAM1_BASE_NS@) /* Internal SRAM Area Non-Secure base address */
-#cmakedefine QSPI_SRAM_BASE_NS (@QSPI_SRAM_BASE_NS@) /* QSPI SRAM Non-Secure base address */
-#cmakedefine DDR4_BLK0_BASE_NS (@DDR4_BLK0_BASE_NS@) /* DDR4 block 0 Non-Secure base address */
-#cmakedefine DDR4_BLK1_BASE_NS (@DDR4_BLK1_BASE_NS@) /* DDR4 block 1 Non-Secure base address */
-#cmakedefine DDR4_BLK2_BASE_NS (@DDR4_BLK2_BASE_NS@) /* DDR4 block 2 Non-Secure base address */
-#cmakedefine DDR4_BLK3_BASE_NS (@DDR4_BLK3_BASE_NS@) /* DDR4 block 3 Non-Secure base address */
-
-#cmakedefine ITCM_BASE_S (@ITCM_BASE_S@) /* Instruction TCM Secure base address */
-#cmakedefine BRAM_BASE_S (@BRAM_BASE_S@) /* CODE SRAM Secure base address */
-#cmakedefine DTCM0_BASE_S (@DTCM0_BASE_S@) /* Data TCM block 0 Secure base address */
-#cmakedefine DTCM1_BASE_S (@DTCM1_BASE_S@) /* Data TCM block 1 Secure base address */
-#cmakedefine DTCM2_BASE_S (@DTCM2_BASE_S@) /* Data TCM block 2 Secure base address */
-#cmakedefine DTCM3_BASE_S (@DTCM3_BASE_S@) /* Data TCM block 3 Secure base address */
-#cmakedefine ISRAM0_BASE_S (@ISRAM0_BASE_S@) /* Internal SRAM Area Secure base address */
-#cmakedefine ISRAM1_BASE_S (@ISRAM1_BASE_S@) /* Internal SRAM Area Secure base address */
-#cmakedefine DDR4_BLK0_BASE_S (@DDR4_BLK0_BASE_S@) /* DDR4 block 0 Secure base address */
-#cmakedefine DDR4_BLK1_BASE_S (@DDR4_BLK1_BASE_S@) /* DDR4 block 1 Secure base address */
-#cmakedefine DDR4_BLK2_BASE_S (@DDR4_BLK2_BASE_S@) /* DDR4 block 2 Secure base address */
-#cmakedefine DDR4_BLK3_BASE_S (@DDR4_BLK3_BASE_S@) /* DDR4 block 3 Secure base address */
-
-#endif /* MEM_REGION_DEFS_H */
diff --git a/source/hal/source/platform/simple/cmake/templates/peripheral_memmap.h.template b/source/hal/source/platform/simple/cmake/templates/peripheral_memmap.h.template
deleted file mode 100644
index 2bfaafc..0000000
--- a/source/hal/source/platform/simple/cmake/templates/peripheral_memmap.h.template
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * Copyright (c) 2021 Arm Limited. All rights reserved.
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-// Auto-generated file
-// ** DO NOT EDIT **
-
-#ifndef PERIPHERAL_MEMMAP_H
-#define PERIPHERAL_MEMMAP_H
-
-#cmakedefine DESIGN_NAME "@DESIGN_NAME@"
-
-/******************************************************************************/
-/* Peripheral memory map */
-/******************************************************************************/
-#cmakedefine PL011_UART0_BASE (@PL011_UART0_BASE@) /* PL011 UART0 Base Address */
-
-#cmakedefine ETHOS_U_NPU_BASE (@ETHOS_U_NPU_BASE@) /* Ethos-U NPU base address*/
-#cmakedefine ETHOS_U_NPU_TA0_BASE (@ETHOS_U_NPU_TA0_BASE@) /* Ethos-U NPU's timing adapter 0 base address */
-#cmakedefine ETHOS_U_NPU_TA1_BASE (@ETHOS_U_NPU_TA1_BASE@) /* Ethos-U NPU's timing adapter 1 base address */
-
-/******************************************************************************/
-/* Secure Peripheral memory map */
-/******************************************************************************/
-
-#cmakedefine SEC_ETHOS_U_NPU_BASE (@SEC_ETHOS_U_NPU_BASE@) /* Ethos-U NPU base address*/
-#cmakedefine SEC_ETHOS_U_NPU_TA0_BASE (@SEC_ETHOS_U_NPU_TA0_BASE@) /* Ethos-U NPU's timing adapter 0 base address */
-#cmakedefine SEC_ETHOS_U_NPU_TA1_BASE (@SEC_ETHOS_U_NPU_TA1_BASE@) /* Ethos-U NPU's timing adapter 1 base address */
-
-#endif /* PERIPHERAL_MEMMAP_H */
diff --git a/source/hal/source/platform/simple/cmake/templates/timing_adapter_settings.template b/source/hal/source/platform/simple/cmake/templates/timing_adapter_settings.template
deleted file mode 100644
index d5e202a..0000000
--- a/source/hal/source/platform/simple/cmake/templates/timing_adapter_settings.template
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
- * Copyright (c) 2021 Arm Limited. All rights reserved.
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-// Auto-generated file
-// ** DO NOT EDIT **
-
-#ifndef TIMING_ADAPTER_SETTINGS_H
-#define TIMING_ADAPTER_SETTINGS_H
-
-#cmakedefine TA0_BASE (@TA0_BASE@)
-#cmakedefine TA1_BASE (@TA1_BASE@)
-
-/* Timing adapter settings for AXI0 */
-#if defined(TA0_BASE)
-
-#define TA0_MAXR (@TA0_MAXR@)
-#define TA0_MAXW (@TA0_MAXW@)
-#define TA0_MAXRW (@TA0_MAXRW@)
-#define TA0_RLATENCY (@TA0_RLATENCY@)
-#define TA0_WLATENCY (@TA0_WLATENCY@)
-#define TA0_PULSE_ON (@TA0_PULSE_ON@)
-#define TA0_PULSE_OFF (@TA0_PULSE_OFF@)
-#define TA0_BWCAP (@TA0_BWCAP@)
-#define TA0_PERFCTRL (@TA0_PERFCTRL@)
-#define TA0_PERFCNT (@TA0_PERFCNT@)
-#define TA0_MODE (@TA0_MODE@)
-#define TA0_HISTBIN (@TA0_HISTBIN@)
-#define TA0_HISTCNT (@TA0_HISTCNT@)
-
-#endif /* defined(TA0_BASE) */
-
-/* Timing adapter settings for AXI1 */
-#if defined(TA1_BASE)
-
-#define TA1_MAXR (@TA1_MAXR@)
-#define TA1_MAXW (@TA1_MAXW@)
-#define TA1_MAXRW (@TA1_MAXRW@)
-#define TA1_RLATENCY (@TA1_RLATENCY@)
-#define TA1_WLATENCY (@TA1_WLATENCY@)
-#define TA1_PULSE_ON (@TA1_PULSE_ON@)
-#define TA1_PULSE_OFF (@TA1_PULSE_OFF@)
-#define TA1_BWCAP (@TA1_BWCAP@)
-#define TA1_PERFCTRL (@TA1_PERFCTRL@)
-#define TA1_PERFCNT (@TA1_PERFCNT@)
-#define TA1_MODE (@TA1_MODE@)
-#define TA1_HISTBIN (@TA1_HISTBIN@)
-#define TA1_HISTCNT (@TA1_HISTCNT@)
-
-#endif /* defined(TA1_BASE) */
-
-#endif /* TIMING_ADAPTER_SETTINGS_H */
\ No newline at end of file
diff --git a/source/hal/source/platform/simple/include/mem_regions.h b/source/hal/source/platform/simple/include/mem_regions.h
new file mode 100644
index 0000000..4d835a2
--- /dev/null
+++ b/source/hal/source/platform/simple/include/mem_regions.h
@@ -0,0 +1,55 @@
+/*
+ * Copyright (c) 2022 Arm Limited. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef MEM_REGION_DEFS_H
+#define MEM_REGION_DEFS_H
+
+#define ITCM_SIZE (0x00080000) /* ITCM size */
+#define DTCM_BLK_SIZE (0x00020000) /* DTCM size, 4 banks of this size available */
+#define BRAM_SIZE (0x00100000) /* BRAM size */
+#define ISRAM0_SIZE (0x00100000) /* ISRAM0 size */
+#define ISRAM1_SIZE (0x00100000) /* ISRAM1 size */
+#define DDR4_BLK_SIZE (0x10000000) /* DDR4 block size */
+
+#define ITCM_BASE_NS (0x00000000) /* Instruction TCM Non-Secure base address */
+#define BRAM_BASE_NS (0x01000000) /* CODE SRAM Non-Secure base address */
+#define DTCM0_BASE_NS (0x20000000) /* Data TCM block 0 Non-Secure base address */
+#define DTCM1_BASE_NS (0x20020000) /* Data TCM block 1 Non-Secure base address */
+#define DTCM2_BASE_NS (0x20040000) /* Data TCM block 2 Non-Secure base address */
+#define DTCM3_BASE_NS (0x20060000) /* Data TCM block 3 Non-Secure base address */
+#define ISRAM0_BASE_NS (0x21000000) /* Internal SRAM Area Non-Secure base address */
+#define ISRAM1_BASE_NS (0x21100000) /* Internal SRAM Area Non-Secure base address */
+#define QSPI_SRAM_BASE_NS (0x28000000) /* QSPI SRAM Non-Secure base address */
+#define DDR4_BLK0_BASE_NS (0x60000000) /* DDR4 block 0 Non-Secure base address */
+#define DDR4_BLK1_BASE_NS (0x80000000) /* DDR4 block 1 Non-Secure base address */
+#define DDR4_BLK2_BASE_NS (0xA0000000) /* DDR4 block 2 Non-Secure base address */
+#define DDR4_BLK3_BASE_NS (0xC0000000) /* DDR4 block 3 Non-Secure base address */
+
+#define ITCM_BASE_S (0x10000000) /* Instruction TCM Secure base address */
+#define BRAM_BASE_S (0x11000000) /* CODE SRAM Secure base address */
+#define DTCM0_BASE_S (0x30000000) /* Data TCM block 0 Secure base address */
+#define DTCM1_BASE_S (0x30020000) /* Data TCM block 1 Secure base address */
+#define DTCM2_BASE_S (0x30040000) /* Data TCM block 2 Secure base address */
+#define DTCM3_BASE_S (0x30060000) /* Data TCM block 3 Secure base address */
+#define ISRAM0_BASE_S (0x31000000) /* Internal SRAM Area Secure base address */
+#define ISRAM1_BASE_S (0x31100000) /* Internal SRAM Area Secure base address */
+#define DDR4_BLK0_BASE_S (0x70000000) /* DDR4 block 0 Secure base address */
+#define DDR4_BLK1_BASE_S (0x90000000) /* DDR4 block 1 Secure base address */
+#define DDR4_BLK2_BASE_S (0xB0000000) /* DDR4 block 2 Secure base address */
+#define DDR4_BLK3_BASE_S (0xD0000000) /* DDR4 block 3 Secure base address */
+
+#endif /* MEM_REGION_DEFS_H */
diff --git a/source/hal/source/platform/simple/cmake/templates/peripheral_irqs.h.template b/source/hal/source/platform/simple/include/peripheral_irqs.h
similarity index 82%
rename from source/hal/source/platform/simple/cmake/templates/peripheral_irqs.h.template
rename to source/hal/source/platform/simple/include/peripheral_irqs.h
index 8126cb4..9ffc675 100644
--- a/source/hal/source/platform/simple/cmake/templates/peripheral_irqs.h.template
+++ b/source/hal/source/platform/simple/include/peripheral_irqs.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021 Arm Limited. All rights reserved.
+ * Copyright (c) 2022 Arm Limited. All rights reserved.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@@ -14,8 +14,6 @@
* See the License for the specific language governing permissions and
* limitations under the License.
*/
-// Auto-generated file
-// ** DO NOT EDIT **
#ifndef PERIPHERAL_IRQS_H
#define PERIPHERAL_IRQS_H
@@ -24,6 +22,6 @@
/* Peripheral interrupt numbers */
/******************************************************************************/
-#cmakedefine EthosU_IRQn (@EthosU_IRQn@) /* Ethos-Uxx Interrupt */
+#define EthosU_IRQn (56) /* Ethos-Uxx Interrupt */
#endif /* PERIPHERAL_IRQS_H */
diff --git a/source/hal/source/platform/simple/include/peripheral_memmap.h b/source/hal/source/platform/simple/include/peripheral_memmap.h
new file mode 100644
index 0000000..21f7765
--- /dev/null
+++ b/source/hal/source/platform/simple/include/peripheral_memmap.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2022 Arm Limited. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef PERIPHERAL_MEMMAP_H
+#define PERIPHERAL_MEMMAP_H
+
+#define DESIGN_NAME "Simple platform"
+
+/******************************************************************************/
+/* Peripheral memory map */
+/******************************************************************************/
+#define PL011_UART0_BASE (0x49303000) /* PL011 UART0 Base Address */
+
+#define ETHOS_U_NPU_BASE (0x48102000) /* Ethos-U NPU base address*/
+#define ETHOS_U_NPU_TA0_BASE (0x48103000) /* Ethos-U NPU's timing adapter 0 base address */
+#define ETHOS_U_NPU_TA1_BASE (0x48103200) /* Ethos-U NPU's timing adapter 1 base address */
+
+/******************************************************************************/
+/* Secure Peripheral memory map */
+/******************************************************************************/
+
+#define SEC_ETHOS_U_NPU_BASE (0x58102000) /* Ethos-U NPU base address*/
+#define SEC_ETHOS_U_NPU_TA0_BASE (0x58103000) /* Ethos-U NPU's timing adapter 0 base address */
+#define SEC_ETHOS_U_NPU_TA1_BASE (0x58103200) /* Ethos-U NPU's timing adapter 1 base address */
+
+#endif /* PERIPHERAL_MEMMAP_H */
diff --git a/source/hal/source/platform/simple/source/platform_drivers.c b/source/hal/source/platform/simple/source/platform_drivers.c
index 19c0057..177ba70 100644
--- a/source/hal/source/platform/simple/source/platform_drivers.c
+++ b/source/hal/source/platform/simple/source/platform_drivers.c
@@ -30,6 +30,14 @@
#include "ethosu_ta_init.h"
#endif /* ETHOS_U_NPU_TIMING_ADAPTER_ENABLED */
+#if defined(ETHOS_U_BASE_ADDR)
+ #if (ETHOS_U_NPU_BASE != ETHOS_U_BASE_ADDR) && (SEC_ETHOS_U_NPU_BASE != ETHOS_U_BASE_ADDR)
+ #error "NPU component configured with incorrect NPU base address."
+ #endif /* (ETHOS_U_NPU_BASE != ETHOS_U_BASE_ADDR) && (SEC_ETHOS_U_NPU_BASE == ETHOS_U_BASE_ADDR) */
+#else
+ #error "ETHOS_U_BASE_ADDR should have been defined by the NPU component."
+#endif /* defined(ETHOS_U_BASE_ADDR) */
+
#endif /* ARM_NPU */
int platform_init(void)