MLECO-2917 Replacing platform CMake definitions with headers
Moving away from CMake description of targets and generation of
platform header files (for memory addresses and IRQ numbers).
Instead these headers are part of the repository under their
respective platform-driver packages under HAL sources.
Change-Id: I9bd3e68eb17385f8b93eb3d8d76b212ce0e1a6d5
Signed-off-by: Kshitij Sisodia <kshitij.sisodia@arm.com>
diff --git a/source/hal/source/platform/simple/include/mem_regions.h b/source/hal/source/platform/simple/include/mem_regions.h
new file mode 100644
index 0000000..4d835a2
--- /dev/null
+++ b/source/hal/source/platform/simple/include/mem_regions.h
@@ -0,0 +1,55 @@
+/*
+ * Copyright (c) 2022 Arm Limited. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef MEM_REGION_DEFS_H
+#define MEM_REGION_DEFS_H
+
+#define ITCM_SIZE (0x00080000) /* ITCM size */
+#define DTCM_BLK_SIZE (0x00020000) /* DTCM size, 4 banks of this size available */
+#define BRAM_SIZE (0x00100000) /* BRAM size */
+#define ISRAM0_SIZE (0x00100000) /* ISRAM0 size */
+#define ISRAM1_SIZE (0x00100000) /* ISRAM1 size */
+#define DDR4_BLK_SIZE (0x10000000) /* DDR4 block size */
+
+#define ITCM_BASE_NS (0x00000000) /* Instruction TCM Non-Secure base address */
+#define BRAM_BASE_NS (0x01000000) /* CODE SRAM Non-Secure base address */
+#define DTCM0_BASE_NS (0x20000000) /* Data TCM block 0 Non-Secure base address */
+#define DTCM1_BASE_NS (0x20020000) /* Data TCM block 1 Non-Secure base address */
+#define DTCM2_BASE_NS (0x20040000) /* Data TCM block 2 Non-Secure base address */
+#define DTCM3_BASE_NS (0x20060000) /* Data TCM block 3 Non-Secure base address */
+#define ISRAM0_BASE_NS (0x21000000) /* Internal SRAM Area Non-Secure base address */
+#define ISRAM1_BASE_NS (0x21100000) /* Internal SRAM Area Non-Secure base address */
+#define QSPI_SRAM_BASE_NS (0x28000000) /* QSPI SRAM Non-Secure base address */
+#define DDR4_BLK0_BASE_NS (0x60000000) /* DDR4 block 0 Non-Secure base address */
+#define DDR4_BLK1_BASE_NS (0x80000000) /* DDR4 block 1 Non-Secure base address */
+#define DDR4_BLK2_BASE_NS (0xA0000000) /* DDR4 block 2 Non-Secure base address */
+#define DDR4_BLK3_BASE_NS (0xC0000000) /* DDR4 block 3 Non-Secure base address */
+
+#define ITCM_BASE_S (0x10000000) /* Instruction TCM Secure base address */
+#define BRAM_BASE_S (0x11000000) /* CODE SRAM Secure base address */
+#define DTCM0_BASE_S (0x30000000) /* Data TCM block 0 Secure base address */
+#define DTCM1_BASE_S (0x30020000) /* Data TCM block 1 Secure base address */
+#define DTCM2_BASE_S (0x30040000) /* Data TCM block 2 Secure base address */
+#define DTCM3_BASE_S (0x30060000) /* Data TCM block 3 Secure base address */
+#define ISRAM0_BASE_S (0x31000000) /* Internal SRAM Area Secure base address */
+#define ISRAM1_BASE_S (0x31100000) /* Internal SRAM Area Secure base address */
+#define DDR4_BLK0_BASE_S (0x70000000) /* DDR4 block 0 Secure base address */
+#define DDR4_BLK1_BASE_S (0x90000000) /* DDR4 block 1 Secure base address */
+#define DDR4_BLK2_BASE_S (0xB0000000) /* DDR4 block 2 Secure base address */
+#define DDR4_BLK3_BASE_S (0xD0000000) /* DDR4 block 3 Secure base address */
+
+#endif /* MEM_REGION_DEFS_H */
diff --git a/source/hal/source/platform/simple/include/peripheral_irqs.h b/source/hal/source/platform/simple/include/peripheral_irqs.h
new file mode 100644
index 0000000..9ffc675
--- /dev/null
+++ b/source/hal/source/platform/simple/include/peripheral_irqs.h
@@ -0,0 +1,27 @@
+/*
+ * Copyright (c) 2022 Arm Limited. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef PERIPHERAL_IRQS_H
+#define PERIPHERAL_IRQS_H
+
+/******************************************************************************/
+/* Peripheral interrupt numbers */
+/******************************************************************************/
+
+#define EthosU_IRQn (56) /* Ethos-Uxx Interrupt */
+
+#endif /* PERIPHERAL_IRQS_H */
diff --git a/source/hal/source/platform/simple/include/peripheral_memmap.h b/source/hal/source/platform/simple/include/peripheral_memmap.h
new file mode 100644
index 0000000..21f7765
--- /dev/null
+++ b/source/hal/source/platform/simple/include/peripheral_memmap.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright (c) 2022 Arm Limited. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef PERIPHERAL_MEMMAP_H
+#define PERIPHERAL_MEMMAP_H
+
+#define DESIGN_NAME "Simple platform"
+
+/******************************************************************************/
+/* Peripheral memory map */
+/******************************************************************************/
+#define PL011_UART0_BASE (0x49303000) /* PL011 UART0 Base Address */
+
+#define ETHOS_U_NPU_BASE (0x48102000) /* Ethos-U NPU base address*/
+#define ETHOS_U_NPU_TA0_BASE (0x48103000) /* Ethos-U NPU's timing adapter 0 base address */
+#define ETHOS_U_NPU_TA1_BASE (0x48103200) /* Ethos-U NPU's timing adapter 1 base address */
+
+/******************************************************************************/
+/* Secure Peripheral memory map */
+/******************************************************************************/
+
+#define SEC_ETHOS_U_NPU_BASE (0x58102000) /* Ethos-U NPU base address*/
+#define SEC_ETHOS_U_NPU_TA0_BASE (0x58103000) /* Ethos-U NPU's timing adapter 0 base address */
+#define SEC_ETHOS_U_NPU_TA1_BASE (0x58103200) /* Ethos-U NPU's timing adapter 1 base address */
+
+#endif /* PERIPHERAL_MEMMAP_H */