MLECO-2985 Adding Corstone-310 support

Change-Id: Ifa4b11154478355c10cb3e747b9938a74afd242b
Signed-off-by: Eanna O Cathain <eanna.ocathain@arm.com>
diff --git a/CMakeLists.txt b/CMakeLists.txt
index c51d0af..feb69b6 100644
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@@ -14,7 +14,7 @@
 #  See the License for the specific language governing permissions and
 #  limitations under the License.
 #----------------------------------------------------------------------------
-cmake_minimum_required(VERSION 3.15.6)
+cmake_minimum_required(VERSION 3.16.3)
 include(ExternalProject)
 
 # Build in release mode by default
diff --git a/docs/sections/appendix.md b/docs/sections/appendix.md
index 555560f..46b838a 100644
--- a/docs/sections/appendix.md
+++ b/docs/sections/appendix.md
@@ -6,15 +6,33 @@
 
 | Name  | Base address | Limit address |  Size     | IDAU |  Remarks                                                  |
 |-------|--------------|---------------|-----------|------|-----------------------------------------------------------|
-| ITCM  | 0x0000_0000  |  0x0007_FFFF  |   512 kiB |  NS  |   ITCM code region                                        |
-| BRAM  | 0x0100_0000  |  0x0120_0000  |   2 MiB   |  NS  |   FPGA data SRAM region                                   |
+| ITCM  | 0x0000_0000  |  0x0007_FFFF  |  512 kiB  |  NS  |   ITCM code region                                        |
+| BRAM  | 0x0100_0000  |  0x0110_0000  |   1 MiB   |  NS  |   FPGA data SRAM region                                   |
 | DTCM  | 0x2000_0000  |  0x2007_FFFF  |  512 kiB  |  NS  |   4 banks for 128 kiB each                                |
-| SRAM  | 0x2100_0000  |  0x213F_FFFF  |  4 MiB    |  NS  |   2 banks of 2 MiB each as SSE-300 internal SRAM region   |
+| SRAM  | 0x2100_0000  |  0x2120_0000  |   2 MiB   |  NS  |   2 banks of 1 MiB each as SSE-300 internal SRAM region   |
 | DDR   | 0x6000_0000  |  0x6FFF_FFFF  |   256 MiB |  NS  |   DDR memory region                                       |
 | ITCM  | 0x1000_0000  |  0x1007_FFFF  |   512 kiB |  S   |   ITCM code region                                        |
-| BRAM  | 0x1100_0000  |  0x1120_0000  |   2 MiB   |  S   |   FPGA data SRAM region                                   |
+| BRAM  | 0x1100_0000  |  0x1110_0000  |   1 MiB   |  S   |   FPGA data SRAM region                                   |
 | DTCM  | 0x3000_0000  |  0x3007_FFFF  |   512 kiB |  S   |   4 banks for 128 kiB each                                |
-| SRAM  | 0x3100_0000  |  0x313F_FFFF  |   4 MiB   |  S   |   2 banks of 2 MiB each as SSE-300 internal SRAM region   |
+| SRAM  | 0x3100_0000  |  0x3120_0000  |   2 MiB   |  S   |   2 banks of 1 MiB each as SSE-300 internal SRAM region   |
 | DDR   | 0x7000_0000  |  0x7FFF_FFFF  |  256 MiB  |  S   |   DDR memory region                                       |
 
 The default memory map can be found here: <https://developer.arm.com/documentation/101051/0002/Memory-model/Memory-map>.
+
+## Arm® Cortex®-M55 Memory map overview for Corstone™-310 reference design
+
+The following table refers to the memory mapping information specific to the Arm® Cortex®-M55.
+
+| Name  | Base address | Limit address |  Size     | IDAU |  Remarks                                                  |
+|-------|--------------|---------------|-----------|------|-----------------------------------------------------------|
+| ITCM  | 0x0000_0000  |  0x0000_7FFF  |   32 kiB  |  NS  |   ITCM code region                                        |
+| BRAM  | 0x0100_0000  |  0x0120_0000  |   2 MiB   |  NS  |   FPGA data SRAM region                                   |
+| DTCM  | 0x2000_0000  |  0x2000_7FFF  |   32 kiB  |  NS  |   4 banks for 8 kiB each                                  |
+| SRAM  | 0x2100_0000  |  0x213F_FFFF  |   4 MiB   |  NS  |   2 banks of 2 MiB each as SSE-310 internal SRAM region   |
+| DDR   | 0x6000_0000  |  0x6FFF_FFFF  |   256 MiB |  NS  |   DDR memory region                                       |
+| ITCM  | 0x1000_0000  |  0x1000_7FFF  |   32 kiB  |  S   |   ITCM code region                                        |
+| BRAM  | 0x1100_0000  |  0x1120_0000  |   2 MiB   |  S   |   FPGA data SRAM region                                   |
+| DTCM  | 0x3000_0000  |  0x3000_7FFF  |   32 kiB  |  S   |   4 banks for 8 kiB each                                  |
+| SRAM  | 0x3100_0000  |  0x313F_FFFF  |   4 MiB   |  S   |   2 banks of 2 MiB each as SSE-310 internal SRAM region   |
+| DDR   | 0x7000_0000  |  0x7FFF_FFFF  |  256 MiB  |  S   |   DDR memory region                                       |
+
diff --git a/docs/sections/arm_virtual_hardware.md b/docs/sections/arm_virtual_hardware.md
index 23c21c4..47761ee 100644
--- a/docs/sections/arm_virtual_hardware.md
+++ b/docs/sections/arm_virtual_hardware.md
@@ -35,7 +35,10 @@
 
 Once you have access to the AWS instance, we recommend starting from the
 [quick start guide](../quick_start.md#Quick-start-example-ML-application) in order to get familiar
-with the ml-embedded-evaluation-kit. Note that on the AWS instance, the FVP is available under `/opt/FVP_Corstone_SSE-300`.
+with the ml-embedded-evaluation-kit. Note that on the AWS instance, the FVPs are available under:
+ - `/opt/VHT/VHT_Corstone_SSE-300_Ethos-U55`
+ - `/opt/VHT/VHT_Corstone_SSE-300_Ethos-U65`
+ - `/opt/VHT/VHT_Corstone_SSE-310`
 
 In order to view the FVP window when launching on the AWS instance a VNC is required.
 See relevant section [here](https://aws.amazon.com/premiumsupport/knowledge-center/ec2-linux-2-install-gui/).
diff --git a/docs/sections/building.md b/docs/sections/building.md
index 5f8a3cb..8fe9f8a 100644
--- a/docs/sections/building.md
+++ b/docs/sections/building.md
@@ -15,6 +15,7 @@
       - [Using Arm Compiler](./building.md#using-arm-compiler)
       - [Generating project for Arm Development Studio](./building.md#generating-project-for-arm-development-studio)
       - [Configuring with custom TPIP dependencies](./building.md#configuring-with-custom-tpip-dependencies)
+    - [Configuring the build for MPS3 SSE-310](./building.md#configuring-the-build-for-mps3-sse_310)
     - [Configuring native unit-test build](./building.md#configuring-native-unit_test-build)
     - [Configuring the build for simple-platform](./building.md#configuring-the-build-for-simple_platform)
     - [Building the configured project](./building.md#building-the-configured-project)
@@ -62,14 +63,14 @@
 
 - If you are using the proprietary Arm Compiler, ensure that the compiler license has been correctly configured.
 
-- CMake version 3.15.6 or above is installed and available on the path. Test CMake by running:
+- CMake version 3.16.3 or above is installed and available on the path. Test CMake by running:
 
     ```commandline
     cmake --version
     ```
 
     ```log
-    cmake version 3.16.2
+    cmake version 3.16.3
     ```
 
 > **Note:** How to add cmake to the path:
@@ -159,6 +160,7 @@
 - `TARGET_SUBSYSTEM`: The target platform subsystem. Specifies the design implementation for the deployment target. For
   both, the MPS3 FVP and the MPS3 FPGA, this must be left to the default value of SSE-300:
   - `sse-300` (default - [Arm® Corstone™-300](https://developer.arm.com/ip-products/subsystem/corstone/corstone-300))
+  - `sse-310` (The FVP is available via Arm Virtual Hardware (AVH) hosted on AWS)
 
 - `CMAKE_TOOLCHAIN_FILE`: This built-in CMake parameter can be used to override the default toolchain file used for the
   build. All the valid toolchain files are located in the scripts directory. For example, see:
@@ -471,6 +473,24 @@
 > **Note:** If re-building with changed parameters values, we recommend that you clean the build directory and re-run
 > the CMake command.
 
+
+### Configuring the build for MPS3 SSE-310
+
+On Linux, execute the following command to build the application for target platform `mps3` and subsystem `sse-310`,
+using the default toolchain file for the target as `bare-metal-gcc` and the default *Ethos-U55* timing adapter settings.
+This is equivalent to running:
+
+```commandline
+cmake .. \
+    -DCMAKE_TOOLCHAIN_FILE=scripts/cmake/toolchains/bare-metal-gcc.cmake \
+    -DTARGET_PLATFORM=mps3 \
+    -DTARGET_SUBSYSTEM=sse-310 \
+    -DTA_CONFIG_FILE=scripts/cmake/timing_adapter/ta_config_u55_high_end.cmake
+```
+
+> **Note:** Only *Ethos-U55* timing adapter settings can be used.
+> *Ethos-U65* is not supported for this subsystem.
+
 ### Configuring native unit-test build
 
 ```commandline
diff --git a/docs/sections/deployment.md b/docs/sections/deployment.md
index 84ffcf6..e2600d8 100644
--- a/docs/sections/deployment.md
+++ b/docs/sections/deployment.md
@@ -205,7 +205,7 @@
 
     Note that the `itcm.bin` and `ddr.bin` files correspond to the part of the application residing in the first and
     second load region respectively, as defined in the
-    [scatter file](../../scripts/cmake/platforms/mps3/mps3-sse-300.sct).
+    [scatter file](../../scripts/cmake/platforms/mps3/sse-300/mps3-sse-300.sct).
 
 2. The `./bin/sectors/images.txt` file must be copied over to the MPS3. The exact location for the destination depends
    on the version of the MPS3 board and the application note for the bit file in use.
diff --git a/scripts/cmake/cmsis-dsp.cmake b/scripts/cmake/cmsis-dsp.cmake
index f2de158..73f6100 100644
--- a/scripts/cmake/cmsis-dsp.cmake
+++ b/scripts/cmake/cmsis-dsp.cmake
@@ -69,7 +69,7 @@
 endif ()
 
 # 5. Add any custom/conditional flags for compilation or linkage
-if (${CMAKE_SYSTEM_PROCESSOR} STREQUAL cortex-m55)
+if ("${CMAKE_SYSTEM_PROCESSOR}" STREQUAL "cortex-m55" OR "${CMAKE_SYSTEM_ARCH}" STREQUAL "armv8.1-m.main")
     target_compile_definitions(${CMSIS_DSP_TARGET} PUBLIC
         ARM_MATH_MVEI
         ARM_MATH_DSP
diff --git a/scripts/cmake/common_user_options.cmake b/scripts/cmake/common_user_options.cmake
index 7dc68de..7981068 100644
--- a/scripts/cmake/common_user_options.cmake
+++ b/scripts/cmake/common_user_options.cmake
@@ -43,7 +43,7 @@
     mps3
     STRING)
 
-USER_OPTION(TARGET_SUBSYSTEM "Specify platform target subsystem: sse-300 or none"
+USER_OPTION(TARGET_SUBSYSTEM "Specify platform target subsystem: sse-300, sse-310 or none"
     sse-300
     STRING)
 
diff --git a/scripts/cmake/platforms/mps3/build_configuration.cmake b/scripts/cmake/platforms/mps3/build_configuration.cmake
index 76c9e78..6e21d9b 100644
--- a/scripts/cmake/platforms/mps3/build_configuration.cmake
+++ b/scripts/cmake/platforms/mps3/build_configuration.cmake
@@ -17,11 +17,35 @@
 
 function(set_platform_global_defaults)
     message(STATUS "Platform: MPS3 FPGA Prototyping Board or FVP")
+
+    if (NOT DEFINED CMAKE_SYSTEM_PROCESSOR)
+        if (TARGET_SUBSYSTEM STREQUAL sse-300)
+            set(CMAKE_SYSTEM_PROCESSOR cortex-m55 CACHE STRING "Cortex-M CPU to use")
+        elseif(TARGET_SUBSYSTEM STREQUAL sse-310)
+            # For CMake versions older than 3.21, the compiler and linker flags for
+            # ArmClang are added by CMake automatically which makes it mandatory to
+            # define the system processor. For CMake versions 3.21 or later (that
+            # implement policy CMP0123) we use armv8.1-m as the arch until the
+            # toolchain officially supports Cortex-M85. For older version of CMake
+            # we revert to using Cortex-M55 as the processor (as this will work
+            # for M85 too).
+            if(POLICY CMP0123)
+                set(CMAKE_SYSTEM_ARCH armv8.1-m.main CACHE STRING "System arch to use")
+            else()
+                set(CMAKE_SYSTEM_PROCESSOR  cortex-m55)
+            endif()
+        endif()
+    endif()
+
     if (NOT DEFINED CMAKE_TOOLCHAIN_FILE)
         set(CMAKE_TOOLCHAIN_FILE ${CMAKE_TOOLCHAIN_DIR}/bare-metal-gcc.cmake
                 CACHE FILEPATH "Toolchain file")
     endif()
 
+    if ((ETHOS_U_NPU_ID STREQUAL U65) AND (TARGET_SUBSYSTEM STREQUAL sse-310))
+        message(FATAL_ERROR "Non compatible Ethos-U NPU processor ${ETHOS_U_NPU_ID} and target subsystem ${TARGET_SUBSYSTEM}")
+    endif()
+
     set(LINKER_SCRIPT_NAME "mps3-${TARGET_SUBSYSTEM}" PARENT_SCOPE)
     set(PLATFORM_DRIVERS_DIR "${HAL_PLATFORM_DIR}/mps3" PARENT_SCOPE)
 
@@ -35,7 +59,7 @@
     # Add link options for the linker script to be used:
     add_linker_script(
             ${PARSED_TARGET_NAME}          # Target
-            ${CMAKE_SCRIPTS_DIR}/platforms/mps3    # Directory path
+            ${CMAKE_SCRIPTS_DIR}/platforms/mps3/${TARGET_SUBSYSTEM}    # Directory path
             ${LINKER_SCRIPT_NAME})  # Name of the file without suffix
 
     add_target_map_file(
@@ -48,8 +72,13 @@
     file(REMOVE_RECURSE ${SECTORS_BIN_DIR})
     file(MAKE_DIRECTORY ${SECTORS_BIN_DIR})
 
-    set(LINKER_SECTION_TAGS     "*.at_itcm" "*.at_ddr")
-    set(LINKER_OUTPUT_BIN_TAGS  "itcm.bin"  "ddr.bin")
+    if (TARGET_SUBSYSTEM STREQUAL sse-310)
+        set(LINKER_SECTION_TAGS     "*.at_bram" "*.at_ddr")
+        set(LINKER_OUTPUT_BIN_TAGS  "bram.bin"  "ddr.bin")
+    else()
+        set(LINKER_SECTION_TAGS     "*.at_itcm" "*.at_ddr")
+        set(LINKER_OUTPUT_BIN_TAGS  "itcm.bin"  "ddr.bin")
+    endif()
 
     add_bin_generation_command(
             TARGET_NAME ${PARSED_TARGET_NAME}
@@ -64,4 +93,4 @@
             POST_BUILD
             COMMAND ${CMAKE_COMMAND} -E copy ${MPS3_FPGA_CONFIG} ${SECTORS_DIR})
 
-endfunction()
\ No newline at end of file
+endfunction()
diff --git a/scripts/cmake/platforms/mps3/mps3-sse-300.ld b/scripts/cmake/platforms/mps3/sse-300/mps3-sse-300.ld
similarity index 100%
rename from scripts/cmake/platforms/mps3/mps3-sse-300.ld
rename to scripts/cmake/platforms/mps3/sse-300/mps3-sse-300.ld
diff --git a/scripts/cmake/platforms/mps3/mps3-sse-300.sct b/scripts/cmake/platforms/mps3/sse-300/mps3-sse-300.sct
similarity index 100%
rename from scripts/cmake/platforms/mps3/mps3-sse-300.sct
rename to scripts/cmake/platforms/mps3/sse-300/mps3-sse-300.sct
diff --git a/scripts/cmake/platforms/mps3/sse-310/mps3-sse-310.ld b/scripts/cmake/platforms/mps3/sse-310/mps3-sse-310.ld
new file mode 100644
index 0000000..a631aaa
--- /dev/null
+++ b/scripts/cmake/platforms/mps3/sse-310/mps3-sse-310.ld
@@ -0,0 +1,214 @@
+/*
+ * Copyright (c) 2021 Arm Limited. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+__STACK_SIZE = 0x00008000;
+__HEAP_SIZE  = 0x000C0000;
+
+/* System memory brief */
+MEMORY
+{
+  ITCM  (rx)  : ORIGIN = 0x10000000, LENGTH = 0x00008000
+  DTCM  (rwx) : ORIGIN = 0x30000000, LENGTH = 0x00008000
+  BRAM  (rwx) : ORIGIN = 0x11000000, LENGTH = 0x00200000
+  SRAM  (rwx) : ORIGIN = 0x31000000, LENGTH = 0x00400000
+  DDR   (rwx) : ORIGIN = 0x70000000, LENGTH = 0x02000000
+
+  /* Dynamic load regions declared for use by FVP only
+   * These regions are mentioned in the CMake subsystem profile.
+   * Do not change the addresses here in isolation. */
+  DDR_dynamic_model (rx) : ORIGIN = 0x90000000, LENGTH = 0x02000000
+  DDR_dynamic_ifm   (rx) : ORIGIN = 0x92000000, LENGTH = 0x01000000
+  DDR_dynamic_ofm   (rx) : ORIGIN = 0x93000000, LENGTH = 0x01000000
+}
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions ITCM and RAM.
+ * It references following symbols, which must be defined in code:
+ *   Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ *   __exidx_start
+ *   __exidx_end
+ *   __copy_table_start__
+ *   __copy_table_end__
+ *   __zero_table_start__
+ *   __zero_table_end__
+ *   __etext
+ *   __data_start__
+ *   __preinit_array_start
+ *   __preinit_array_end
+ *   __init_array_start
+ *   __init_array_end
+ *   __fini_array_start
+ *   __fini_array_end
+ *   __data_end__
+ *   __bss_start__
+ *   __bss_end__
+ *   __end__
+ *   end
+ *   __HeapLimit
+ *   __StackLimit
+ *   __StackTop
+ *   __stack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+  .text.at_bram :
+  {
+    KEEP(*(.vectors))
+
+    KEEP(*(.init))
+    KEEP(*(.fini))
+
+    /* .ctors */
+    *crtbegin.o(.ctors)
+    *crtbegin?.o(.ctors)
+    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+    *(SORT(.ctors.*))
+    *(.ctors)
+
+    /* .dtors */
+    *crtbegin.o(.dtors)
+    *crtbegin?.o(.dtors)
+    *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+    *(SORT(.dtors.*))
+    *(.dtors)
+
+    KEEP(*(.eh_frame*))
+    
+    *(vtable)
+    *(.data)
+    *(.data.*)
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP(*(.preinit_array))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP(*(SORT(.init_array.*)))
+    KEEP(*(.init_array))
+    PROVIDE_HIDDEN (__init_array_end = .);
+    . = ALIGN(4);
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP(*(SORT(.fini_array.*)))
+    KEEP(*(.fini_array))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+    KEEP(*(.jcr*))
+    . = ALIGN(4);
+
+    *(.ARM.extab* .gnu.linkonce.armextab.*)
+    . = ALIGN(4);
+
+    *(.rodata*)
+    . = ALIGN(4);
+    * (npu_driver_version)
+    . = ALIGN(4);
+    * (npu_driver_arch_version)
+    . = ALIGN(4);
+
+    __copy_table_start__ = .;
+    . = ALIGN(4);
+    __copy_table_end__ = .;
+  } > BRAM
+
+  __exidx_start = .;
+  .ARM.exidx.at_bram :
+  {
+    *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+  } > BRAM
+  __exidx_end = .;
+
+  .sram :
+  {
+    . = ALIGN(16);
+    /* Cache area (if used) */
+    *(.bss.NoInit.ethos_u_cache)
+    . = ALIGN (16);
+    /* activation buffers a.k.a tensor arena when memory mode sram only or shared sram */
+    *(.bss.NoInit.activation_buf_sram)
+    . = ALIGN(16);
+  } > SRAM AT > SRAM
+
+  .bss :
+  {
+    . = ALIGN(4);
+    __bss_start__ = .;
+    *(.bss)
+    *(.bss.*)
+    *(COMMON)
+    . = ALIGN(4);
+    __bss_end__ = .;
+  } > BRAM
+
+  .zero.table.at_bram :
+  {
+    . = ALIGN(4);
+    __zero_table_start__ = .;
+
+    LONG (__bss_start__)
+    LONG ((__bss_end__ - __bss_start__)/4) /* Size is in 32-bit words */
+
+    __zero_table_end__ = .;
+  } > BRAM
+  
+  .heap (COPY) :
+  {
+    . = ALIGN(8);
+    __end__ = .;
+    PROVIDE(end = .);
+    . = . + __HEAP_SIZE;
+    . = ALIGN(8);
+    __HeapLimit = .;
+  } > BRAM
+
+  __bram_total = ALIGN(4);
+
+  ASSERT( __bram_total < (ORIGIN(BRAM) + LENGTH(BRAM)), "BRAM overflow")
+
+  .stack (ORIGIN(DTCM) + LENGTH(DTCM) - __STACK_SIZE) (COPY) :
+  {
+    . = ALIGN(8);
+    __StackLimit = .;
+    . = . + __STACK_SIZE;
+    . = ALIGN(8);
+    __StackTop = .;
+  } > DTCM
+  PROVIDE(__stack = __StackTop);
+  ASSERT(__STACK_SIZE <= LENGTH(DTCM), "DTCM overflow")
+
+  .ddr.at_ddr :
+  {
+    /* __attribute__((aligned(16))) is not handled by the CMSIS startup code.
+     * Force the alignment here as a workaround */
+    . = ALIGN(16);
+    /* nn model's baked in input matrices */
+    *(ifm)
+    . = ALIGN(16);
+    /* nn model's default space */
+    *(nn_model)
+    . = ALIGN (16);
+    /* labels */
+    *(labels)
+    . = ALIGN (16);
+    /* activation buffers a.k.a tensor arena when memory mode dedicated sram */
+    *(activation_buf_dram)
+    . = ALIGN (16);
+  } > DDR AT > DDR
+
+}
diff --git a/scripts/cmake/platforms/mps3/sse-310/mps3-sse-310.sct b/scripts/cmake/platforms/mps3/sse-310/mps3-sse-310.sct
new file mode 100644
index 0000000..452b0fe
--- /dev/null
+++ b/scripts/cmake/platforms/mps3/sse-310/mps3-sse-310.sct
@@ -0,0 +1,140 @@
+;  Copyright (c) 2021 Arm Limited. All rights reserved.
+;  SPDX-License-Identifier: Apache-2.0
+;
+;  Licensed under the Apache License, Version 2.0 (the "License");
+;  you may not use this file except in compliance with the License.
+;  You may obtain a copy of the License at
+;
+;      http://www.apache.org/licenses/LICENSE-2.0
+;
+;  Unless required by applicable law or agreed to in writing, software
+;  distributed under the License is distributed on an "AS IS" BASIS,
+;  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+;  See the License for the specific language governing permissions and
+;  limitations under the License.
+
+; *************************************************************
+; ***       Scatter-Loading Description File                ***
+; *************************************************************
+; Please see docs/sections/appendix.md for memory mapping
+; information.
+;
+; Note: Ethos-U NPU can access BRAM, internal SRAM and the DDR
+;       sections => activation buffers and the model should
+;       only be placed in those regions.
+;
+
+;---------------------------------------------------------
+; First load region (SRAM/BRAM) 2MiB region
+;---------------------------------------------------------
+LOAD_REGION_0       0x11000000                  0x00200000
+{
+    ;-----------------------------------------------------
+    ; 0.5 MiB of SRAM/BRAM region. Our vector table also
+    ; resides here as the default INITSVTOR is 0x11000000.
+    ; We currently do not use the ITCM for any code, but
+    ; could potentially put some critical code in there
+    ; if we need to.
+    ;-----------------------------------------------------
+    bram.bin        0x11000000                  0x00080000
+    {
+        *.o (RESET, +First)
+        * (InRoot$$Sections)
+
+        ; Essentially only RO (code + data)
+        .ANY (+RO)
+    }
+
+    ;-----------------------------------------------------
+    ; Next 0.5 MiB of SRAM/BRAM region for RO, RW and ZI
+    ; data, 8 byte aligned.
+    ;-----------------------------------------------------
+    data.bin        0x11080000 ALIGN 8          0x00080000
+    {
+        ; Any RO-DATA
+        .ANY (+RO-DATA)
+
+        ; Any R/W and/or zero initialised data
+        .ANY(+RW +ZI)
+    }
+
+    ;-----------------------------------------------------
+    ; 768 KiB of remaining part of the 1MiB BRAM used as
+    ; heap space.
+    ;-----------------------------------------------------
+    ARM_LIB_HEAP    0x11100000 EMPTY ALIGN 8    0x000C0000
+    {}
+
+    ;-----------------------------------------------------
+    ; 32 kiB of stack space occupying the DTCM region.
+    ;-----------------------------------------------------
+    ARM_LIB_STACK   0x30000000 EMPTY ALIGN 8    0x00008000
+    {}
+
+    ;-----------------------------------------------------
+    ; FPGA internal SRAM of 2MiB - reserved for activation
+    ; buffers. The total memory is 4 MiB (we are choosing
+    ; to not use the other bank). This region should have
+    ; 3 cycle read latency from both CPU and Ethos-U NPU.
+    ;-----------------------------------------------------
+    isram.bin       0x31000000  UNINIT ALIGN 16 0x00200000
+    {
+        ; Cache area (if used)
+        *.o (.bss.NoInit.ethos_u_cache)
+
+        ; activation buffers a.k.a tensor arena when
+        ; memory mode sram only or shared sram
+        *.o (.bss.NoInit.activation_buf_sram)
+    }
+}
+
+;---------------------------------------------------------
+; Second load region (DDR)
+;---------------------------------------------------------
+LOAD_REGION_1       0x70000000                  0x02000000
+{
+    ;-----------------------------------------------------
+    ; 32 MiB of DDR space for neural network model,
+    ; input vectors and labels. If the activation buffer
+    ; size required by the network is bigger than the
+    ; SRAM size available, it is accommodated here.
+    ;-----------------------------------------------------
+    ddr.bin        0x70000000 ALIGN 16         0x02000000
+    {
+        ; nn model's baked in input matrices
+        *.o (ifm)
+
+        ; nn model's default space
+        *.o (nn_model)
+
+        ; labels
+        *.o (labels)
+
+        ; activation buffers a.k.a tensor arena when memory mode dedicated sram
+        *.o (activation_buf_dram)
+    }
+
+    ;-----------------------------------------------------
+    ; The following regions are for use by the FVP to
+    ; allow loading or dumping of dynamic data into or
+    ; from the memory. These regions are mentioned in
+    ; the CMake subsystem profile. Do not change the
+    ; addresses and sizes below in isolation.
+    ;-----------------------------------------------------
+    ; 32 MiB of model space for run-time load of model
+    ;-----------------------------------------------------
+    runtime_model   0x90000000 EMPTY ALIGN 16   0x02000000
+    {}
+
+    ;-----------------------------------------------------
+    ; 16 MiB of IFM space for run-time loading (FVP only)
+    ;-----------------------------------------------------
+    runtime_ifm     0x92000000 EMPTY ALIGN 16   0x01000000
+    {}
+
+    ;-----------------------------------------------------
+    ; 16 MiB of OFM space for run-time loading (FVP only)
+    ;-----------------------------------------------------
+    runtime_ofm     0x93000000 EMPTY ALIGN 16   0x01000000
+    {}
+}
diff --git a/scripts/cmake/tensorflow.cmake b/scripts/cmake/tensorflow.cmake
index 2374c86..8a790bc 100644
--- a/scripts/cmake/tensorflow.cmake
+++ b/scripts/cmake/tensorflow.cmake
@@ -50,7 +50,16 @@
     set(TENSORFLOW_LITE_MICRO_TARGET_ARCH x86_64)
 else()
     set(TENSORFLOW_LITE_MICRO_TARGET "cortex_m_generic")
-    set(TENSORFLOW_LITE_MICRO_TARGET_ARCH ${CMAKE_SYSTEM_PROCESSOR}${CPU_FEATURES})
+
+    if ("${CMAKE_SYSTEM_ARCH}" STREQUAL "armv8.1-m.main")
+        # TensorFlow's generic makefile doesn't currently have a flow for Cortex-M85.
+        # We build for Arm Cortex-M55 instead.
+        # @TODO: check with latest TensorFlow package.
+        set(TENSORFLOW_LITE_MICRO_TARGET_ARCH "cortex-m55")
+    else()
+        set(TENSORFLOW_LITE_MICRO_TARGET_ARCH "${CMAKE_SYSTEM_PROCESSOR}")
+    endif()
+
     if(ETHOS_U_NPU_ENABLED)
         # Arm Ethos-U55 NPU is the co-processor for ML workload:
         set(TENSORFLOW_LITE_MICRO_CO_PROCESSOR  "ethos_u")
diff --git a/scripts/cmake/toolchains/bare-metal-armclang.cmake b/scripts/cmake/toolchains/bare-metal-armclang.cmake
index d0b0824..97da76f 100644
--- a/scripts/cmake/toolchains/bare-metal-armclang.cmake
+++ b/scripts/cmake/toolchains/bare-metal-armclang.cmake
@@ -31,7 +31,7 @@
 set(CMAKE_C_COMPILER_WORKS          1)
 set(CMAKE_CXX_COMPILER_WORKS        1)
 
-if (NOT DEFINED CMAKE_SYSTEM_PROCESSOR)
+if (NOT DEFINED CMAKE_SYSTEM_PROCESSOR AND NOT DEFINED CMAKE_SYSTEM_ARCH)
     set(CMAKE_SYSTEM_PROCESSOR      cortex-m55)
 endif()
 
@@ -39,13 +39,27 @@
     # Flags for cortex-m55
     set(CPU_ID                      M55)
     set(CPU_COMPILE_DEF             CPU_CORTEX_${CPU_ID})
-    set(CPU_NAME                    ${CMAKE_SYSTEM_PROCESSOR})
     set(ARM_CPU                     "ARMC${CPU_ID}")
     set(FLOAT_ABI                   hard)
     set(ARM_MATH_DSP                1)
     set(ARM_MATH_LOOPUNROLL         1)
     set(CPU_HEADER_FILE             "${ARM_CPU}.h")
+    set(CPU_COMPILE_OPTION          "-mcpu=${CMAKE_SYSTEM_PROCESSOR}")
     set(CPU_LINK_OPT                "--cpu=Cortex-${CPU_ID}")
+elseif (CMAKE_SYSTEM_PROCESSOR STREQUAL cortex-m85 OR CMAKE_SYSTEM_ARCH STREQUAL armv8.1-m.main)
+    # Flags for Cortex-M85
+    set(CPU_ID                      ARMv81MML_DSP_DP_MVE_FP)
+    set(ARM_CPU                     "ARMv81MML")
+    set(CPU_COMPILE_DEF             ${CPU_ID})
+    set(FLOAT_ABI                   hard)
+    set(ARM_MATH_DSP                1)
+    set(ARM_MATH_LOOPUNROLL         1)
+
+    # @TODO: Revise once we have the CPU file in CMSIS and CPU flags
+    # are supported by toolchains.
+    set(CPU_HEADER_FILE             "${CPU_ID}.h")
+    set(CPU_COMPILE_OPTION          "-march=armv8.1-m.main+mve.fp+fp.dp")
+    set(CPU_LINK_OPT                "--cpu=8.1-M.Main.mve.fp")
 elseif(CMAKE_SYSTEM_PROCESSOR STREQUAL cortex-m33)
     # Flags for cortex-m33 to go here
 endif()
@@ -67,11 +81,11 @@
 # Arch compile options:
 add_compile_options(
     -mthumb
-    -mcpu=${CPU_NAME}
     -mfloat-abi=${FLOAT_ABI}
     --target=arm-arm-non-eabi
     -mlittle-endian
-    -MD)
+    -MD
+    ${CPU_COMPILE_OPTION})
 
 # Compile definitions:
 add_compile_definitions(
diff --git a/scripts/cmake/toolchains/bare-metal-gcc.cmake b/scripts/cmake/toolchains/bare-metal-gcc.cmake
index a5688d6..a6d6c0e 100644
--- a/scripts/cmake/toolchains/bare-metal-gcc.cmake
+++ b/scripts/cmake/toolchains/bare-metal-gcc.cmake
@@ -29,7 +29,7 @@
 set(CMAKE_C_COMPILER_WORKS          1)
 set(CMAKE_CXX_COMPILER_WORKS        1)
 
-if (NOT DEFINED CMAKE_SYSTEM_PROCESSOR)
+if (NOT DEFINED CMAKE_SYSTEM_PROCESSOR AND NOT DEFINED CMAKE_SYSTEM_ARCH)
     set(CMAKE_SYSTEM_PROCESSOR      cortex-m55)
 endif()
 
@@ -37,13 +37,27 @@
     # Flags for cortex-m55
     set(CPU_ID                      M55)
     set(CPU_COMPILE_DEF             CPU_CORTEX_${CPU_ID})
-    set(CPU_NAME                    ${CMAKE_SYSTEM_PROCESSOR})
     set(ARM_CPU                     "ARMC${CPU_ID}")
     set(FLOAT_ABI                   hard)
     set(ARM_MATH_DSP                1)
     set(ARM_MATH_LOOPUNROLL         1)
     set(CPU_HEADER_FILE             "${ARM_CPU}.h")
+    set(CPU_COMPILE_OPTION          "-mcpu=${CMAKE_SYSTEM_PROCESSOR}")
     set(CPU_LINK_OPT                "--cpu=Cortex-${CPU_ID}")
+elseif (CMAKE_SYSTEM_PROCESSOR STREQUAL cortex-m85 OR CMAKE_SYSTEM_ARCH STREQUAL armv8.1-m.main)
+    # Flags for Cortex-M85
+    set(CPU_ID                      ARMv81MML_DSP_DP_MVE_FP)
+    set(ARM_CPU                     "ARMv81MML")
+    set(CPU_COMPILE_DEF             ${CPU_ID})
+    set(FLOAT_ABI                   hard)
+    set(ARM_MATH_DSP                1)
+    set(ARM_MATH_LOOPUNROLL         1)
+
+    # @TODO: Revise once we have the CPU file in CMSIS and CPU flags
+    # are supported by toolchains.
+    set(CPU_HEADER_FILE             "${CPU_ID}.h")
+    set(CPU_COMPILE_OPTION          "-march=armv8.1-m.main+mve.fp+fp.dp")
+    set(CPU_LINK_OPT                "--cpu=8.1-M.Main.mve.fp")
 elseif(CMAKE_SYSTEM_PROCESSOR STREQUAL cortex-m33)
     # Flags for cortex-m33 to go here
 endif()
@@ -67,10 +81,10 @@
 # Arch compile options:
 add_compile_options(
     -mthumb
-    -mcpu=${CPU_NAME}
     -mfloat-abi=${FLOAT_ABI}
     -mlittle-endian
-    -MD)
+    -MD
+    ${CPU_COMPILE_OPTION})
 
 # Compile definitions:
 add_compile_definitions(
@@ -82,7 +96,7 @@
 # Link options:
 add_link_options(
     -mthumb
-    -mcpu=${CPU_NAME}
+    ${CPU_COMPILE_OPTION}
     -mfloat-abi=${FLOAT_ABI}
     -mlittle-endian
     --stats
diff --git a/scripts/mps3/sse-310/images.txt b/scripts/mps3/sse-310/images.txt
new file mode 100644
index 0000000..8a920cb
--- /dev/null
+++ b/scripts/mps3/sse-310/images.txt
@@ -0,0 +1,23 @@
+TITLE: Arm MPS3 FPGA prototyping board Images Configuration File
+
+; MCC mapping for Corstone-310 MPS3 bitfile package AN555
+; +-------------+---------------+-------------------------------+
+; | FPGA addr   | MCC addr      |  Region                       |
+; +-------------+---------------+-------------------------------+
+; | 0x00000000  | 0x00000000    | ITCM (NS)                     |
+; | 0x01000000  | 0x02000000    | BRAM or FPGA's data SRAM (NS) |
+; | 0x60000000  | 0x08000000    | DDR (NS)                      |
+; | 0x70000000  | 0x0c000000    | DDR (S)                       |
+; +-------------+---------------+-------------------------------+
+
+[IMAGES]
+
+TOTALIMAGES: 2 ;Number of Images (Max: 32)
+
+IMAGE0ADDRESS: 0x00000000 ; MCC@0x00000000 <=> FPGA@0x00000000
+IMAGE0UPDATE: AUTO
+IMAGE0FILE: \SOFTWARE\itcm.bin
+
+IMAGE1ADDRESS: 0x0c000000 ; MCC@0x0c000000 <=> FPGA@0x70000000
+IMAGE1UPDATE: AUTO
+IMAGE1FILE: \SOFTWARE\ddr.bin
diff --git a/set_up_default_resources.py b/set_up_default_resources.py
index 9e0bdf4..0b885c0 100755
--- a/set_up_default_resources.py
+++ b/set_up_default_resources.py
@@ -250,6 +250,8 @@
 )
 
 # The internal SRAM size for Corstone-300 implementation on MPS3 specified by AN552
+# The internal SRAM size for Corstone-310 implementation on MPS3 specified by AN555
+# is 4MB, but we are content with the 2MB specified below.
 mps3_max_sram_sz = 2 * 1024 * 1024  # 2 MiB (2 banks of 1 MiB each)
 
 
diff --git a/source/hal/CMakeLists.txt b/source/hal/CMakeLists.txt
index 8f32c00..b8c115c 100644
--- a/source/hal/CMakeLists.txt
+++ b/source/hal/CMakeLists.txt
@@ -19,7 +19,7 @@
 #                       HAL library                     #
 #########################################################
 
-cmake_minimum_required(VERSION 3.15.6)
+cmake_minimum_required(VERSION 3.16.3)
 
 set(HAL_TARGET hal)
 project(${HAL_TARGET}
@@ -67,4 +67,5 @@
 message(STATUS "*******************************************************")
 message(STATUS "Library                                : " ${HAL_TARGET})
 message(STATUS "CMAKE_SYSTEM_PROCESSOR                 : " ${CMAKE_SYSTEM_PROCESSOR})
+message(STATUS "CMAKE_SYSTEM_ARCH                      : " ${CMAKE_SYSTEM_ARCH})
 message(STATUS "*******************************************************")
diff --git a/source/hal/source/components/cmsis_device/CMakeLists.txt b/source/hal/source/components/cmsis_device/CMakeLists.txt
index 11b8658..5615506 100644
--- a/source/hal/source/components/cmsis_device/CMakeLists.txt
+++ b/source/hal/source/components/cmsis_device/CMakeLists.txt
@@ -18,7 +18,7 @@
 #########################################################
 # Generic CMSIS Start up library for Cortex-M targets   #
 #########################################################
-cmake_minimum_required(VERSION 3.15.6)
+cmake_minimum_required(VERSION 3.16.3)
 
 set(CMSIS_DEVICE_TARGET cmsis_device)
 set(CPU_HEADER_TARGET rte_components)
@@ -86,4 +86,5 @@
 message(STATUS "*******************************************************")
 message(STATUS "Library                                : " ${CMSIS_DEVICE_TARGET})
 message(STATUS "CMAKE_SYSTEM_PROCESSOR                 : " ${CMAKE_SYSTEM_PROCESSOR})
+message(STATUS "CMAKE_SYSTEM_ARCH                      : " ${CMAKE_SYSTEM_ARCH})
 message(STATUS "*******************************************************")
diff --git a/source/hal/source/components/lcd/CMakeLists.txt b/source/hal/source/components/lcd/CMakeLists.txt
index d260091..7262618 100644
--- a/source/hal/source/components/lcd/CMakeLists.txt
+++ b/source/hal/source/components/lcd/CMakeLists.txt
@@ -19,7 +19,7 @@
 # LCD library                                           #
 #########################################################
 
-cmake_minimum_required(VERSION 3.15.6)
+cmake_minimum_required(VERSION 3.16.3)
 
 project(lcd_component
     DESCRIPTION     "LCD support library"
diff --git a/source/hal/source/components/lcd/source/lcd_img.c b/source/hal/source/components/lcd/source/lcd_img.c
index e3921a9..92069c2 100644
--- a/source/hal/source/components/lcd/source/lcd_img.c
+++ b/source/hal/source/components/lcd/source/lcd_img.c
@@ -30,6 +30,8 @@
     /* LCD title string */
 #if defined(CPU_CORTEX_M55)
     const char* cpu_name = "Arm Cortex-M55";
+#elif defined (ARMv81MML_DSP_DP_MVE_FP)
+    const char* cpu_name = "ARMv8.1-M CPU";
 #else /* defined(CPU_CORTEX_M55) */
     const char* cpu_name = "Arm CPU";
 #endif /* defined(CPU_CORTEX_M55) */
diff --git a/source/hal/source/components/npu/CMakeLists.txt b/source/hal/source/components/npu/CMakeLists.txt
index 48f21bc..f94d0f9 100644
--- a/source/hal/source/components/npu/CMakeLists.txt
+++ b/source/hal/source/components/npu/CMakeLists.txt
@@ -19,7 +19,7 @@
 #         Ethos-U NPU initialization library            #
 #########################################################
 
-cmake_minimum_required(VERSION 3.15.6)
+cmake_minimum_required(VERSION 3.16.3)
 set(ETHOS_U_NPU_COMPONENT ethos_u_npu)
 project(${ETHOS_U_NPU_COMPONENT}
     DESCRIPTION     "Ethos-U NPU initialization library"
diff --git a/source/hal/source/components/npu_ta/CMakeLists.txt b/source/hal/source/components/npu_ta/CMakeLists.txt
index edb1fdd..358dab9 100644
--- a/source/hal/source/components/npu_ta/CMakeLists.txt
+++ b/source/hal/source/components/npu_ta/CMakeLists.txt
@@ -24,7 +24,7 @@
 # sweeps on the Arm Ethos-U NPUs. The wrapper library here provides an
 # easy way to add initialisation of the timing adapter block.
 
-cmake_minimum_required(VERSION 3.15.6)
+cmake_minimum_required(VERSION 3.16.3)
 set(ETHOS_U_NPU_TA_COMPONENT ethos_u_ta)
 project(${ETHOS_U_NPU_TA_COMPONENT}
     DESCRIPTION     "Ethos-U NPU timing adapter initialization library"
diff --git a/source/hal/source/components/platform_pmu/CMakeLists.txt b/source/hal/source/components/platform_pmu/CMakeLists.txt
index 3ef407d..df375c3 100644
--- a/source/hal/source/components/platform_pmu/CMakeLists.txt
+++ b/source/hal/source/components/platform_pmu/CMakeLists.txt
@@ -18,7 +18,7 @@
 #####################################################################
 #  Interface library for platform performance monitoring unit       #
 #####################################################################
-cmake_minimum_required(VERSION 3.15.6)
+cmake_minimum_required(VERSION 3.16.3)
 
 project(platform_pmu
     DESCRIPTION     "Header/interface for platform PMU"
diff --git a/source/hal/source/components/stdout/CMakeLists.txt b/source/hal/source/components/stdout/CMakeLists.txt
index f1e26ff..9e60e36 100644
--- a/source/hal/source/components/stdout/CMakeLists.txt
+++ b/source/hal/source/components/stdout/CMakeLists.txt
@@ -22,7 +22,7 @@
 # and PL011 UART drivers with retarget functions.       #
 #########################################################
 
-cmake_minimum_required(VERSION 3.15.6)
+cmake_minimum_required(VERSION 3.16.3)
 
 project(stdout
     DESCRIPTION     "Standard output and err redirection over UART"
diff --git a/source/hal/source/platform/mps3/CMakeLists.txt b/source/hal/source/platform/mps3/CMakeLists.txt
index 332837c..b90f6b7 100644
--- a/source/hal/source/platform/mps3/CMakeLists.txt
+++ b/source/hal/source/platform/mps3/CMakeLists.txt
@@ -19,7 +19,7 @@
 #           MPS3 platform support library               #
 #########################################################
 
-cmake_minimum_required(VERSION 3.15.6)
+cmake_minimum_required(VERSION 3.16.3)
 set(PLATFORM_DRIVERS_TARGET platform_drivers)
 project(${PLATFORM_DRIVERS_TARGET}
     DESCRIPTION     "Platform drivers library for MPS3 FPGA/FVP targets"
@@ -41,8 +41,22 @@
     set(ETHOS_U_SEC_ENABLED  "1"            CACHE STRING "Ethos-U NPU Security enable")
     set(ETHOS_U_PRIV_ENABLED "1"            CACHE STRING "Ethos-U NPU Privilege enable")
 
-    set(DYNAMIC_MODEL_BASE   "0x90000000"   CACHE STRING "Region to be used for dynamic load of model into memory")
-    set(DYNAMIC_MODEL_SIZE   "0x02000000"   CACHE STRING "Size of the space reserved for the model")
+    if (ETHOS_U_NPU_TIMING_ADAPTER_ENABLED)
+        set(TA0_BASE         "0x58103000"   CACHE STRING "Ethos-U NPU timing adapter 0")
+        set(TA1_BASE         "0x58103200"   CACHE STRING "Ethos-U NPU timing adapter 1")
+    endif()
+endif()
+
+# Define target specific base addresses here (before adding the components)
+if (TARGET_SUBSYSTEM STREQUAL sse-310)
+    set(UART0_BASE           "0x49303000"   CACHE STRING "UART base address")
+    set(UART0_BAUDRATE       "115200"       CACHE STRING "UART baudrate")
+    set(SYSTEM_CORE_CLOCK    "25000000"     CACHE STRING "System peripheral clock (Hz)")
+    set(CLCD_CONFIG_BASE     "0x4930A000"   CACHE STRING "LCD configuration base address")
+    set(ETHOS_U_BASE_ADDR    "0x50004000"   CACHE STRING "Ethos-U NPU base address")
+    set(ETHOS_U_IRQN         "16"           CACHE STRING "Ethos-U55 Interrupt")
+    set(ETHOS_U_SEC_ENABLED  "1"            CACHE STRING "Ethos-U NPU Security enable")
+    set(ETHOS_U_PRIV_ENABLED "1"            CACHE STRING "Ethos-U NPU Privilege enable")
 
     if (ETHOS_U_NPU_TIMING_ADAPTER_ENABLED)
         set(TA0_BASE         "0x58103000"   CACHE STRING "Ethos-U NPU timing adapter 0")
@@ -50,6 +64,9 @@
     endif()
 endif()
 
+set(DYNAMIC_MODEL_BASE   "0x90000000"   CACHE STRING "Region to be used for dynamic load of model into memory")
+set(DYNAMIC_MODEL_SIZE   "0x02000000"   CACHE STRING "Size of the space reserved for the model")
+
 math(EXPR IFM_BASE      "${DYNAMIC_MODEL_BASE} + ${DYNAMIC_MODEL_SIZE}" OUTPUT_FORMAT HEXADECIMAL)
 set(DYNAMIC_IFM_BASE    "${IFM_BASE}" CACHE STRING "Base address for IFMs to be loaded")
 set(DYNAMIC_IFM_SIZE    "0x01000000" CACHE STRING "Size of the space reserved for the IFM")
@@ -57,6 +74,7 @@
 set(DYNAMIC_OFM_BASE    "${OFM_BASE}" CACHE STRING "Base address for OFMs to be dumped to")
 set(DYNAMIC_OFM_SIZE    "0x01000000" CACHE STRING "Size of the space reserved for the OFM")
 
+
 # 2. Create static library
 add_library(${PLATFORM_DRIVERS_TARGET} STATIC)
 
@@ -142,4 +160,5 @@
 message(STATUS "*******************************************************")
 message(STATUS "Library                                : " ${PLATFORM_DRIVERS_TARGET})
 message(STATUS "CMAKE_SYSTEM_PROCESSOR                 : " ${CMAKE_SYSTEM_PROCESSOR})
+message(STATUS "CMAKE_SYSTEM_ARCH                      : " ${CMAKE_SYSTEM_ARCH})
 message(STATUS "*******************************************************")
diff --git a/source/hal/source/platform/mps3/include/sse-310/mem_regions.h b/source/hal/source/platform/mps3/include/sse-310/mem_regions.h
new file mode 100644
index 0000000..f6430e0
--- /dev/null
+++ b/source/hal/source/platform/mps3/include/sse-310/mem_regions.h
@@ -0,0 +1,56 @@
+/*
+ * Copyright (c) 2022 Arm Limited. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef MEM_REGION_DEFS_H
+#define MEM_REGION_DEFS_H
+
+#define ITCM_SIZE             (0x00080000)     /* ITCM size */
+#define DTCM_BLK_SIZE         (0x00020000)     /* DTCM size, 4 banks of this size available */
+#define BRAM_SIZE             (0x00200000)     /* BRAM size */
+#define ISRAM0_SIZE           (0x00200000)     /* ISRAM0 size */
+#define ISRAM1_SIZE           (0x00200000)     /* ISRAM1 size */
+#define QSPI_SRAM_SIZE        (0x00800000)     /* QSPI Flash size */
+#define DDR4_BLK_SIZE         (0x10000000)     /* DDR4 block size */
+
+#define ITCM_BASE_NS          (0x00000000)     /* Instruction TCM Non-Secure base address */
+#define BRAM_BASE_NS          (0x01000000)     /* CODE SRAM Non-Secure base address */
+#define DTCM0_BASE_NS         (0x20000000)     /* Data TCM block 0 Non-Secure base address */
+#define DTCM1_BASE_NS         (0x20020000)     /* Data TCM block 1 Non-Secure base address */
+#define DTCM2_BASE_NS         (0x20040000)     /* Data TCM block 2 Non-Secure base address */
+#define DTCM3_BASE_NS         (0x20060000)     /* Data TCM block 3 Non-Secure base address */
+#define ISRAM0_BASE_NS        (0x21000000)     /* Internal SRAM Area Non-Secure base address */
+#define ISRAM1_BASE_NS        (0x21100000)     /* Internal SRAM Area Non-Secure base address */
+#define QSPI_SRAM_BASE_NS     (0x28000000)     /* QSPI SRAM Non-Secure base address */
+#define DDR4_BLK0_BASE_NS     (0x60000000)     /* DDR4 block 0 Non-Secure base address */
+#define DDR4_BLK1_BASE_NS     (0x80000000)     /* DDR4 block 1 Non-Secure base address */
+#define DDR4_BLK2_BASE_NS     (0xA0000000)     /* DDR4 block 2 Non-Secure base address */
+#define DDR4_BLK3_BASE_NS     (0xC0000000)     /* DDR4 block 3 Non-Secure base address */
+
+#define ITCM_BASE_S           (0x10000000)     /* Instruction TCM Secure base address */
+#define BRAM_BASE_S           (0x11000000)     /* CODE SRAM Secure base address */
+#define DTCM0_BASE_S          (0x30000000)     /* Data TCM block 0 Secure base address */
+#define DTCM1_BASE_S          (0x30020000)     /* Data TCM block 1 Secure base address */
+#define DTCM2_BASE_S          (0x30040000)     /* Data TCM block 2 Secure base address */
+#define DTCM3_BASE_S          (0x30060000)     /* Data TCM block 3 Secure base address */
+#define ISRAM0_BASE_S         (0x31000000)     /* Internal SRAM Area Secure base address */
+#define ISRAM1_BASE_S         (0x31100000)     /* Internal SRAM Area Secure base address */
+#define DDR4_BLK0_BASE_S      (0x70000000)     /* DDR4 block 0 Secure base address */
+#define DDR4_BLK1_BASE_S      (0x90000000)     /* DDR4 block 1 Secure base address */
+#define DDR4_BLK2_BASE_S      (0xB0000000)     /* DDR4 block 2 Secure base address */
+#define DDR4_BLK3_BASE_S      (0xD0000000)     /* DDR4 block 3 Secure base address */
+
+#endif /*  MEM_REGION_DEFS_H  */
diff --git a/source/hal/source/platform/mps3/include/sse-310/peripheral_irqs.h b/source/hal/source/platform/mps3/include/sse-310/peripheral_irqs.h
new file mode 100644
index 0000000..99f8b46
--- /dev/null
+++ b/source/hal/source/platform/mps3/include/sse-310/peripheral_irqs.h
@@ -0,0 +1,134 @@
+/*
+ * Copyright (c) 2022 Arm Limited. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef PERIPHERAL_IRQS_H
+#define PERIPHERAL_IRQS_H
+
+/******************************************************************************/
+/*                    Peripheral interrupt numbers                            */
+/******************************************************************************/
+
+/* -------------------  Cortex-M Processor Exceptions Numbers  -------------- */
+/*                 -14 to -1 should be defined by the system header           */
+/* ----------------------  Core Specific Interrupt Numbers  ------------------*/
+#define NONSEC_WATCHDOG_RESET_IRQn ( 0)  /* Non-Secure Watchdog Reset Interrupt   */
+#define NONSEC_WATCHDOG_IRQn       ( 1)  /* Non-Secure Watchdog Interrupt         */
+#define S32K_TIMER_IRQn            ( 2)  /* S32K Timer Interrupt                  */
+#define TIMER0_IRQn                ( 3)  /* TIMER 0 Interrupt                     */
+#define TIMER1_IRQn                ( 4)  /* TIMER 1 Interrupt                     */
+#define TIMER2_IRQn                ( 5)  /* TIMER 2 Interrupt                    */
+#define MPC_IRQn                   ( 9)  /* MPC Combined () Interrupt       */
+#define PPC_IRQn                   (10)  /* PPC Combined () Interrupt       */
+#define MSC_IRQn                   (11)  /* MSC Combined () Interrput       */
+#define BRIDGE_ERROR_IRQn          (12)  /* Bridge Error Combined () Interrupt */
+#define MGMT_PPU_IRQn              (14)  /* MGMT_PPU */
+#define EthosU_IRQn                (16)   /* Ethos-Uxx Interrupt */
+#define CPU0_PPU_IRQn              (16)  /* CPU0_PPU */
+#define DEBUG_PPU_IRQn             (26)  /* DEBUG_PPU */
+#define TIMER3_AON_IRQn            (27)  /* TIMER3_AON */
+#define CPU0CTIIQ0_IRQn            (28)  /* CPU0CTIIQ0 */
+#define CPU0CTIIQ01_IRQn           (29)  /* CPU0CTIIQ01 */
+
+#define SYS_TSTAMP_COUNTER_IRQn    (32)  /* System timestamp counter interrupt */
+
+/* ----------------------  CMSDK Specific Interrupt Numbers  ----------------- */
+#define UARTRX0_IRQn               (33)  /* UART 0 RX Interrupt                   */
+#define UARTTX0_IRQn               (34)  /* UART 0 TX Interrupt                   */
+#define UARTRX1_IRQn               (35)  /* UART 1 RX Interrupt                   */
+#define UARTTX1_IRQn               (36)  /* UART 1 TX Interrupt                   */
+#define UARTRX2_IRQn               (37)  /* UART 2 RX Interrupt                   */
+#define UARTTX2_IRQn               (38)  /* UART 2 TX Interrupt                   */
+#define UARTRX3_IRQn               (39)  /* UART 3 RX Interrupt                   */
+#define UARTTX3_IRQn               (40)  /* UART 3 TX Interrupt                   */
+#define UARTRX4_IRQn               (41)  /* UART 4 RX Interrupt                   */
+#define UARTTX4_IRQn               (42)  /* UART 4 TX Interrupt                   */
+#define UART0_IRQn                 (43)  /* UART 0 combined Interrupt             */
+#define UART1_IRQn                 (44)  /* UART 1 combined Interrupt             */
+#define UART2_IRQn                 (45)  /* UART 2 combined Interrupt             */
+#define UART3_IRQn                 (46)  /* UART 3 combined Interrupt             */
+#define UART4_IRQn                 (47)  /* UART 4 combined Interrupt             */
+#define UARTOVF_IRQn               (48)  /* UART 0,1,2,3 and 4 Overflow Interrupt */
+#define ETHERNET_IRQn              (49)  /* Ethernet Interrupt                    */
+#define I2S_IRQn                   (50)  /* I2S Interrupt                         */
+#define TSC_IRQn                   (51)  /* Touch Screen Interrupt                */
+#define SPI2_IRQn                  (53)  /* SPI 2 Interrupt                       */
+#define SPI3_IRQn                  (54)  /* SPI 3 Interrupt                       */
+#define SPI4_IRQn                  (55)  /* SPI 4 Interrupt                       */
+
+#define GPIO0_IRQn                 (69)  /* GPIO 0 Combined Interrupt             */
+#define GPIO1_IRQn                 (70)  /* GPIO 1 Combined Interrupt             */
+#define GPIO2_IRQn                 (71)  /* GPIO 2 Combined Interrupt             */
+#define GPIO3_IRQn                 (72)  /* GPIO 3 Combined Interrupt             */
+
+#define GPIO0_0_IRQn               (73)  /* All P0 I/O pins used as irq source    */
+#define GPIO0_1_IRQn               (74)  /* There are 16 pins in total            */
+#define GPIO0_2_IRQn               (75)
+#define GPIO0_3_IRQn               (76)
+#define GPIO0_4_IRQn               (77)
+#define GPIO0_5_IRQn               (78)
+#define GPIO0_6_IRQn               (79)
+#define GPIO0_7_IRQn               (80)
+#define GPIO0_8_IRQn               (81)
+#define GPIO0_9_IRQn               (82)
+#define GPIO0_10_IRQn              (83)
+#define GPIO0_11_IRQn              (84)
+#define GPIO0_12_IRQn              (85)
+#define GPIO0_13_IRQn              (86)
+#define GPIO0_14_IRQn              (87)
+#define GPIO0_15_IRQn              (88)
+#define GPIO1_0_IRQn               (89)  /* All P1 I/O pins used as irq source    */
+#define GPIO1_1_IRQn               (90)  /* There are 16 pins in total            */
+#define GPIO1_2_IRQn               (91)
+#define GPIO1_3_IRQn               (92)
+#define GPIO1_4_IRQn               (93)
+#define GPIO1_5_IRQn               (94)
+#define GPIO1_6_IRQn               (95)
+#define GPIO1_7_IRQn               (96)
+#define GPIO1_8_IRQn               (97)
+#define GPIO1_9_IRQn               (98)
+#define GPIO1_10_IRQn              (99)
+#define GPIO1_11_IRQn              (100)
+#define GPIO1_12_IRQn              (101)
+#define GPIO1_13_IRQn              (102)
+#define GPIO1_14_IRQn              (103)
+#define GPIO1_15_IRQn              (104)
+#define GPIO2_0_IRQn               (105)  /* All P2 I/O pins used as irq source    */
+#define GPIO2_1_IRQn               (106)  /* There are 15 pins in total            */
+#define GPIO2_2_IRQn               (107)
+#define GPIO2_3_IRQn               (108)
+#define GPIO2_4_IRQn               (109)
+#define GPIO2_5_IRQn               (110)
+#define GPIO2_6_IRQn               (111)
+#define GPIO2_7_IRQn               (112)
+#define GPIO2_8_IRQn               (113)
+#define GPIO2_9_IRQn               (114)
+#define GPIO2_10_IRQn              (115)
+#define GPIO2_11_IRQn              (116)
+#define GPIO2_12_IRQn              (117)
+#define GPIO2_13_IRQn              (118)
+#define GPIO2_14_IRQn              (119)
+#define GPIO2_15_IRQn              (120)
+#define GPIO3_0_IRQn               (121)  /* All P3 I/O pins used as irq source    */
+#define GPIO3_1_IRQn               (122)  /* There are 4 pins in total             */
+#define GPIO3_2_IRQn               (123)
+#define GPIO3_3_IRQn               (124)
+#define UARTRX5_IRQn               (125)  /* UART 5 RX Interrupt                   */
+#define UARTTX5_IRQn               (126)  /* UART 5 TX Interrupt                   */
+#define UART5_IRQn                 (127)  /* UART 5 combined Interrupt             */
+/* #undef HDCLCD_IRQn */
+
+#endif /* PERIPHERAL_IRQS_H */
diff --git a/source/hal/source/platform/mps3/include/sse-310/peripheral_memmap.h b/source/hal/source/platform/mps3/include/sse-310/peripheral_memmap.h
new file mode 100644
index 0000000..9ba8533
--- /dev/null
+++ b/source/hal/source/platform/mps3/include/sse-310/peripheral_memmap.h
@@ -0,0 +1,164 @@
+/*
+ * Copyright (c) 2022 Arm Limited. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef PERIPHERAL_MEMMAP_H
+#define PERIPHERAL_MEMMAP_H
+
+#define DESIGN_NAME              "Arm Corstone-310 - AN555"
+
+/******************************************************************************/
+/*                         Peripheral memory map                              */
+/******************************************************************************/
+
+#define CMSDK_GPIO0_BASE         (0x41100000)       /* User GPIO 0 Base Address   */
+#define CMSDK_GPIO1_BASE         (0x41101000)       /* User GPIO 1 Base Address   */
+#define CMSDK_GPIO2_BASE         (0x41102000)       /* User GPIO 2 Base Address   */
+#define CMSDK_GPIO3_BASE         (0x41103000)       /* User GPIO 3 Base Address   */
+
+#define FMC_CMDSK_GPIO_BASE0        (0x41104000)       /* FMC_CMDSK_GPIO_BASE 0 Base Address (4KB) */
+#define FMC_CMDSK_GPIO_BASE1        (0x41105000)       /* FMC_CMDSK_GPIO_BASE 1 Base Address (4KB)*/
+#define FMC_CMDSK_GPIO_BASE2        (0x41106000)       /* FMC_CMDSK_GPIO_BASE 2 Base Address (4KB)*/
+#define FMC_USER_AHB_BASE           (0x41107000)       /* FMC_USER_AHB_BASE     Base Address (4KB)*/
+
+#define DMA0_BASE                (0x41200000)       /* DMA0 (4KB) */
+#define DMA1_BASE                (0x41201000)       /* DMA1 (4KB) */
+#define DMA2_BASE                (0x41202000)       /* DMA2 (4KB) */
+#define DMA3_BASE                (0x41203000)       /* DMA3 (4KB) */
+
+#define USER_APB0_BASE           (0x41700000)       /* User APB0 */
+#define USER_APB1_BASE           (0x41701000)       /* User APB1 */
+#define USER_APB2_BASE           (0x41702000)       /* User APB2 */
+#define USER_APB3_BASE           (0x41703000)       /* User APB3 */
+
+#define MPS3_I2C0_BASE           (0x49200000)       /* Touch Screen I2C Base Address */
+#define MPS3_I2C1_BASE           (0x49201000)       /* Audio Interface I2C Base Address */
+#define MPS3_SSP2_BASE           (0x49202000)       /* ADC SPI PL022 Base Address   */
+#define MPS3_SSP3_BASE           (0x49203000)       /* Shield 0 SPI PL022 Base Address   */
+
+#define MPS3_SSP4_BASE           (0x49204000)       /* Shield 1 SPI PL022 Base Address   */
+#define MPS3_I2C2_BASE           (0x49205000)       /* Shield 0 SBCon Base Address */
+#define MPS3_I2C3_BASE           (0x49206000)       /* Shield 1 SBCon Base Address */
+
+#define USER_APB_BASE            (0x49207000)       /* User APB Base Address */
+/* #undef MPS3_I2C4_BASE */
+#define MPS3_I2C5_BASE           (0x49208000)       /* DDR EPROM I2C SBCon Base Address */
+#define MPS3_SCC_BASE            (0x49300000)       /* SCC Base Address    */
+#define MPS3_AAIC_I2S_BASE       (0x49301000)       /* Audio Interface I2S Base Address */
+#define MPS3_FPGAIO_BASE         (0x49302000)       /* FPGA IO Base Address */
+/* #undef PL011_UART0_BASE */
+#define CMSDK_UART0_BASE         (0x49303000)       /* UART 0 Base Address */
+#define CMSDK_UART1_BASE         (0x49304000)       /* UART 1 Base Address */
+#define CMSDK_UART2_BASE         (0x49305000)       /* UART 2 Base Address */
+#define CMSDK_UART3_BASE         (0x49306000)       /* UART 3 Base Address Shield 0*/
+
+#define ETHOS_U_NPU_BASE           (0x40004000)    /* Ethos-U NPU base address*/
+#define ETHOS_U_NPU_TA0_BASE       (0x48103000)    /* Ethos-U NPU's timing adapter 0 base address */
+#define ETHOS_U_NPU_TA1_BASE       (0x48103200)    /* Ethos-U NPU's timing adapter 1 base address */
+
+#define CMSDK_UART4_BASE         (0x49307000)       /* UART 4 Base Address Shield 1*/
+#define CMSDK_UART5_BASE         (0x49308000)       /* UART 5 Base Address */
+/* #undef HDMI_AUDIO_BASE */
+#define CLCD_CONFIG_BASE         (0x4930A000)       /* CLCD CONFIG Base Address */
+#define RTC_BASE                 (0x4930B000)       /* RTC Base address */
+#define SMSC9220_BASE            (0x41400000)       /* Ethernet SMSC9220 Base Address */
+#define USB_BASE                 (0x41500000)       /* USB Base Address */
+/* #undef CMSDK_SDIO_BASE */
+/* #undef MPS3_CLCD_BASE */
+/* #undef MPS3_eMMC_BASE */
+/* #undef USER_BASE */
+
+#define QSPI_XIP_BASE            (0x41800000)       /* QSPI XIP config Base Address */
+#define QSPI_WRITE_BASE          (0x41801000)       /* QSPI write config Base Address */
+
+/******************************************************************************/
+/*                      Secure Peripheral memory map                          */
+/******************************************************************************/
+
+#define MPC_ISRAM0_BASE_S        (0x50083000)       /* ISRAM0 Memory Protection Controller Secure base address */
+#define MPC_ISRAM1_BASE_S        (0x50084000)       /* ISRAM1 Memory Protection Controller Secure base address */
+
+#define SEC_CMSDK_GPIO0_BASE     (0x51100000)       /* User GPIO 0 Base Address   */
+#define SEC_CMSDK_GPIO1_BASE     (0x51101000)       /* User GPIO 0 Base Address   */
+#define SEC_CMSDK_GPIO2_BASE     (0x51102000)       /* User GPIO 0 Base Address   */
+#define SEC_CMSDK_GPIO3_BASE     (0x51103000)       /* User GPIO 0 Base Address   */
+
+#define SEC_AHB_USER0_BASE       (0x51104000)       /* AHB USER 0 Base Address (4KB) */
+#define SEC_AHB_USER1_BASE       (0x51105000)       /* AHB USER 1 Base Address (4KB)*/
+#define SEC_AHB_USER2_BASE       (0x51106000)       /* AHB USER 2 Base Address (4KB)*/
+#define SEC_AHB_USER3_BASE       (0x51107000)       /* AHB USER 3 Base Address (4KB)*/
+
+#define SEC_DMA0_BASE            (0x51200000)       /* DMA0 (4KB) */
+#define SEC_DMA1_BASE            (0x51201000)       /* DMA1 (4KB) */
+#define SEC_DMA2_BASE            (0x51202000)       /* DMA2 (4KB) */
+#define SEC_DMA3_BASE            (0x51203000)       /* DMA3 (4KB) */
+
+#define SEC_USER_APB0_BASE       (0x51700000)       /* User APB0 */
+#define SEC_USER_APB1_BASE       (0x51701000)       /* User APB1 */
+#define SEC_USER_APB2_BASE       (0x51702000)       /* User APB2 */
+#define SEC_USER_APB3_BASE       (0x51703000)       /* User APB3 */
+
+#define SEC_MPS3_I2C0_BASE       (0x59200000)       /* Touch Screen I2C Base Address */
+#define SEC_MPS3_I2C1_BASE       (0x59201000)       /* Audio Interface I2C Base Address */
+#define SEC_MPS3_SSP2_BASE       (0x59202000)       /* ADC SPI PL022 Base Address   */
+#define SEC_MPS3_SSP3_BASE       (0x59203000)       /* Shield 0 SPI PL022 Base Address   */
+
+#define SEC_MPS3_SSP4_BASE       (0x59204000)       /* Shield 1 SPI PL022 Base Address   */
+#define SEC_MPS3_I2C2_BASE       (0x59205000)       /* Shield 0 SBCon Base Address */
+#define SEC_MPS3_I2C3_BASE       (0x59206000)       /* Shield 1 SBCon Base Address */
+
+/* #undef SEC_MPS3_I2C4_BASE */
+#define SEC_MPS3_I2C5_BASE       (0x59208000)       /* DDR EPROM I2C SBCon Base Address */
+#define SEC_MPS3_SCC_BASE        (0x59300000)       /* SCC Base Address    */
+#define SEC_MPS3_AAIC_I2S_BASE   (0x59301000)       /* Audio Interface I2S Base Address */
+#define SEC_MPS3_FPGAIO_BASE     (0x59302000)       /* FPGA IO Base Address */
+#define SEC_CMSDK_UART0_BASE     (0x59303000)       /* UART 0 Base Address */
+#define SEC_CMSDK_UART1_BASE     (0x59304000)       /* UART 1 Base Address */
+#define SEC_CMSDK_UART2_BASE     (0x59305000)       /* UART 2 Base Address */
+#define SEC_CMSDK_UART3_BASE     (0x59306000)       /* UART 3 Base Address Shield 0*/
+
+#define SEC_CMSDK_UART4_BASE     (0x59307000)       /* UART 4 Base Address Shield 1*/
+#define SEC_CMSDK_UART5_BASE     (0x59308000)       /* UART 5 Base Address */
+/* #undef SEC_HDMI_AUDIO_BASE */
+#define SEC_CLCD_CONFIG_BASE     (0x5930A000)       /* CLCD CONFIG Base Address */
+#define SEC_RTC_BASE             (0x5930B000)       /* RTC Base address */
+
+
+
+
+#define SEC_SMSC9220_BASE        (0x51400000)       /* Ethernet SMSC91C111 Base Address */
+#define SEC_USB_BASE             (0x51500000)       /* USB Base Address */
+
+#define SEC_ETHOS_U_NPU_BASE       (0x50004000)   /* Ethos-U NPU base address*/
+#define SEC_ETHOS_U_NPU_TA0_BASE   (0x58103000)   /* Ethos-U NPU's timing adapter 0 base address */
+#define SEC_ETHOS_U_NPU_TA1_BASE   (0x58103200)   /* Ethos-U NPU's timing adapter 1 base address */
+
+/* #undef SEC_USER_BASE */
+
+#define SEC_QSPI_XIP_BASE        (0x51800000)       /* QSPI XIP config Base Address */
+#define SEC_QSPI_WRITE_BASE      (0x51801000)       /* QSPI write config Base Address */
+
+/******************************************************************************/
+/*                                  MPCs                                      */
+/******************************************************************************/
+
+#define MPC_ISRAM0_BASE_S        (0x50083000)       /* Internal SRAM 0 MPC */
+#define MPC_ISRAM1_BASE_S        (0x50084000)       /* Internal SRAM 1 MPC */
+#define MPC_BRAM_BASE_S          (0x57000000)       /* SRAM Memory Protection Controller Secure base address */
+#define MPC_QSPI_BASE_S          (0x57001000)       /* QSPI Memory Protection Controller Secure base address */
+#define MPC_DDR4_BASE_S          (0x57002000)       /* DDR4 Memory Protection Controller Secure base address */
+
+#endif /* PERIPHERAL_MEMMAP_H */
diff --git a/source/hal/source/platform/mps3/source/platform_drivers.c b/source/hal/source/platform/mps3/source/platform_drivers.c
index d1c3da2..801cd0b 100644
--- a/source/hal/source/platform/mps3/source/platform_drivers.c
+++ b/source/hal/source/platform/mps3/source/platform_drivers.c
@@ -136,7 +136,17 @@
     info("CPU ID: 0x%08" PRIx32 "\n", id);
 
     if(EXTRACT_BITS(id, 15, 8) == 0xD2) {
-        if (EXTRACT_BITS(id, 7, 4) == 2) {
+        if (EXTRACT_BITS(id, 7, 4) == 3) {
+            info ("CPU: Cortex-M85 r%dp%d\n\n",
+                  EXTRACT_BITS(id, 23, 20),EXTRACT_BITS(id, 3, 0));
+            /* @TODO: Remove CPU_CORTEX_M55 from here once CMake min version is > 3.21.0 or when
+             * toolchains officially support Cortex-M85. Currently, for CMake versions older than
+             * this, Cortex-M85 is built using Cortex-M55 flags. */
+#if defined (CPU_CORTEX_M55) || defined (ARMv81MML_DSP_DP_MVE_FP) || defined(CPU_CORTEX_M85)
+            /* CPU ID should be "0x_41_0f_d2_30" for Cortex-M85 */
+            return 0;
+#endif /* (CPU_CORTEX_M55) || (ARMv81MML_DSP_DP_MVE_FP) || (CPU_CORTEX_M85) */
+        } else if (EXTRACT_BITS(id, 7, 4) == 2) {
             info ("CPU: Cortex-M55 r%dp%d\n\n",
                 EXTRACT_BITS(id, 23, 20),EXTRACT_BITS(id, 3, 0));
 #if defined (CPU_CORTEX_M55)
diff --git a/source/hal/source/platform/native/CMakeLists.txt b/source/hal/source/platform/native/CMakeLists.txt
index e0cc711..41d68e9 100644
--- a/source/hal/source/platform/native/CMakeLists.txt
+++ b/source/hal/source/platform/native/CMakeLists.txt
@@ -19,7 +19,7 @@
 #    Native target platform support library             #
 #########################################################
 
-cmake_minimum_required(VERSION 3.15.6)
+cmake_minimum_required(VERSION 3.16.3)
 
 set(PLATFORM_DRIVERS_TARGET platform_drivers)
 
@@ -73,4 +73,5 @@
 message(STATUS "*******************************************************")
 message(STATUS "Library                                : " ${PLATFORM_DRIVERS_TARGET})
 message(STATUS "CMAKE_SYSTEM_PROCESSOR                 : " ${CMAKE_SYSTEM_PROCESSOR})
+message(STATUS "CMAKE_SYSTEM_ARCH                      : " ${CMAKE_SYSTEM_ARCH})
 message(STATUS "*******************************************************")
diff --git a/source/hal/source/platform/simple/CMakeLists.txt b/source/hal/source/platform/simple/CMakeLists.txt
index 1b8da30..1ab8e25 100644
--- a/source/hal/source/platform/simple/CMakeLists.txt
+++ b/source/hal/source/platform/simple/CMakeLists.txt
@@ -19,7 +19,7 @@
 #       A generic (simple) platform support library     #
 #########################################################
 
-cmake_minimum_required(VERSION 3.15.6)
+cmake_minimum_required(VERSION 3.16.3)
 set(PLATFORM_DRIVERS_TARGET platform_drivers)
 project(${PLATFORM_DRIVERS_TARGET}
     DESCRIPTION     "Platform drivers library for a generic target"
@@ -124,4 +124,5 @@
 message(STATUS "*******************************************************")
 message(STATUS "Library                                : " ${PLATFORM_DRIVERS_TARGET})
 message(STATUS "CMAKE_SYSTEM_PROCESSOR                 : " ${CMAKE_SYSTEM_PROCESSOR})
+message(STATUS "CMAKE_SYSTEM_ARCH                      : " ${CMAKE_SYSTEM_ARCH})
 message(STATUS "*******************************************************")
diff --git a/source/log/CMakeLists.txt b/source/log/CMakeLists.txt
index 1de737e..79ebc2d 100644
--- a/source/log/CMakeLists.txt
+++ b/source/log/CMakeLists.txt
@@ -18,7 +18,7 @@
 #######################################################
 # Header-only logging definitions as an interface lib.#
 #######################################################
-cmake_minimum_required(VERSION 3.15.6)
+cmake_minimum_required(VERSION 3.16.3)
 
 set(BSP_LOGGING_TARGET log)
 
@@ -40,4 +40,5 @@
 message(STATUS "*******************************************************")
 message(STATUS "Library                                : " ${BSP_LOGGING_TARGET})
 message(STATUS "CMAKE_SYSTEM_PROCESSOR                 : " ${CMAKE_SYSTEM_PROCESSOR})
+message(STATUS "CMAKE_SYSTEM_ARCH                      : " ${CMAKE_SYSTEM_ARCH})
 message(STATUS "*******************************************************")
diff --git a/source/log/include/log_macros.h b/source/log/include/log_macros.h
index 15f4dd5..3d42e47 100644
--- a/source/log/include/log_macros.h
+++ b/source/log/include/log_macros.h
@@ -70,4 +70,4 @@
 }
 #endif
 
-#endif /* ML_EMBEDDED_CORE_LOG_H */
\ No newline at end of file
+#endif /* ML_EMBEDDED_CORE_LOG_H */
diff --git a/source/math/CMakeLists.txt b/source/math/CMakeLists.txt
index eab6622..eee8f75 100644
--- a/source/math/CMakeLists.txt
+++ b/source/math/CMakeLists.txt
@@ -33,7 +33,7 @@
 
 target_link_libraries(arm_math PRIVATE log)
 
-if (${CMAKE_SYSTEM_PROCESSOR} STREQUAL cortex-m55)
+if ("${CMAKE_SYSTEM_PROCESSOR}" STREQUAL "cortex-m55" OR "${CMAKE_SYSTEM_ARCH}" STREQUAL "armv8.1-m.main")
     include(${CMAKE_SCRIPTS_DIR}/cmsis-dsp.cmake)
     target_link_libraries(arm_math PUBLIC cmsis-dsp)
 endif ()
@@ -41,4 +41,5 @@
 message(STATUS "*******************************************************")
 message(STATUS "Library                                : " arm_math)
 message(STATUS "CMAKE_SYSTEM_PROCESSOR                 : " ${CMAKE_SYSTEM_PROCESSOR})
+message(STATUS "CMAKE_SYSTEM_ARCH                      : " ${CMAKE_SYSTEM_ARCH})
 message(STATUS "*******************************************************")
diff --git a/source/profiler/CMakeLists.txt b/source/profiler/CMakeLists.txt
index 0a9c338..7e3db3e 100644
--- a/source/profiler/CMakeLists.txt
+++ b/source/profiler/CMakeLists.txt
@@ -39,4 +39,5 @@
 message(STATUS "*******************************************************")
 message(STATUS "Library                                : " profiler)
 message(STATUS "CMAKE_SYSTEM_PROCESSOR                 : " ${CMAKE_SYSTEM_PROCESSOR})
+message(STATUS "CMAKE_SYSTEM_ARCH                      : " ${CMAKE_SYSTEM_ARCH})
 message(STATUS "*******************************************************")