diff --git a/scripts/cmake/platforms/mps3/sse-310/mps3-sse-310.sct b/scripts/cmake/platforms/mps3/sse-310/mps3-sse-310.sct
new file mode 100644
index 0000000..452b0fe
--- /dev/null
+++ b/scripts/cmake/platforms/mps3/sse-310/mps3-sse-310.sct
@@ -0,0 +1,140 @@
+;  Copyright (c) 2021 Arm Limited. All rights reserved.
+;  SPDX-License-Identifier: Apache-2.0
+;
+;  Licensed under the Apache License, Version 2.0 (the "License");
+;  you may not use this file except in compliance with the License.
+;  You may obtain a copy of the License at
+;
+;      http://www.apache.org/licenses/LICENSE-2.0
+;
+;  Unless required by applicable law or agreed to in writing, software
+;  distributed under the License is distributed on an "AS IS" BASIS,
+;  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+;  See the License for the specific language governing permissions and
+;  limitations under the License.
+
+; *************************************************************
+; ***       Scatter-Loading Description File                ***
+; *************************************************************
+; Please see docs/sections/appendix.md for memory mapping
+; information.
+;
+; Note: Ethos-U NPU can access BRAM, internal SRAM and the DDR
+;       sections => activation buffers and the model should
+;       only be placed in those regions.
+;
+
+;---------------------------------------------------------
+; First load region (SRAM/BRAM) 2MiB region
+;---------------------------------------------------------
+LOAD_REGION_0       0x11000000                  0x00200000
+{
+    ;-----------------------------------------------------
+    ; 0.5 MiB of SRAM/BRAM region. Our vector table also
+    ; resides here as the default INITSVTOR is 0x11000000.
+    ; We currently do not use the ITCM for any code, but
+    ; could potentially put some critical code in there
+    ; if we need to.
+    ;-----------------------------------------------------
+    bram.bin        0x11000000                  0x00080000
+    {
+        *.o (RESET, +First)
+        * (InRoot$$Sections)
+
+        ; Essentially only RO (code + data)
+        .ANY (+RO)
+    }
+
+    ;-----------------------------------------------------
+    ; Next 0.5 MiB of SRAM/BRAM region for RO, RW and ZI
+    ; data, 8 byte aligned.
+    ;-----------------------------------------------------
+    data.bin        0x11080000 ALIGN 8          0x00080000
+    {
+        ; Any RO-DATA
+        .ANY (+RO-DATA)
+
+        ; Any R/W and/or zero initialised data
+        .ANY(+RW +ZI)
+    }
+
+    ;-----------------------------------------------------
+    ; 768 KiB of remaining part of the 1MiB BRAM used as
+    ; heap space.
+    ;-----------------------------------------------------
+    ARM_LIB_HEAP    0x11100000 EMPTY ALIGN 8    0x000C0000
+    {}
+
+    ;-----------------------------------------------------
+    ; 32 kiB of stack space occupying the DTCM region.
+    ;-----------------------------------------------------
+    ARM_LIB_STACK   0x30000000 EMPTY ALIGN 8    0x00008000
+    {}
+
+    ;-----------------------------------------------------
+    ; FPGA internal SRAM of 2MiB - reserved for activation
+    ; buffers. The total memory is 4 MiB (we are choosing
+    ; to not use the other bank). This region should have
+    ; 3 cycle read latency from both CPU and Ethos-U NPU.
+    ;-----------------------------------------------------
+    isram.bin       0x31000000  UNINIT ALIGN 16 0x00200000
+    {
+        ; Cache area (if used)
+        *.o (.bss.NoInit.ethos_u_cache)
+
+        ; activation buffers a.k.a tensor arena when
+        ; memory mode sram only or shared sram
+        *.o (.bss.NoInit.activation_buf_sram)
+    }
+}
+
+;---------------------------------------------------------
+; Second load region (DDR)
+;---------------------------------------------------------
+LOAD_REGION_1       0x70000000                  0x02000000
+{
+    ;-----------------------------------------------------
+    ; 32 MiB of DDR space for neural network model,
+    ; input vectors and labels. If the activation buffer
+    ; size required by the network is bigger than the
+    ; SRAM size available, it is accommodated here.
+    ;-----------------------------------------------------
+    ddr.bin        0x70000000 ALIGN 16         0x02000000
+    {
+        ; nn model's baked in input matrices
+        *.o (ifm)
+
+        ; nn model's default space
+        *.o (nn_model)
+
+        ; labels
+        *.o (labels)
+
+        ; activation buffers a.k.a tensor arena when memory mode dedicated sram
+        *.o (activation_buf_dram)
+    }
+
+    ;-----------------------------------------------------
+    ; The following regions are for use by the FVP to
+    ; allow loading or dumping of dynamic data into or
+    ; from the memory. These regions are mentioned in
+    ; the CMake subsystem profile. Do not change the
+    ; addresses and sizes below in isolation.
+    ;-----------------------------------------------------
+    ; 32 MiB of model space for run-time load of model
+    ;-----------------------------------------------------
+    runtime_model   0x90000000 EMPTY ALIGN 16   0x02000000
+    {}
+
+    ;-----------------------------------------------------
+    ; 16 MiB of IFM space for run-time loading (FVP only)
+    ;-----------------------------------------------------
+    runtime_ifm     0x92000000 EMPTY ALIGN 16   0x01000000
+    {}
+
+    ;-----------------------------------------------------
+    ; 16 MiB of OFM space for run-time loading (FVP only)
+    ;-----------------------------------------------------
+    runtime_ofm     0x93000000 EMPTY ALIGN 16   0x01000000
+    {}
+}