diff --git a/scripts/cmake/timing_adapter/ta_config_u65_high_end.cmake b/scripts/cmake/timing_adapter/ta_config_u65_high_end.cmake
index d1fdc00..e046d59 100644
--- a/scripts/cmake/timing_adapter/ta_config_u65_high_end.cmake
+++ b/scripts/cmake/timing_adapter/ta_config_u65_high_end.cmake
@@ -26,8 +26,8 @@
 message(STATUS "using TA0_BASE @ ${TA0_BASE}; TA1_BASE @ ${TA1_BASE}.")
 
 # Timing adapter settings for AXI0
-set(TA0_MAXR        "16"        CACHE STRING "6-bit field. Max no. of pending reads. 0=infinite")
-set(TA0_MAXW        "16"        CACHE STRING "6-bit field. Max no. of pending writes. 0=infinite")
+set(TA0_MAXR        "16"       CACHE STRING "6-bit field. Max no. of pending reads. 0=infinite")
+set(TA0_MAXW        "16"       CACHE STRING "6-bit field. Max no. of pending writes. 0=infinite")
 set(TA0_MAXRW       "0"        CACHE STRING "6-bit field. Max no. of pending reads+writes. 0=infinite")
 set(TA0_RLATENCY    "32"       CACHE STRING "12-bit field. Minimum latency (clock cycles) from AVALID to RVALID.")
 set(TA0_WLATENCY    "32"       CACHE STRING "12-bit field. Minimum latency (clock cycles) from WVALID&WLAST to BVALID.")
@@ -46,19 +46,19 @@
 
 # Timing adapter settings for AXI1
 set(TA1_MAXR        "24"       CACHE STRING "6-bit field. Max no. of pending reads. 0=infinite")
-set(TA1_MAXW        "112"       CACHE STRING "6-bit field. Max no. of pending writes. 0=infinite")
-set(TA1_MAXRW       "0"       CACHE STRING "6-bit field. Max no. of pending reads+writes. 0=infinite")
+set(TA1_MAXW        "12"       CACHE STRING "6-bit field. Max no. of pending writes. 0=infinite")
+set(TA1_MAXRW       "0"        CACHE STRING "6-bit field. Max no. of pending reads+writes. 0=infinite")
 set(TA1_RLATENCY    "500"      CACHE STRING "12-bit field. Minimum latency (clock cycles) from AVALID to RVALID.")
-set(TA1_WLATENCY    "250"       CACHE STRING "12-bit field. Minimum latency (clock cycles) from WVALID&WLAST to BVALID.")
+set(TA1_WLATENCY    "250"      CACHE STRING "12-bit field. Minimum latency (clock cycles) from WVALID&WLAST to BVALID.")
 set(TA1_PULSE_ON    "4000"     CACHE STRING "No. of cycles addresses let through (0-65535).")
-set(TA1_PULSE_OFF   "1000"      CACHE STRING "No. of cycles addresses blocked (0-65535).")
-set(TA1_BWCAP       "1172"      CACHE STRING "16-bit field. Max no. of 64-bit words transfered per pulse cycle 0=infinite")
-set(TA1_PERFCTRL    "0"       CACHE STRING "6-bit field selecting an event for event counter 0=default")
-set(TA1_PERFCNT     "0"       CACHE STRING "32-bit event counter")
-set(TA1_MODE        "1"       CACHE STRING "Bit 0: 1=enable dynamic clocking to avoid underrun;
+set(TA1_PULSE_OFF   "1000"     CACHE STRING "No. of cycles addresses blocked (0-65535).")
+set(TA1_BWCAP       "1172"     CACHE STRING "16-bit field. Max no. of 64-bit words transfered per pulse cycle 0=infinite")
+set(TA1_PERFCTRL    "0"        CACHE STRING "6-bit field selecting an event for event counter 0=default")
+set(TA1_PERFCNT     "0"        CACHE STRING "32-bit event counter")
+set(TA1_MODE        "1"        CACHE STRING "Bit 0: 1=enable dynamic clocking to avoid underrun;
                                             Bit 1: 1=enable random AR reordering (0=default);
                                             Bit 2: 1=enable random R reordering (0=default);
                                             Bit 3: 1=enable random B reordering (0=default);
                                             Bit 11-4: Frequency scale 0=full speed, 255=(1/256) speed")
-set(TA1_HISTBIN     "0"       CACHE STRING "Controls which histogram bin (0-15) that should be accessed by HISTCNT.")
-set(TA1_HISTCNT     "0"       CACHE STRING "32-bit field. Read/write the selected histogram bin.")
+set(TA1_HISTBIN     "0"        CACHE STRING "Controls which histogram bin (0-15) that should be accessed by HISTCNT.")
+set(TA1_HISTCNT     "0"        CACHE STRING "32-bit field. Read/write the selected histogram bin.")