MLECO-2919: Restructuring to standardise HAL APIs
* LCD module component created (removed from individual
platform packs).
* retarget.c moved out into its own component that wraps
the uart module. It also have the native stub for
GetLine => paved the way for removing data_acq module
from profiles.
* shortened names for components' dir for npu and ta
* remove peripheral_memmap and peripheral_irqs headers
from platform_drivers.h. There should be no need for
these to be included in the top level now. These should
be private headers.
* cmsis_device moved in as a component.
* Pyenv created by set_up_default_resource.py will also
install packages that CMake's source generator needs.
TODO's:
* Remove timer from profiles (MLECO-3096)
Change-Id: I9d6ea2f4f291788f40a16ed507019563c8d7f205
diff --git a/source/hal/source/components/cmsis_device/CMakeLists.txt b/source/hal/source/components/cmsis_device/CMakeLists.txt
new file mode 100644
index 0000000..dcaeff5
--- /dev/null
+++ b/source/hal/source/components/cmsis_device/CMakeLists.txt
@@ -0,0 +1,89 @@
+#----------------------------------------------------------------------------
+# Copyright (c) 2022 Arm Limited. All rights reserved.
+# SPDX-License-Identifier: Apache-2.0
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#----------------------------------------------------------------------------
+
+#########################################################
+# Generic CMSIS Start up library for Cortex-M targets #
+#########################################################
+cmake_minimum_required(VERSION 3.15.6)
+
+set(CMSIS_DEVICE_TARGET cmsis_device)
+set(CPU_HEADER_TARGET cmsis_device_cpu_header)
+
+project(${CMSIS_DEVICE_TARGET}
+ DESCRIPTION "Generic CMSIS start up file for Cortex-M targets"
+ LANGUAGES C CXX ASM)
+
+# 1. We should be cross-compiling (non-native target)
+if (NOT ${CMAKE_CROSSCOMPILING})
+ message(FATAL_ERROR "No ${CMSIS_DEVICE_TARGET} support for this target.")
+endif()
+
+# 2. Check if CMSIS sources have been defined
+if (NOT DEFINED CMSIS_SRC_PATH)
+ message(FATAL_ERROR "CMSIS_SRC_PATH path should be defined for ${CMSIS_DEVICE_TARGET}.")
+endif()
+
+# 3.1 Create an interface library for CPU header only
+add_library(${CPU_HEADER_TARGET} INTERFACE)
+
+## Interface include directories:
+target_include_directories(${CPU_HEADER_TARGET}
+ INTERFACE
+ include
+ ${CMSIS_SRC_PATH}/CMSIS/Core/Include
+ ${CMSIS_SRC_PATH}/Device/ARM/${ARM_CPU}/Include
+ ${CMSIS_SRC_PATH}/Device/ARM/${ARM_CPU}/Include/Template)
+
+# 3.2 Create static library
+add_library(${CMSIS_DEVICE_TARGET} STATIC)
+
+## Sources - public
+target_sources(${CMSIS_DEVICE_TARGET}
+ PUBLIC
+ source/handlers.c)
+
+## Sources - private
+target_sources(${CMSIS_DEVICE_TARGET}
+ PRIVATE
+ ${CMSIS_SRC_PATH}/Device/ARM/${ARM_CPU}/Source/system_${ARM_CPU}.c
+ ${CMSIS_SRC_PATH}/Device/ARM/${ARM_CPU}/Source/startup_${ARM_CPU}.c)
+
+# Device definition needs to be set, is checked in source files to include correct header
+target_compile_definitions(${CMSIS_DEVICE_TARGET} PUBLIC ${ARM_CPU})
+
+# Tell linker that reset interrupt handler is our entry point
+target_link_options(
+ ${CMSIS_DEVICE_TARGET}
+ INTERFACE
+ --entry Reset_Handler)
+
+# Link libraries
+target_link_libraries(${CMSIS_DEVICE_TARGET}
+ PUBLIC
+ ${CPU_HEADER_TARGET})
+
+# Check if semihosting configuration is available
+if (COMMAND configure_semihosting)
+ configure_semihosting(${CMSIS_DEVICE_TARGET} OFF)
+endif()
+
+# 4 Display status:
+message(STATUS "CMAKE_CURRENT_SOURCE_DIR: " ${CMAKE_CURRENT_SOURCE_DIR})
+message(STATUS "*******************************************************")
+message(STATUS "Library : " ${CMSIS_DEVICE_TARGET})
+message(STATUS "CMAKE_SYSTEM_PROCESSOR : " ${CMAKE_SYSTEM_PROCESSOR})
+message(STATUS "*******************************************************")
diff --git a/source/hal/source/components/cmsis_device/include/RTE_Components.h b/source/hal/source/components/cmsis_device/include/RTE_Components.h
new file mode 100644
index 0000000..8988e9b
--- /dev/null
+++ b/source/hal/source/components/cmsis_device/include/RTE_Components.h
@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2022 Arm Limited. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+#if defined(CPU_HEADER_FILE)
+#include CPU_HEADER_FILE /* Cortex M system header file from CMSIS. */
+#endif /* CPU_HEADER_FILE */
+
+#endif /* RTE_COMPONENTS_H */
diff --git a/source/hal/source/components/cmsis_device/source/handlers.c b/source/hal/source/components/cmsis_device/source/handlers.c
new file mode 100644
index 0000000..a3119e6
--- /dev/null
+++ b/source/hal/source/components/cmsis_device/source/handlers.c
@@ -0,0 +1,152 @@
+/*
+ * Copyright (c) 2021 Arm Limited. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include "RTE_Components.h"
+
+#include <stdio.h>
+#include <inttypes.h>
+
+/**
+ * @brief Dump core registers on stdout
+ */
+static void LogCoreCPURegisters(void)
+{
+ printf("CTRL : 0x%08" PRIx32 "\n", __get_CONTROL());
+ printf("IPSR : 0x%08" PRIx32 "\n", __get_IPSR());
+ printf("APSR : 0x%08" PRIx32 "\n", __get_APSR());
+ printf("xPSR : 0x%08" PRIx32 "\n", __get_xPSR());
+ printf("PSP : 0x%08" PRIx32 "\n", __get_PSP());
+ printf("MSP : 0x%08" PRIx32 "\n", __get_MSP());
+ printf("PRIMASK : 0x%08" PRIx32 "\n", __get_PRIMASK());
+ printf("BASEPRI : 0x%08" PRIx32 "\n", __get_BASEPRI());
+ printf("FAULTMSK: 0x%08" PRIx32 "\n", __get_FAULTMASK());
+}
+
+/**
+ * @brief Default interrupt handler - an infinite loop.
+ **/
+__attribute__((noreturn)) static void DefaultHandler(void)
+{
+ LogCoreCPURegisters();
+ while (1) {
+ /* Without the following line, armclang may optimize away the
+ * infinite loop because it'd be without side effects and thus
+ * undefined behaviour. */
+ __ASM volatile("");
+ }
+}
+
+#define DEFAULT_HANDLER_CALL(type) \
+ do { \
+ printf("\n"); \
+ printf("%s caught by function %s\n", \
+ type, __FUNCTION__); \
+ DefaultHandler(); \
+ } while (0)
+
+#define DEFAULT_ERROR_HANDLER_CALL() \
+ DEFAULT_HANDLER_CALL("Exception")
+
+#define DEFAULT_IRQ_HANDLER_CALL() \
+ DEFAULT_HANDLER_CALL("Interrupt")
+
+/**
+ * Placeholder Exception Handlers for core interrupts.
+ *
+ * Weak definitions provided to be used if the user chooses not
+ * to override them.
+ **/
+
+/**
+ * @brief Non maskable interrupt handler.
+ **/
+__attribute__((weak)) void NMI_Handler(void)
+{
+ DEFAULT_ERROR_HANDLER_CALL();
+}
+
+/**
+ * @brief Hardfault interrupt handler.
+ **/
+__attribute__((weak)) void HardFault_Handler(void)
+{
+ DEFAULT_ERROR_HANDLER_CALL();
+}
+
+/**
+ * @brief Memory management interrupt handler.
+ **/
+__attribute__((weak)) void MemManage_Handler(void)
+{
+ DEFAULT_IRQ_HANDLER_CALL();
+}
+
+/**
+ * @brief Bus fault interrupt handler.
+ **/
+__attribute__((weak)) void BusFault_Handler(void)
+{
+ DEFAULT_ERROR_HANDLER_CALL();
+}
+
+/**
+ * @brief Usage fault interrupt handler.
+ **/
+__attribute__((weak)) void UsageFault_Handler(void)
+{
+ DEFAULT_ERROR_HANDLER_CALL();
+}
+
+/**
+ * @brief Secure access fault interrupt handler.
+ **/
+__attribute__((weak)) void SecureFault_Handler(void)
+{
+ DEFAULT_ERROR_HANDLER_CALL();
+}
+
+/**
+ * @brief Supervisor call interrupt handler.
+ **/
+__attribute__((weak)) void SVC_Handler(void)
+{
+ DEFAULT_IRQ_HANDLER_CALL();
+}
+
+/**
+ * @brief Debug monitor interrupt handler.
+ **/
+__attribute__((weak)) void DebugMon_Handler(void)
+{
+ DEFAULT_IRQ_HANDLER_CALL();
+}
+
+/**
+ * @brief Pending SV call interrupt handler.
+ */
+__attribute__((weak)) void PendSV_Handler(void)
+{
+ DEFAULT_IRQ_HANDLER_CALL();
+}
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/source/hal/source/components/lcd/CMakeLists.txt b/source/hal/source/components/lcd/CMakeLists.txt
new file mode 100644
index 0000000..7378713
--- /dev/null
+++ b/source/hal/source/components/lcd/CMakeLists.txt
@@ -0,0 +1,90 @@
+#----------------------------------------------------------------------------
+# Copyright (c) 2022 Arm Limited. All rights reserved.
+# SPDX-License-Identifier: Apache-2.0
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#----------------------------------------------------------------------------
+
+#########################################################
+# LCD library #
+#########################################################
+
+cmake_minimum_required(VERSION 3.15.6)
+
+project(lcd_component
+ DESCRIPTION "LCD support library"
+ LANGUAGES C CXX ASM)
+
+# Add top level interface library
+set(LCD_IFACE_TARGET lcd_iface)
+add_library(${LCD_IFACE_TARGET} INTERFACE)
+target_include_directories(${LCD_IFACE_TARGET} INTERFACE include)
+
+# Create static library for MPS3 LCD
+set(LCD_MPS3_COMPONENT_TARGET lcd_mps3)
+add_library(${LCD_MPS3_COMPONENT_TARGET} STATIC)
+
+set(CLCD_CONFIG_BASE "0x4930A000" CACHE STRING "LCD configuration base address")
+
+## Include directories - private
+target_include_directories(${LCD_MPS3_COMPONENT_TARGET}
+ PRIVATE
+ source)
+
+## Component sources
+target_sources(${LCD_MPS3_COMPONENT_TARGET}
+ PRIVATE
+ source/glcd_mps3/glcd_mps3.c
+ source/lcd_img.c)
+
+# Compile definitions
+target_compile_definitions(${LCD_MPS3_COMPONENT_TARGET}
+ PRIVATE
+ CLCD_CONFIG_BASE=${CLCD_CONFIG_BASE})
+
+## Add dependencies
+target_link_libraries(${LCD_MPS3_COMPONENT_TARGET} PUBLIC
+ ${LCD_IFACE_TARGET}
+ log)
+
+# Display status
+message(STATUS "CMAKE_CURRENT_SOURCE_DIR: " ${CMAKE_CURRENT_SOURCE_DIR})
+message(STATUS "*******************************************************")
+message(STATUS "Library : " ${LCD_MPS3_COMPONENT_TARGET})
+message(STATUS "*******************************************************")
+
+# Create static library for LCD Stubs
+set(LCD_STUBS_COMPONENT_TARGET lcd_stubs)
+add_library(${LCD_STUBS_COMPONENT_TARGET} STATIC)
+
+## Include directories - private
+target_include_directories(${LCD_STUBS_COMPONENT_TARGET}
+ PRIVATE
+ source)
+
+## Component sources
+target_sources(${LCD_STUBS_COMPONENT_TARGET}
+ PRIVATE
+ source/glcd_stubs/glcd_stubs.c
+ source/lcd_img.c)
+
+## Add dependencies
+target_link_libraries(${LCD_STUBS_COMPONENT_TARGET} PUBLIC
+ ${LCD_IFACE_TARGET}
+ log)
+
+# Display status
+message(STATUS "CMAKE_CURRENT_SOURCE_DIR: " ${CMAKE_CURRENT_SOURCE_DIR})
+message(STATUS "*******************************************************")
+message(STATUS "Library : " ${LCD_STUBS_COMPONENT_TARGET})
+message(STATUS "*******************************************************")
\ No newline at end of file
diff --git a/source/hal/source/components/lcd/include/lcd_img.h b/source/hal/source/components/lcd/include/lcd_img.h
new file mode 100644
index 0000000..b447767
--- /dev/null
+++ b/source/hal/source/components/lcd/include/lcd_img.h
@@ -0,0 +1,90 @@
+/*
+ * Copyright (c) 2021-2022 Arm Limited. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef LCD_IMG_H
+#define LCD_IMG_H
+
+#include <stdint.h>
+#include <stddef.h>
+#include <stdbool.h>
+
+/**
+ * @brief Initialise the LCD
+ * @return 0 if successful, error code otherwise.
+ **/
+int lcd_init(void);
+
+/**
+ * @brief Display a given image on the LCD. This allows displaying 8 bit
+ * single or multi-channel images on the LCD.
+ * @param[in] data Pointer to start of the image.
+ * @param[in] width Width of this image.
+ * @param[in] height Image height.
+ * @param[in] channels Number of channels.
+ * @param[in] pos_x Screen position x co-ordinate.
+ * @param[in] pos_y Screen position y co-ordinate.
+ * @param[in] downsample_factor Factor by which the image needs to be
+ * downsampled.
+ * @return 0 if successful, non-zero otherwise.
+ **/
+int lcd_display_image(const uint8_t* data, const uint32_t width,
+ const uint32_t height, const uint32_t channels,
+ const uint32_t pos_x, const uint32_t pos_y,
+ const uint32_t downsample_factor);
+
+/**
+ * @brief Display a given image on the LCD. This allows displaying 8 bit
+ * single or multi-channel images on the LCD.
+ * @param[in] str Pointer to a null terminated string.
+ * @param[in] str_sz Length of the string.
+ * @param[in] pos_x Screen position x co-ordinate.
+ * @param[in] pos_y Screen position y co-ordinate.
+ * @param[in] allow_multiple_lines The function will try and spread
+ * the string into multiple lines if
+ * they don't fit in one.
+ * @return 0 if successful, non-zero otherwise.
+ **/
+int lcd_display_text(const char* str, const size_t str_sz,
+ const uint32_t pos_x, const uint32_t pos_y,
+ const bool allow_multiple_lines);
+
+/**
+ * @brief Display a box with given color on LCD.
+ * @param[in] pos_x Screen position x co-ordinate.
+ * @param[in] pos_y Screen position y co-ordinate.
+ * @param[in] width Width.
+ * @param[in] height Height.
+ * @param[in] color Fill color.
+ * @return 0 if successful, non-zero otherwise.
+ **/
+int lcd_display_box(const uint32_t pos_x, const uint32_t pos_y,
+ const uint32_t width, const uint32_t height, const uint16_t color);
+
+/**
+ * @brief Clear LCD.
+ * @param[in] color Fill color.
+ * @return 0 if successful, non-zero otherwise.
+ **/
+int lcd_clear(const uint16_t color);
+
+/**
+ * @brief Set text color.
+ * @param[in] color Fill color.
+ * @return 0 if successful, non-zero otherwise.
+ **/
+int lcd_set_text_color(const uint16_t color);
+
+#endif /* LCD_IMG_H */
diff --git a/source/hal/source/components/lcd/source/glcd.h b/source/hal/source/components/lcd/source/glcd.h
new file mode 100644
index 0000000..a54c6d0
--- /dev/null
+++ b/source/hal/source/components/lcd/source/glcd.h
@@ -0,0 +1,202 @@
+/*
+ * Copyright (c) 2021-2022 Arm Limited. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef GLCD_H
+#define GLCD_H
+
+#include <stdint.h>
+
+/******************************************************************************
+ Color coding
+ GLCD is coded: 15..11 red, 10..5 green, 4..0 blue (unsigned short)
+ GLCD_R5, GLCD_G6, GLCD_B5
+ original coding: 17..12 red, 11..6 green, 5..0 blue
+ ORG_R6, ORG_G6, ORG_B6
+
+ ORG_R1..5 = GLCD_R0..4, ORG_R0 = GLCD_R4
+ ORG_G0..5 = GLCD_G0..5,
+ ORG_B1..5 = GLCD_B0..4, ORG_B0 = GLCD_B4
+
+ GLCD RGB color definitions
+******************************************************************************/
+#define Black 0x0000 /* 0, 0, 0 */
+#define Navy 0x000F /* 0, 0, 128 */
+#define DarkGreen 0x03E0 /* 0, 128, 0 */
+#define DarkCyan 0x03EF /* 0, 128, 128 */
+#define Maroon 0x7800 /* 128, 0, 0 */
+#define Purple 0x780F /* 128, 0, 128 */
+#define Olive 0x7BE0 /* 128, 128, 0 */
+#define LightGrey 0xC618 /* 192, 192, 192 */
+#define DarkGrey 0x7BEF /* 128, 128, 128 */
+#define Blue 0x001F /* 0, 0, 255 */
+#define Green 0x07E0 /* 0, 255, 0 */
+#define Cyan 0x07FF /* 0, 255, 255 */
+#define Red 0xF800 /* 255, 0, 0 */
+#define Magenta 0xF81F /* 255, 0, 255 */
+#define Yellow 0xFFE0 /* 255, 255, 0 */
+#define White 0xFFFF /* 255, 255, 255 */
+
+/************************** Orientation configuration ************************/
+#ifndef LANDSCAPE
+#define LANDSCAPE 1 /* 1 for landscape, 0 for portrait. */
+#endif
+#ifndef ROTATE180
+#define ROTATE180 1 /* 1 to rotate the screen for 180 deg. */
+#endif
+
+/*------------------------- Speed dependent settings -------------------------*/
+
+/* If processor works on high frequency delay has to be increased, it can be
+ increased by factor 2^N by this constant. */
+#define DELAY_2N 8
+
+/*---------------------- Graphic LCD size definitions ------------------------*/
+#if (LANDSCAPE == 1)
+ #define GLCD_WIDTH 320 /* Screen Width (in pixels). */
+ #define GLCD_HEIGHT 240 /* Screen Height (in pixels). */
+#else
+ #define GLCD_WIDTH 240 /* Screen Width (in pixels). */
+ #define GLCD_HEIGHT 320 /* Screen Height (in pixels). */
+#endif
+
+#define BPP 16 /* Bits per pixel. */
+#define BYPP ((BPP+7)/8) /* Bytes per pixel. */
+
+
+/**
+ * @brief Initialize the Himax LCD with HX8347-D LCD Controller.
+ */
+void GLCD_Initialize(void);
+
+/**
+ * @brief Set draw window region to whole screen.
+ */
+void GLCD_WindowMax(void);
+
+/**
+ * @brief Set draw window region.
+ * @param[in] x Horizontal position.
+ * @param[in] y Vertical position.
+ * @param[in] w Window width in pixel.
+ * @param[in] h Window height in pixels.
+ */
+void GLCD_SetWindow(unsigned int x, unsigned int y,
+ unsigned int w, unsigned int h);
+
+/**
+ * @brief Set foreground color.
+ * @param[in] color Foreground color.
+ */
+void GLCD_SetTextColor(unsigned short color);
+
+/**
+ * @brief Set background color.
+ * @param[in] color Background color.
+ */
+void GLCD_SetBackColor(unsigned short color);
+
+/**
+ * @brief Clear display.
+ * @param[in] color Display clearing color.
+ *
+ */
+void GLCD_Clear(unsigned short color);
+
+/**
+ * @brief Draw character on given position.
+ * @param[in] x Horizontal position.
+ * @param[in] y Vertical position.
+ * @param[in] cw Character width in pixel.
+ * @param[in] ch Character height in pixels.
+ * @param[in] c Pointer to character bitmap.
+ *
+ */
+void GLCD_DrawChar(unsigned int x, unsigned int y,
+ unsigned int cw, unsigned int ch,
+ unsigned char *c);
+
+/**
+ * @brief Display character on given line.
+ * @param[in] ln Line number.
+ * @param[in] col Column number.
+ * @param[in] fi Font index (0 = 9x15).
+ * @param[in] c ASCII character.
+ */
+void GLCD_DisplayChar(unsigned int ln, unsigned int col,
+ unsigned char fi, unsigned char c);
+
+
+/**
+ * @brief Display string on given line.
+ * @param[in] ln Line number.
+ * @param[in] col Column number.
+ * @param[in] fi Font index (0 = 9x15).
+ * @param[in] s Pointer to string.
+ */
+void GLCD_DisplayString(unsigned int ln, unsigned int col,
+ unsigned char fi, char *s);
+
+/**
+ * @brief Clear given line.
+ * @param[in] ln: Line number.
+ * @param[in] fi Font index (0 = 9x15).
+ */
+void GLCD_ClearLn(unsigned int ln, unsigned char fi);
+
+/**
+ * @brief Display graphical bitmap image at position x horizontally and y
+ * vertically. This function is optimized for 16 bits per pixel
+ * format, it has to be adapted for any other format.
+ * @param[in] x Horizontal position.
+ * @param[in] y Vertical position.
+ * @param[in] w Width of bitmap.
+ * @param[in] h Height of bitmap.
+ * @param[in] bitmap Address at which the bitmap data resides.
+ */
+void GLCD_Bitmap(unsigned int x, unsigned int y,
+ unsigned int w, unsigned int h,
+ unsigned short *bitmap);
+
+/**
+ * @brief Displays an 8 bit image, conversion to the LCD's
+ * 16 bit codec is done on the fly.
+ * @param[in] data Pointer to the full sized image data.
+ * @param[in] width Image width.
+ * @param[in] height Image height.
+ * @param[in] channels Number of channels in the image.
+ * @param[in] pos_x Start x position for the LCD.
+ * @param[in] pos_y Start y position for the LCD.
+ * @param[in] downsample_factor Factor by which the image
+ * is downsampled by.
+ */
+void GLCD_Image(const void *data, const uint32_t width,
+ const uint32_t height, const uint32_t channels,
+ const uint32_t pos_x, const uint32_t pos_y,
+ const uint32_t downsample_factor);
+
+/**
+ * @brief Draw box filled with color.
+ * @param[in] x Horizontal position.
+ * @param[in] y Vertical position.
+ * @param[in] w Window width in pixels.
+ * @param[in] h Window height in pixels.
+ * @param[in] color Box color.
+ */
+void GLCD_Box(unsigned int x, unsigned int y,
+ unsigned int w, unsigned int h,
+ unsigned short color);
+
+#endif /* GLCD_H */
diff --git a/source/hal/source/components/lcd/source/glcd_mps3/font_9x15_h.h b/source/hal/source/components/lcd/source/glcd_mps3/font_9x15_h.h
new file mode 100644
index 0000000..bbfb930
--- /dev/null
+++ b/source/hal/source/components/lcd/source/glcd_mps3/font_9x15_h.h
@@ -0,0 +1,128 @@
+/*
+ * Copyright (c) 2021 Arm Limited. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+//Font Generated by MikroElektronika GLCD Font Creator 1.2.0.0
+//MikroElektrnika 2011
+//http://www.mikroe.com
+
+//GLCD FontName : Lucida_Console9x15
+//GLCD FontSize : 9x15
+
+#ifndef FONT_9x15_H_H
+#define FONT_9x15_H_H
+
+const unsigned short Font_9x15_h[] = {
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* Code for char num 32. */
+ 0x00,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x00,0x10,0x10,0x00,0x00,0x00, /* Code for char num 33. */
+ 0x44,0x44,0x44,0x44,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* Code for char num 34. */
+ 0x00,0x12,0x12,0x24,0x7F,0x24,0x28,0x48,0xFE,0x48,0x90,0x90,0x00,0x00,0x00, /* Code for char num 35. */
+ 0x10,0x7C,0x16,0x12,0x12,0x1C,0x38,0x70,0x50,0x50,0x52,0x3E,0x10,0x00,0x00, /* Code for char num 36. */
+ 0x00,0x8C,0x92,0x52,0x52,0x2C,0x10,0x08,0x68,0x94,0x92,0x92,0x62,0x00,0x00, /* Code for char num 37. */
+ 0x00,0x18,0x24,0x24,0x34,0x18,0x0C,0x12,0xB2,0xE2,0xC2,0xBC,0x00,0x00,0x00, /* Code for char num 38. */
+ 0x08,0x08,0x08,0x08,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* Code for char num 39. */
+ 0xC0,0x60,0x10,0x10,0x08,0x08,0x08,0x08,0x08,0x08,0x10,0x10,0x60,0xC0,0x00, /* Code for char num 40. */
+ 0x0C,0x18,0x20,0x20,0x40,0x40,0x40,0x40,0x40,0x40,0x20,0x20,0x18,0x0C,0x00, /* Code for char num 41. */
+ 0x00,0x10,0x92,0xEE,0x18,0x28,0x28,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* Code for char num 42. */
+ 0x00,0x00,0x00,0x00,0x10,0x10,0x10,0x10,0xFE,0x10,0x10,0x10,0x00,0x00,0x00, /* Code for char num 43. */
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x18,0x18,0x10,0x08,0x00, /* Code for char num 44. */
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x7C,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* Code for char num 45. */
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x18,0x18,0x00,0x00,0x00, /* Code for char num 46. */
+ 0x80,0x40,0x40,0x60,0x20,0x20,0x10,0x10,0x08,0x08,0x0C,0x04,0x04,0x02,0x00, /* Code for char num 47. */
+ 0x00,0x38,0x44,0x82,0x82,0x82,0x82,0x82,0x82,0x82,0x44,0x38,0x00,0x00,0x00, /* Code for char num 48. */
+ 0x00,0x10,0x1E,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0xFE,0x00,0x00,0x00, /* Code for char num 49. */
+ 0x00,0x3E,0x42,0x40,0x40,0x40,0x20,0x10,0x08,0x04,0x02,0x7E,0x00,0x00,0x00, /* Code for char num 50. */
+ 0x00,0x3C,0x40,0x40,0x40,0x60,0x38,0x40,0x40,0x40,0x40,0x3C,0x00,0x00,0x00, /* Code for char num 51. */
+ 0x00,0x20,0x30,0x28,0x24,0x24,0x22,0x21,0x7F,0x20,0x20,0x20,0x00,0x00,0x00, /* Code for char num 52. */
+ 0x00,0x7C,0x04,0x04,0x04,0x1C,0x20,0x40,0x40,0x40,0x20,0x3C,0x00,0x00,0x00, /* Code for char num 53. */
+ 0x00,0x78,0x04,0x04,0x02,0x3A,0x46,0x82,0x82,0x82,0x44,0x38,0x00,0x00,0x00, /* Code for char num 54. */
+ 0x00,0xFE,0x80,0x40,0x20,0x20,0x10,0x10,0x08,0x08,0x04,0x04,0x00,0x00,0x00, /* Code for char num 55. */
+ 0x00,0x3C,0x42,0x42,0x42,0x24,0x1C,0x62,0x42,0x42,0x42,0x3C,0x00,0x00,0x00, /* Code for char num 56. */
+ 0x00,0x38,0x44,0x82,0x82,0x82,0xC4,0xB8,0x80,0x40,0x40,0x3C,0x00,0x00,0x00, /* Code for char num 57. */
+ 0x00,0x00,0x00,0x00,0x18,0x18,0x00,0x00,0x00,0x00,0x18,0x18,0x00,0x00,0x00, /* Code for char num 58. */
+ 0x00,0x00,0x00,0x00,0x18,0x18,0x00,0x00,0x00,0x00,0x18,0x18,0x10,0x08,0x00, /* Code for char num 59. */
+ 0x00,0x00,0x00,0x00,0x80,0x60,0x10,0x0C,0x0C,0x10,0x60,0x80,0x00,0x00,0x00, /* Code for char num 60. */
+ 0x00,0x00,0x00,0x00,0x00,0x00,0xFE,0x00,0x00,0xFE,0x00,0x00,0x00,0x00,0x00, /* Code for char num 61. */
+ 0x00,0x00,0x00,0x00,0x02,0x0C,0x10,0x60,0x60,0x10,0x0C,0x02,0x00,0x00,0x00, /* Code for char num 62. */
+ 0x00,0x3E,0x42,0x42,0x40,0x20,0x10,0x08,0x08,0x00,0x08,0x08,0x00,0x00,0x00, /* Code for char num 63. */
+ 0x00,0x78,0x84,0xE2,0x92,0x8A,0x8A,0xCA,0xCA,0xB2,0xA6,0x3C,0x00,0x00,0x00, /* Code for char num 64. */
+ 0x00,0x00,0x10,0x38,0x28,0x28,0x44,0x44,0xFE,0x82,0x82,0x82,0x00,0x00,0x00, /* Code for char num 65. */
+ 0x00,0x00,0x3E,0x42,0x42,0x22,0x1E,0x22,0x42,0x42,0x42,0x3E,0x00,0x00,0x00, /* Code for char num 66. */
+ 0x00,0x00,0xF8,0x06,0x02,0x01,0x01,0x01,0x01,0x02,0x06,0xF8,0x00,0x00,0x00, /* Code for char num 67. */
+ 0x00,0x00,0x3E,0x42,0x82,0x82,0x82,0x82,0x82,0x82,0x42,0x3E,0x00,0x00,0x00, /* Code for char num 68. */
+ 0x00,0x00,0xFE,0x02,0x02,0x02,0x02,0x7E,0x02,0x02,0x02,0xFE,0x00,0x00,0x00, /* Code for char num 69. */
+ 0x00,0x00,0xFE,0x02,0x02,0x02,0x02,0x7E,0x02,0x02,0x02,0x02,0x00,0x00,0x00, /* Code for char num 70. */
+ 0x00,0x00,0xF8,0x06,0x02,0x01,0x01,0xE1,0x81,0x82,0x86,0xF8,0x00,0x00,0x00, /* Code for char num 71. */
+ 0x00,0x00,0x42,0x42,0x42,0x42,0x42,0x7E,0x42,0x42,0x42,0x42,0x00,0x00,0x00, /* Code for char num 72. */
+ 0x00,0x00,0xFE,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0xFE,0x00,0x00,0x00, /* Code for char num 73. */
+ 0x00,0x00,0x3C,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x1E,0x00,0x00,0x00, /* Code for char num 74. */
+ 0x00,0x00,0x42,0x22,0x12,0x0A,0x06,0x0A,0x12,0x22,0x42,0x82,0x00,0x00,0x00, /* Code for char num 75. */
+ 0x00,0x00,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0xFE,0x00,0x00,0x00, /* Code for char num 76. */
+ 0x00,0x00,0x63,0x63,0x63,0x55,0x55,0x55,0x4D,0x49,0x41,0x41,0x00,0x00,0x00, /* Code for char num 77. */
+ 0x00,0x00,0x82,0x86,0x8A,0x8A,0x92,0x92,0xA2,0xA2,0xC2,0x82,0x00,0x00,0x00, /* Code for char num 78. */
+ 0x00,0x00,0x3C,0x42,0x81,0x81,0x81,0x81,0x81,0x81,0x42,0x3C,0x00,0x00,0x00, /* Code for char num 79. */
+ 0x00,0x00,0x3E,0x42,0x42,0x42,0x62,0x1E,0x02,0x02,0x02,0x02,0x00,0x00,0x00, /* Code for char num 80. */
+ 0x00,0x00,0x3C,0x42,0x81,0x81,0x81,0x81,0x81,0x81,0x42,0x3C,0x60,0x80,0x00, /* Code for char num 81. */
+ 0x00,0x00,0x3E,0x42,0x42,0x42,0x22,0x1E,0x12,0x22,0x42,0x82,0x00,0x00,0x00, /* Code for char num 82. */
+ 0x00,0x00,0x7C,0x42,0x02,0x06,0x1C,0x20,0x40,0x40,0x42,0x3E,0x00,0x00,0x00, /* Code for char num 83. */
+ 0x00,0x00,0xFE,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x00,0x00,0x00, /* Code for char num 84. */
+ 0x00,0x00,0x82,0x82,0x82,0x82,0x82,0x82,0x82,0x82,0x44,0x3C,0x00,0x00,0x00, /* Code for char num 85. */
+ 0x00,0x00,0x82,0x82,0x82,0x82,0x44,0x44,0x28,0x28,0x38,0x10,0x00,0x00,0x00, /* Code for char num 86. */
+ 0x00,0x00,0x82,0x82,0x92,0x92,0xAA,0xAA,0xAA,0xAA,0x64,0x44,0x00,0x00,0x00, /* Code for char num 87. */
+ 0x00,0x00,0x82,0x82,0x44,0x28,0x10,0x10,0x28,0x44,0x82,0x82,0x00,0x00,0x00, /* Code for char num 88. */
+ 0x00,0x00,0x82,0x82,0x44,0x44,0x28,0x10,0x10,0x10,0x10,0x10,0x00,0x00,0x00, /* Code for char num 89. */
+ 0x00,0x00,0xFF,0x80,0x40,0x20,0x10,0x08,0x04,0x02,0x01,0xFF,0x00,0x00,0x00, /* Code for char num 90. */
+ 0xF8,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0xF8,0x00, /* Code for char num 91. */
+ 0x02,0x04,0x04,0x04,0x08,0x08,0x10,0x10,0x20,0x20,0x20,0x40,0x40,0x80,0x00, /* Code for char num 92. */
+ 0x3E,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x3E,0x00, /* Code for char num 93. */
+ 0x00,0x10,0x10,0x10,0x28,0x28,0x44,0x44,0x44,0x82,0x00,0x00,0x00,0x00,0x00, /* Code for char num 94. */
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFE,0x00,0x00, /* Code for char num 95. */
+ 0x10,0x20,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* Code for char num 96. */
+ 0x00,0x00,0x00,0x00,0x3C,0x40,0x40,0x78,0x44,0x42,0x62,0xDC,0x00,0x00,0x00, /* Code for char num 97. */
+ 0x02,0x02,0x02,0x02,0x7A,0x46,0x82,0x82,0x82,0x82,0x46,0x3A,0x00,0x00,0x00, /* Code for char num 98. */
+ 0x00,0x00,0x00,0x00,0xF8,0x04,0x02,0x02,0x02,0x02,0x04,0xF8,0x00,0x00,0x00, /* Code for char num 99. */
+ 0x80,0x80,0x80,0x80,0xB8,0xC4,0x82,0x82,0x82,0x82,0xC4,0xBC,0x00,0x00,0x00, /* Code for char num 100. */
+ 0x00,0x00,0x00,0x00,0x38,0x44,0x42,0x7E,0x02,0x02,0x04,0x78,0x00,0x00,0x00, /* Code for char num 101. */
+ 0xF0,0x08,0x08,0x08,0xFE,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x00,0x00,0x00, /* Code for char num 102. */
+ 0x00,0x00,0x00,0x00,0xB8,0xC4,0x82,0x82,0x82,0x82,0xC4,0xBC,0x80,0x40,0x3C, /* Code for char num 103. */
+ 0x02,0x02,0x02,0x02,0x3A,0x46,0x42,0x42,0x42,0x42,0x42,0x42,0x00,0x00,0x00, /* Code for char num 104. */
+ 0x18,0x18,0x00,0x00,0x1E,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x00,0x00,0x00, /* Code for char num 105. */
+ 0x30,0x30,0x00,0x00,0x3C,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x1E, /* Code for char num 106. */
+ 0x02,0x02,0x02,0x02,0x42,0x22,0x12,0x0E,0x0A,0x12,0x22,0x42,0x00,0x00,0x00, /* Code for char num 107. */
+ 0x1E,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x00,0x00,0x00, /* Code for char num 108. */
+ 0x00,0x00,0x00,0x00,0xDA,0xB6,0x92,0x92,0x92,0x92,0x92,0x92,0x00,0x00,0x00, /* Code for char num 109. */
+ 0x00,0x00,0x00,0x00,0x3A,0x46,0x42,0x42,0x42,0x42,0x42,0x42,0x00,0x00,0x00, /* Code for char num 110. */
+ 0x00,0x00,0x00,0x00,0x38,0x44,0x82,0x82,0x82,0x82,0x44,0x38,0x00,0x00,0x00, /* Code for char num 111. */
+ 0x00,0x00,0x00,0x00,0x7A,0x46,0x82,0x82,0x82,0x82,0x46,0x3A,0x02,0x02,0x02, /* Code for char num 112. */
+ 0x00,0x00,0x00,0x00,0xB8,0xC4,0x82,0x82,0x82,0x82,0xC4,0xBC,0x80,0x80,0x80, /* Code for char num 113. */
+ 0x00,0x00,0x00,0x00,0xF4,0x8C,0x04,0x04,0x04,0x04,0x04,0x04,0x00,0x00,0x00, /* Code for char num 114. */
+ 0x00,0x00,0x00,0x00,0x7C,0x02,0x02,0x0C,0x30,0x40,0x42,0x3E,0x00,0x00,0x00, /* Code for char num 115. */
+ 0x00,0x00,0x08,0x08,0xFE,0x08,0x08,0x08,0x08,0x08,0x08,0xF0,0x00,0x00,0x00, /* Code for char num 116. */
+ 0x00,0x00,0x00,0x00,0x42,0x42,0x42,0x42,0x42,0x42,0x62,0x5C,0x00,0x00,0x00, /* Code for char num 117. */
+ 0x00,0x00,0x00,0x00,0x82,0x82,0x82,0x44,0x44,0x28,0x28,0x10,0x00,0x00,0x00, /* Code for char num 118. */
+ 0x00,0x00,0x00,0x00,0x82,0x92,0xAA,0xAA,0xAA,0xAA,0x44,0x44,0x00,0x00,0x00, /* Code for char num 119. */
+ 0x00,0x00,0x00,0x00,0x82,0x44,0x28,0x10,0x10,0x28,0x44,0x82,0x00,0x00,0x00, /* Code for char num 120. */
+ 0x00,0x00,0x00,0x00,0x82,0x82,0x82,0x44,0x44,0x28,0x28,0x10,0x10,0x0C,0x00, /* Code for char num 121. */
+ 0x00,0x00,0x00,0x00,0xFE,0x80,0x40,0x20,0x10,0x08,0x04,0xFE,0x00,0x00,0x00, /* Code for char num 122. */
+ 0xE0,0x10,0x10,0x10,0x10,0x10,0x10,0x0C,0x10,0x10,0x10,0x10,0x10,0xE0,0x00, /* Code for char num 123. */
+ 0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x00, /* Code for char num 124. */
+ 0x0E,0x10,0x10,0x10,0x10,0x10,0x10,0x60,0x10,0x10,0x10,0x10,0x10,0x0E,0x00, /* Code for char num 125. */
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x62,0x92,0x8C,0x00,0x00,0x00,0x00,0x00,0x00, /* Code for char num 126. */
+ 0x00,0x00,0x00,0x07,0x05,0x05,0x05,0x05,0x05,0x05,0x07,0x00,0x00,0x00,0x00 /* Code for char num 127. */
+};
+
+
+#endif /* FONT_9x15_H_H */
diff --git a/source/hal/source/components/lcd/source/glcd_mps3/glcd_mps3.c b/source/hal/source/components/lcd/source/glcd_mps3/glcd_mps3.c
new file mode 100644
index 0000000..c67483e
--- /dev/null
+++ b/source/hal/source/components/lcd/source/glcd_mps3/glcd_mps3.c
@@ -0,0 +1,474 @@
+/*
+ * Copyright (c) 2022 Arm Limited. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "glcd.h"
+
+#include "log_macros.h"
+#include "font_9x15_h.h"
+
+#define CLCD_CS_Pos 0
+#define CLCD_CS_Msk (1UL<<CLCD_CS_Pos)
+#define SHIELD_0_nCS_Pos 1
+#define SHIELD_0_nCS_Msk (1UL<<SHIELD_0_nCS_Pos)
+#define SHIELD_1_nCS_Pos 2
+#define SHIELD_1_nCS_Msk (1UL<<SHIELD_1_nCS_Pos)
+#define CLCD_RESET_Pos 3
+#define CLCD_RESET_Msk (1UL<<CLCD_RESET_Pos)
+#define CLCD_RS_Pos 4
+#define CLCD_RS_Msk (1UL<<CLCD_RS_Pos)
+#define CLCD_RD_Pos 5
+#define CLCD_RD_Msk (1UL<<CLCD_RD_Pos)
+#define CLCD_BL_Pos 6
+#define CLCD_BL_Msk (1UL<<CLCD_BL_Pos)
+
+/*-------------- CLCD Controller Internal Register addresses ----------------*/
+#define CHAR_COM ((volatile unsigned int *)(CLCD_CONFIG_BASE + 0x000))
+#define CHAR_DAT ((volatile unsigned int *)(CLCD_CONFIG_BASE + 0x004))
+#define CHAR_RD ((volatile unsigned int *)(CLCD_CONFIG_BASE + 0x008))
+#define CHAR_RAW ((volatile unsigned int *)(CLCD_CONFIG_BASE + 0x00C))
+#define CHAR_MASK ((volatile unsigned int *)(CLCD_CONFIG_BASE + 0x010))
+#define CHAR_STAT ((volatile unsigned int *)(CLCD_CONFIG_BASE + 0x014))
+#define CHAR_MISC ((volatile unsigned int *)(CLCD_CONFIG_BASE + 0x04C))
+
+/*--------------- Graphic LCD interface hardware definitions -----------------*/
+/* Pin CS setting to 0 or 1 */
+#define LCD_CS(x) ((x) ? (*CHAR_MISC |= CLCD_CS_Msk) : (*CHAR_MISC &= ~CLCD_CS_Msk))
+#define LCD_RST(x) ((x) ? (*CHAR_MISC |= CLCD_RESET_Msk) : (*CHAR_MISC &= ~CLCD_RESET_Msk))
+#define LCD_BL(x) ((x) ? (*CHAR_MISC |= CLCD_BL_Msk) : (*CHAR_MISC &= ~CLCD_BL_Msk))
+
+#define BG_COLOR 0 /* Background colour */
+#define TXT_COLOR 1 /* Text colour */
+
+/**
+* Text and background colour
+*/
+static volatile unsigned short Color[2] = {Black, White};
+
+/**
+ * @brief Delay in while loop cycles.
+ * @param[in] cnt Number of while cycles to delay.
+ **/
+static void delay (int cnt)
+{
+ cnt <<= DELAY_2N;
+ while (cnt != 0) {
+ --cnt;
+ }
+}
+
+/**
+ * @brief Write a command the LCD controller.
+ * @param[in] cmd Command to be written.
+ */
+static __inline void wr_cmd(unsigned char cmd)
+{
+ LCD_CS(0);
+ *CHAR_COM = cmd;
+ LCD_CS(1);
+}
+
+/**
+ * @brief Start of data writing to the LCD controller.
+ */
+static __inline void wr_dat_start (void)
+{
+ LCD_CS(0);
+}
+
+/**
+ * @brief Stop of data writing to the LCD controller.
+ */
+static __inline void wr_dat_stop (void)
+{
+ LCD_CS(1);
+}
+
+/**
+ * @brief Data writing to the LCD controller.
+ * @param[in] dat Data to be written.
+ */
+static __inline void wr_dat_only(unsigned short dat)
+{
+ *CHAR_DAT = (dat >> 8); /* Write D8..D15 */
+ *CHAR_DAT = (dat & 0xFF); /* Write D0..D7 */
+}
+
+/**
+ * @brief Write a value to the to LCD register.
+ * @param[in] reg Register to be written.
+ * @param[in] val Value to write to the register.
+ */
+static __inline void wr_reg(unsigned char reg, unsigned short val)
+{
+ LCD_CS(0);
+ *CHAR_COM = reg;
+ wr_dat_only(val);
+ LCD_CS(1);
+}
+
+/**
+ * @brief Converts a gray value to RGB565 representation.
+ * @param[in] src_uchar Pointer to the source pixel.
+ * @return 16 bit RGB565 value.
+ */
+static inline uint16_t _GLCD_Gray8_to_RGB565(uint8_t *src_uchar)
+{
+ uint16_t val_r = (*src_uchar >> 3);
+ uint16_t val_g = (*src_uchar >> 2);
+ return ((val_r << 11) | (val_g << 5) | val_r);
+}
+
+/**
+ * @brief Converts an RGB888 value to RGB565 representation.
+ * @param[in] src_uchar Pointer to the source pixel for R (assumed to
+ * be RGB format).
+ * @return 16 bit RGB565 value.
+ */
+static inline uint16_t _GLCD_RGB888_to_RGB565(uint8_t *src_uchar)
+{
+ uint16_t val_r = (*src_uchar >> 3) & 0x1F;
+ uint16_t val_g = (*(src_uchar+1) >> 2) & 0x3F;
+ uint16_t val_b = (*(src_uchar+2) >> 3) & 0x1F;
+ return ((val_r << 11) | (val_g << 5) | val_b);
+}
+
+/* Helper typedef to encapsulate the colour conversion function
+ * signatures */
+typedef uint16_t (* std_clr_2_lcd_clr_fn)(uint8_t *src_uchar);
+
+void GLCD_SetWindow(unsigned int x, unsigned int y, unsigned int w, unsigned int h) {
+ unsigned int xe, ye;
+
+ xe = x+w-1;
+ ye = y+h-1;
+
+ wr_reg(0x02, x >> 8); /* Column address start MSB */
+ wr_reg(0x03, x & 0xFF); /* Column address start LSB */
+ wr_reg(0x04, xe >> 8); /* Column address end MSB */
+ wr_reg(0x05, xe & 0xFF); /* Column address end LSB */
+
+ wr_reg(0x06, y >> 8); /* Row address start MSB */
+ wr_reg(0x07, y & 0xFF); /* Row address start LSB */
+ wr_reg(0x08, ye >> 8); /* Row address end MSB */
+ wr_reg(0x09, ye & 0xFF); /* Row address end LSB */
+}
+
+void GLCD_WindowMax(void)
+{
+ GLCD_SetWindow (0, 0, GLCD_WIDTH, GLCD_HEIGHT);
+}
+
+void GLCD_SetTextColor(unsigned short color)
+{
+ Color[TXT_COLOR] = color;
+}
+
+void GLCD_SetBackColor(unsigned short color)
+{
+ Color[BG_COLOR] = color;
+}
+
+void GLCD_Clear(unsigned short color)
+{
+ unsigned int i;
+
+ GLCD_WindowMax();
+ wr_cmd(0x22);
+ wr_dat_start();
+
+ for(i = 0; i < (GLCD_WIDTH*GLCD_HEIGHT); ++i) {
+ wr_dat_only(color);
+ }
+ wr_dat_stop();
+}
+
+
+void GLCD_DrawChar(
+ unsigned int x, unsigned int y,
+ unsigned int cw, unsigned int ch,
+ unsigned char *c)
+{
+ unsigned int i, j, k, pixs;
+
+ /* Sanity check: out of bounds? */
+ if ((x + cw) > GLCD_WIDTH || (y + ch) > GLCD_HEIGHT) {
+ return;
+ }
+
+ GLCD_SetWindow(x, y, cw, ch);
+
+ wr_cmd(0x22);
+ wr_dat_start();
+
+ k = (cw + 7)/8;
+
+ if (k == 1) {
+ for (j = 0; j < ch; ++j) {
+ pixs = *(unsigned char *)c;
+ c += 1;
+
+ for (i = 0; i < cw; ++i) {
+ wr_dat_only (Color[(pixs >> i) & 1]);
+ }
+ }
+ }
+ else if (k == 2) {
+ for (j = 0; j < ch; ++j) {
+ pixs = *(unsigned short *)c;
+ c += 2;
+
+ for (i = 0; i < cw; ++i) {
+ wr_dat_only (Color[(pixs >> i) & 1]);
+ }
+ }
+ }
+ wr_dat_stop();
+}
+
+void GLCD_DisplayChar(
+ unsigned int ln, unsigned int col,
+ unsigned char fi, unsigned char c)
+{
+ c -= 32;
+ switch (fi) {
+ case 0: /* Font 9 x 15. */
+ GLCD_DrawChar(col * 9, ln * 15, 9, 15,
+ (unsigned char *)&Font_9x15_h[c * 15]);
+ break;
+ }
+}
+
+void GLCD_DisplayString(
+ unsigned int ln, unsigned int col,
+ unsigned char fi, char *s)
+{
+ while (*s) {
+ GLCD_DisplayChar(ln, col++, fi, *s++);
+ }
+}
+
+
+
+void GLCD_ClearLn(unsigned int ln, unsigned char fi)
+{
+ unsigned char i;
+ char buf[60];
+
+ GLCD_WindowMax();
+ switch (fi) {
+ case 0: /* Font 9x15*/
+ for (i = 0; i < (GLCD_WIDTH+8)/9; ++i) {
+ buf[i] = ' ';
+ }
+ buf[i+1] = 0;
+ break;
+ }
+ GLCD_DisplayString (ln, 0, fi, buf);
+}
+
+void GLCD_Bitmap(unsigned int x, unsigned int y,
+ unsigned int w, unsigned int h,
+ unsigned short *bitmap)
+{
+ unsigned int i;
+ unsigned short *bitmap_ptr = bitmap;
+
+ GLCD_SetWindow (x, y, w, h);
+
+ wr_cmd(0x22);
+ wr_dat_start();
+
+ for (i = 0; i < (w*h); ++i) {
+ wr_dat_only (bitmap_ptr[i]);
+ }
+ wr_dat_stop();
+}
+
+void GLCD_Image(const void *data, const uint32_t width,
+ const uint32_t height, const uint32_t channels,
+ const uint32_t pos_x, const uint32_t pos_y,
+ const uint32_t downsample_factor)
+{
+ uint32_t i, j = 0; /* for loops */
+ const uint32_t x_incr = channels * downsample_factor; /* stride. */
+ const uint32_t y_incr = channels * width * (downsample_factor - 1); /* skip rows. */
+ uint8_t* src_unsigned = (uint8_t *)data; /* temporary pointer. */
+ std_clr_2_lcd_clr_fn cvt_clr_fn = 0; /* colour conversion function. */
+
+ /* Based on number of channels, we decide which of the above functions to use. */
+ switch (channels) {
+ case 1:
+ cvt_clr_fn = _GLCD_Gray8_to_RGB565;
+ break;
+
+ case 3:
+ cvt_clr_fn = _GLCD_RGB888_to_RGB565;
+ break;
+
+ default:
+ printf_err("number of channels not supported by display\n");
+ return;
+ }
+
+ /* Set the window position expected. Note: this is integer div. */
+ GLCD_SetWindow(pos_x, pos_y,
+ width/downsample_factor, height/downsample_factor);
+ wr_cmd(0x22);
+ wr_dat_start();
+
+ /* Loop over the image. */
+ for (j = height; j != 0; j -= downsample_factor) {
+ for (i = width; i != 0; i -= downsample_factor) {
+ wr_dat_only(cvt_clr_fn(src_unsigned));
+ src_unsigned += x_incr;
+ }
+
+ /* Skip rows if needed. */
+ src_unsigned += y_incr;
+ }
+
+ wr_dat_stop();
+}
+
+void GLCD_Box(
+ unsigned int x, unsigned int y,
+ unsigned int w, unsigned int h,
+ unsigned short color)
+{
+ unsigned int i;
+
+ GLCD_SetWindow (x, y, w, h);
+
+ wr_cmd(0x22);
+ wr_dat_start();
+ for(i = 0; i < (w*h); ++i){
+ wr_dat_only (color);
+ }
+ wr_dat_stop();
+}
+
+
+void GLCD_Initialize (void)
+{
+ /* CLCD screen setup (Default CLCD screen interface state) ------------- */
+ LCD_CS(1); /* deassert nCS0. */
+ LCD_RST(1); /* deassert Reset. */
+ LCD_BL(0); /* switch off backlight. */
+
+ /* Reset CLCD screen --------------------------------------------------- */
+ LCD_RST(0); /* assert Reset. */
+ delay(1);
+ LCD_RST(1); /* deassert Reset. */
+ delay(10);
+
+ /* Driving ability settings ----------------------------------------------*/
+ wr_reg(0xEA, 0x00); /* Power control internal used (1). */
+ wr_reg(0xEB, 0x20); /* Power control internal used (2). */
+ wr_reg(0xEC, 0x0C); /* Source control internal used (1). */
+ wr_reg(0xED, 0xC7); /* Source control internal used (2). */
+ wr_reg(0xE8, 0x38); /* Source output period Normal mode. */
+ wr_reg(0xE9, 0x10); /* Source output period Idle mode. */
+ wr_reg(0xF1, 0x01); /* RGB 18-bit interface ;0x0110. */
+ wr_reg(0xF2, 0x10);
+
+ /* Adjust the Gamma Curve ------------------------------------------------*/
+ wr_reg(0x40, 0x01);
+ wr_reg(0x41, 0x00);
+ wr_reg(0x42, 0x00);
+ wr_reg(0x43, 0x10);
+ wr_reg(0x44, 0x0E);
+ wr_reg(0x45, 0x24);
+ wr_reg(0x46, 0x04);
+ wr_reg(0x47, 0x50);
+ wr_reg(0x48, 0x02);
+ wr_reg(0x49, 0x13);
+ wr_reg(0x4A, 0x19);
+ wr_reg(0x4B, 0x19);
+ wr_reg(0x4C, 0x16);
+
+ wr_reg(0x50, 0x1B);
+ wr_reg(0x51, 0x31);
+ wr_reg(0x52, 0x2F);
+ wr_reg(0x53, 0x3F);
+ wr_reg(0x54, 0x3F);
+ wr_reg(0x55, 0x3E);
+ wr_reg(0x56, 0x2F);
+ wr_reg(0x57, 0x7B);
+ wr_reg(0x58, 0x09);
+ wr_reg(0x59, 0x06);
+ wr_reg(0x5A, 0x06);
+ wr_reg(0x5B, 0x0C);
+ wr_reg(0x5C, 0x1D);
+ wr_reg(0x5D, 0xCC);
+
+ /* Power voltage setting -------------------------------------------------*/
+ wr_reg(0x1B, 0x1B);
+ wr_reg(0x1A, 0x01);
+ wr_reg(0x24, 0x2F);
+ wr_reg(0x25, 0x57);
+ wr_reg(0x23, 0x88);
+
+ /* Power on setting ------------------------------------------------------*/
+ wr_reg(0x18, 0x36); /* Internal oscillator frequency adj. */
+ wr_reg(0x19, 0x01); /* Enable internal oscillator. */
+ wr_reg(0x01, 0x00); /* Normal mode, no scroll. */
+ wr_reg(0x1F, 0x88); /* Power control 6 - DDVDH Off. */
+ delay(20);
+ wr_reg(0x1F, 0x82); /* Power control 6 - Step-up: 3 x VCI. */
+ delay(5);
+ wr_reg(0x1F, 0x92); /* Power control 6 - Step-up: On. */
+ delay(5);
+ wr_reg(0x1F, 0xD2); /* Power control 6 - VCOML active. */
+ delay(5);
+
+ /* Color selection -------------------------------------------------------*/
+ wr_reg(0x17, 0x55); /* RGB, System interface: 16 Bit/Pixel. */
+ wr_reg(0x00, 0x00); /* Scrolling off, no standby. */
+
+ /* Interface config ------------------------------------------------------*/
+ wr_reg(0x2F, 0x11); /* LCD Drive: 1-line inversion. */
+ wr_reg(0x31, 0x00);
+ wr_reg(0x32, 0x00); /* DPL=0, HSPL=0, VSPL=0, EPL=0. */
+
+ /* Display on setting ----------------------------------------------------*/
+ wr_reg(0x28, 0x38); /* PT(0,0) active, VGL/VGL. */
+ delay(20);
+ wr_reg(0x28, 0x3C); /* Display active, VGL/VGL. */
+
+#if (LANDSCAPE == 1)
+#if (ROTATE180 == 0)
+ wr_reg (0x16, 0xA8);
+#else /* (ROTATE180 == 0) */
+ wr_reg (0x16, 0x68);
+#endif /* (ROTATE180 == 0) */
+#else /* (LANDSCAPE == 1) */
+#if (ROTATE180 == 0)
+ wr_reg (0x16, 0x08);
+#else /* (ROTATE180 == 0) */
+ wr_reg (0x16, 0xC8);
+#endif /* (ROTATE180 == 0) */
+#endif /* (LANDSCAPE == 1) */
+
+ /* Display scrolling settings --------------------------------------------*/
+ wr_reg(0x0E, 0x00); /* TFA MSB */
+ wr_reg(0x0F, 0x00); /* TFA LSB */
+ wr_reg(0x10, 320 >> 8); /* VSA MSB */
+ wr_reg(0x11, 320 & 0xFF); /* VSA LSB */
+ wr_reg(0x12, 0x00); /* BFA MSB */
+ wr_reg(0x13, 0x00); /* BFA LSB */
+
+ LCD_BL(1); /* turn on backlight */
+}
diff --git a/source/hal/source/components/lcd/source/glcd_stubs/glcd_stubs.c b/source/hal/source/components/lcd/source/glcd_stubs/glcd_stubs.c
new file mode 100644
index 0000000..5df1522
--- /dev/null
+++ b/source/hal/source/components/lcd/source/glcd_stubs/glcd_stubs.c
@@ -0,0 +1,90 @@
+/*
+ * Copyright (c) 2021-2022 Arm Limited. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "glcd.h"
+#include "log_macros.h"
+
+#include <inttypes.h>
+
+void GLCD_Initialize(void) {}
+
+void GLCD_Bitmap(unsigned int x, unsigned int y,
+ unsigned int w, unsigned int h, unsigned short *bitmap)
+{
+ UNUSED(x);
+ UNUSED(y);
+ UNUSED(w);
+ UNUSED(h);
+ UNUSED(bitmap);
+}
+
+void GLCD_Image(const void *data, const uint32_t width,
+ const uint32_t height, const uint32_t channels,
+ const uint32_t pos_x, const uint32_t pos_y,
+ const uint32_t downsample_factor)
+{
+ UNUSED(data);
+ UNUSED(pos_x);
+ UNUSED(pos_y);
+ UNUSED(width);
+ UNUSED(height);
+ UNUSED(channels);
+ UNUSED(downsample_factor);
+ debug("image display: (x, y, w, h) = "
+ "(%" PRIu32 ", %" PRIu32 ", %" PRIu32 ", %" PRIu32 ")\n",
+ pos_x, pos_y, width, height);
+ debug("image display: channels = %" PRIu32 ", downsample factor = %" PRIu32 "\n",
+ channels, downsample_factor);
+}
+
+void GLCD_Clear(unsigned short color)
+{
+ UNUSED(color);
+}
+
+void GLCD_SetTextColor(unsigned short color)
+{
+ UNUSED(color);
+}
+
+void GLCD_DisplayChar (unsigned int ln, unsigned int col, unsigned char fi,
+ unsigned char c)
+{
+ UNUSED(ln);
+ UNUSED(col);
+ UNUSED(fi);
+ UNUSED(c);
+}
+
+void GLCD_DisplayString(unsigned int ln, unsigned int col, unsigned char fi,
+ char *s)
+{
+ UNUSED(ln);
+ UNUSED(col);
+ UNUSED(fi);
+ UNUSED(s);
+ debug("text display: %s\n", s);
+}
+
+void GLCD_Box(unsigned int x, unsigned int y, unsigned int w, unsigned int h,
+ unsigned short color)
+{
+ UNUSED(x);
+ UNUSED(y);
+ UNUSED(w);
+ UNUSED(h);
+ UNUSED(color);
+}
diff --git a/source/hal/source/components/lcd/source/lcd_img.c b/source/hal/source/components/lcd/source/lcd_img.c
new file mode 100644
index 0000000..e3921a9
--- /dev/null
+++ b/source/hal/source/components/lcd/source/lcd_img.c
@@ -0,0 +1,160 @@
+/*
+ * Copyright (c) 2022 Arm Limited. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "lcd_img.h"
+
+#include "log_macros.h"
+#include "glcd.h"
+
+#include <string.h>
+#include <assert.h>
+
+static int show_title(void)
+{
+ char title[128];
+ int status = 0;
+
+ /* LCD title string */
+#if defined(CPU_CORTEX_M55)
+ const char* cpu_name = "Arm Cortex-M55";
+#else /* defined(CPU_CORTEX_M55) */
+ const char* cpu_name = "Arm CPU";
+#endif /* defined(CPU_CORTEX_M55) */
+
+ lcd_set_text_color(White);
+
+ /* First line */
+ snprintf(title, sizeof(title), "Arm ML embedded code samples");
+
+ if (0 != (status = lcd_display_text(
+ title, strlen(title), 10, 0, false))) {
+ return status;
+ }
+
+ /* Second line */
+#if defined (ARM_NPU)
+ snprintf(title, sizeof(title), "%s + Arm Ethos-U NPU", cpu_name);
+#else /* defined (ARM_NPU) */
+ snprintf(title, sizeof(title), "%s", cpu_name);
+#endif /* defined (ARM_NPU) */
+
+ return lcd_display_text(title, strlen(title), 10, 20, false);
+}
+
+int lcd_init(void)
+{
+ GLCD_Initialize();
+ GLCD_Clear(Black);
+ return show_title();
+}
+
+int lcd_display_image(const uint8_t* data, const uint32_t width,
+ const uint32_t height, const uint32_t channels,
+ const uint32_t pos_x, const uint32_t pos_y,
+ const uint32_t downsample_factor)
+{
+ /* Sanity checks */
+ assert(data);
+ if ((pos_x + width/downsample_factor > GLCD_WIDTH) ||
+ (pos_y + height/downsample_factor > GLCD_HEIGHT)) {
+ printf_err("Invalid image size for given location!\n");
+ return 1;
+ }
+
+ if (1 == channels || 3 == channels) {
+ GLCD_Image(data, width, height, channels, pos_x, pos_y,
+ downsample_factor);
+ } else {
+ printf_err("Only single and three channel images are supported!\n");
+ return 1;
+ }
+
+ return 0;
+}
+
+int lcd_display_text(const char* str, const size_t str_sz,
+ const uint32_t pos_x, const uint32_t pos_y,
+ const bool allow_multiple_lines)
+{
+ /* We use a font 0 which is 9x15. */
+ const uint32_t x_span = 9; /* Each character is this 9 pixels "wide". */
+ const uint32_t y_span = 15; /* Each character is this 15 pixels "high". */
+
+ if (str_sz == 0) {
+ return 1;
+ }
+
+ /* If not within the LCD bounds, return error. */
+ if (pos_x + x_span > GLCD_WIDTH || pos_y + y_span > GLCD_HEIGHT) {
+ return 1;
+ } else {
+ const unsigned char font_idx = 0; /* We are using the custom font = 0 */
+
+ const uint32_t col = pos_x/x_span;
+ const uint32_t max_cols = GLCD_WIDTH/x_span - 1;
+ const uint32_t max_lines = GLCD_HEIGHT/y_span - 1;
+
+ uint32_t i = 0;
+ uint32_t current_line = pos_y/y_span;
+ uint32_t current_col = col;
+
+ /* Display the string on the LCD. */
+ for (i = 0; i < str_sz; ++i) {
+
+ if (allow_multiple_lines) {
+
+ /* If the next character won't fit. */
+ if (current_col > max_cols) {
+ current_col = col;
+
+ /* If the next line won't fit. */
+ if (++current_line > max_lines) {
+ return 1;
+ }
+ }
+ }
+
+ GLCD_DisplayChar(current_line, current_col++, font_idx, str[i]);
+ }
+ }
+ return 0;
+}
+
+int lcd_display_box(const uint32_t pos_x, const uint32_t pos_y,
+ const uint32_t width, const uint32_t height, const uint16_t color)
+{
+ /* If not within the LCD bounds, return error. */
+ if (pos_x > GLCD_WIDTH || pos_y > GLCD_HEIGHT) {
+ return 1;
+ }
+ else {
+ GLCD_Box(pos_x, pos_y, width, height, color);
+ }
+ return 0;
+}
+
+int lcd_clear(const uint16_t color)
+{
+ GLCD_Clear(color);
+ GLCD_SetTextColor(White);
+ return show_title();
+}
+
+int lcd_set_text_color(const uint16_t color)
+{
+ GLCD_SetTextColor(color);
+ return 0;
+}
diff --git a/source/hal/source/components/npu/CMakeLists.txt b/source/hal/source/components/npu/CMakeLists.txt
new file mode 100644
index 0000000..804fb45
--- /dev/null
+++ b/source/hal/source/components/npu/CMakeLists.txt
@@ -0,0 +1,106 @@
+#----------------------------------------------------------------------------
+# Copyright (c) 2022 Arm Limited. All rights reserved.
+# SPDX-License-Identifier: Apache-2.0
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#----------------------------------------------------------------------------
+
+#########################################################
+# Ethos-U NPU initialization library #
+#########################################################
+
+cmake_minimum_required(VERSION 3.15.6)
+set(ETHOS_U_NPU_INIT_COMPONENT ethos_u_npu)
+project(${ETHOS_U_NPU_INIT_COMPONENT}
+ DESCRIPTION "Ethos-U NPU initialization library"
+ LANGUAGES C CXX ASM)
+
+if (NOT DEFINED ETHOS_U_NPU_DRIVER_SRC_PATH)
+ message(FATAL_ERROR "ETHOS_U_NPU_DRIVER_SRC_PATH should"
+ " be defined when ETHOS_U_NPU_ENABLED=${ETHOS_U_NPU_ENABLED}")
+endif()
+
+# For the driver, we need to provide the CMSIS_PATH variable
+set(CMSIS_PATH ${CMSIS_SRC_PATH} CACHE PATH "Path to CMSIS directory")
+
+# Driver needs to know what MAC configuration to build for.
+if(ETHOS_U_NPU_CONFIG_ID MATCHES "^[A-Z]([0-9]+$)")
+ set(ETHOSU_MACS ${CMAKE_MATCH_1})
+else()
+ message(FATAL_ERROR "Couldn't work out Ethos-U number of MACS from ${ETHOS_U_NPU_CONFIG_ID}")
+endif()
+set(ETHOSU_TARGET_NPU_CONFIG
+ "ethos-${ETHOS_U_NPU_ID}-${ETHOSU_MACS}" CACHE STRING "Target Ethos-U configuration for driver.")
+
+## Memory mode target definition
+if (NOT DEFINED ETHOS_U_NPU_ID)
+ set(ETHOS_U_NPU_ID U55)
+endif()
+
+if (NOT DEFINED ETHOS_U_NPU_MEMORY_MODE)
+ set(ETHOS_U_NPU_MEMORY_MODE Shared_Sram)
+endif()
+
+if (ETHOS_U_NPU_MEMORY_MODE STREQUAL Sram_Only)
+ if (ETHOS_U_NPU_ID STREQUAL U55)
+ set(ETHOS_U_NPU_MEMORY_MODE_FLAG "-DETHOS_U_NPU_MEMORY_MODE=ETHOS_U_NPU_MEM_MODE_SRAM_ONLY")
+ else ()
+ message(FATAL_ERROR "Non compatible Ethos-U NPU memory mode and processor ${ETHOS_U_NPU_MEMORY_MODE} - ${ETHOS_U_NPU_ID}. `sram_only` can be used only for Ethos-U55.")
+ endif ()
+elseif (ETHOS_U_NPU_MEMORY_MODE STREQUAL Shared_Sram)
+ # Shared Sram can be used for Ethos-U55 and Ethos-U65
+ set(ETHOS_U_NPU_MEMORY_MODE_FLAG "-DETHOS_U_NPU_MEMORY_MODE=ETHOS_U_NPU_MEMORY_MODE_SHARED_SRAM")
+elseif (ETHOS_U_NPU_MEMORY_MODE STREQUAL Dedicated_Sram)
+ # Dedicated Sram is used only for Ethos-U65
+ if (ETHOS_U_NPU_ID STREQUAL U65)
+ list(APPEND ETHOS_U_NPU_MEMORY_MODE_FLAG "-DETHOS_U_NPU_MEMORY_MODE=ETHOS_U_NPU_MEMORY_MODE_DEDICATED_SRAM" "-DETHOS_U_NPU_CACHE_SIZE=${ETHOS_U_NPU_CACHE_SIZE}")
+ else ()
+ message(FATAL_ERROR "Non compatible Ethos-U NPU memory mode and processor ${ETHOS_U_NPU_MEMORY_MODE} - ${ETHOS_U_NPU_ID}. `dedicated_sram` can be used only for Ethos-U65.")
+ endif ()
+else ()
+ message(FATAL_ERROR "Non compatible Ethos-U NPU memory mode ${ETHOS_U_NPU_MEMORY_MODE}")
+endif ()
+
+add_subdirectory(${ETHOS_U_NPU_DRIVER_SRC_PATH} ${CMAKE_BINARY_DIR}/ethos-u-driver)
+
+# Create static library
+add_library(${ETHOS_U_NPU_INIT_COMPONENT} STATIC)
+
+## Include directories - public
+target_include_directories(${ETHOS_U_NPU_INIT_COMPONENT}
+ PUBLIC
+ include
+ ${SOURCE_GEN_DIR})
+
+## Component sources
+target_sources(${ETHOS_U_NPU_INIT_COMPONENT}
+ PRIVATE
+ ethosu_npu_init.c
+ ethosu_cpu_cache.c)
+
+## Add dependencies:
+target_link_libraries(${ETHOS_U_NPU_INIT_COMPONENT} PUBLIC
+ cmsis_device_cpu_header
+ ethosu_core_driver
+ log)
+
+target_compile_definitions(${ETHOS_U_NPU_INIT_COMPONENT}
+ PUBLIC
+ ARM_NPU
+ ${ETHOS_U_NPU_MEMORY_MODE_FLAG})
+
+# Display status
+message(STATUS "CMAKE_CURRENT_SOURCE_DIR: " ${CMAKE_CURRENT_SOURCE_DIR})
+message(STATUS "*******************************************************")
+message(STATUS "Library : " ${ETHOS_U_NPU_INIT_COMPONENT})
+message(STATUS "*******************************************************")
diff --git a/source/hal/source/components/npu/ethosu_cpu_cache.c b/source/hal/source/components/npu/ethosu_cpu_cache.c
new file mode 100644
index 0000000..13f6f0a
--- /dev/null
+++ b/source/hal/source/components/npu/ethosu_cpu_cache.c
@@ -0,0 +1,54 @@
+/*
+ * Copyright (c) 2022 Arm Limited. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ethosu_cpu_cache.h"
+
+#include "RTE_Components.h" /* For CPU related defintiions */
+#include "ethosu_driver.h" /* Arm Ethos-U driver header */
+#include "log_macros.h" /* Logging macros */
+
+void ethosu_flush_dcache(uint32_t *p, size_t bytes)
+{
+#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+ if (SCB->CCR & SCB_CCR_DC_Msk) {
+ if (p) {
+ SCB_CleanDCache_by_Addr((void *) p, (int32_t) bytes);
+ } else {
+ SCB_CleanDCache();
+ }
+ }
+#else
+ UNUSED(p);
+ UNUSED(bytes);
+#endif /* defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) */
+}
+
+void ethosu_invalidate_dcache(uint32_t *p, size_t bytes)
+{
+#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+ if (SCB->CCR & SCB_CCR_DC_Msk) {
+ if (p) {
+ SCB_InvalidateDCache_by_Addr((void *) p, (int32_t) bytes);
+ } else {
+ SCB_InvalidateDCache();
+ }
+ }
+#else
+ UNUSED(p);
+ UNUSED(bytes);
+#endif /* defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) */
+}
diff --git a/source/hal/source/components/npu/ethosu_npu_init.c b/source/hal/source/components/npu/ethosu_npu_init.c
new file mode 100644
index 0000000..9ccd887
--- /dev/null
+++ b/source/hal/source/components/npu/ethosu_npu_init.c
@@ -0,0 +1,122 @@
+/*
+ * Copyright (c) 2022 Arm Limited. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ethosu_npu_init.h"
+
+#include "RTE_Components.h" /* For CPU related defintiions */
+#include "peripheral_memmap.h" /* Peripheral memory map definitions. */
+#include "peripheral_irqs.h" /* IRQ numbers for this platform. */
+#include "log_macros.h" /* Logging functions */
+
+#include "ethosu_mem_config.h" /* Arm Ethos-U memory config */
+#include "ethosu_driver.h" /* Arm Ethos-U driver header */
+
+struct ethosu_driver ethosu_drv; /* Default Ethos-U device driver */
+
+#if defined(ETHOS_U_CACHE_BUF_SZ) && (ETHOS_U_CACHE_BUF_SZ > 0)
+static uint8_t cache_arena[ETHOS_U_CACHE_BUF_SZ] CACHE_BUF_ATTRIBUTE;
+#else /* defined (ETHOS_U_CACHE_BUF_SZ) && (ETHOS_U_CACHE_BUF_SZ > 0) */
+static uint8_t *cache_arena = NULL;
+#endif /* defined (ETHOS_U_CACHE_BUF_SZ) && (ETHOS_U_CACHE_BUF_SZ > 0) */
+
+static uint8_t *get_cache_arena()
+{
+ return cache_arena;
+}
+
+static size_t get_cache_arena_size()
+{
+#if defined(ETHOS_U_CACHE_BUF_SZ) && (ETHOS_U_CACHE_BUF_SZ > 0)
+ return sizeof(cache_arena);
+#else /* defined (ETHOS_U_CACHE_BUF_SZ) && (ETHOS_U_CACHE_BUF_SZ > 0) */
+ return 0;
+#endif /* defined (ETHOS_U_CACHE_BUF_SZ) && (ETHOS_U_CACHE_BUF_SZ > 0) */
+}
+
+/**
+ * @brief Defines the Ethos-U interrupt handler: just a wrapper around the default
+ * implementation.
+ **/
+static void arm_ethosu_npu_irq_handler(void)
+{
+ /* Call the default interrupt handler from the NPU driver */
+ ethosu_irq_handler(ðosu_drv);
+}
+
+/**
+ * @brief Initialises the NPU IRQ
+ **/
+static void arm_ethosu_npu_irq_init(void)
+{
+ const IRQn_Type ethosu_irqnum = (IRQn_Type)EthosU_IRQn;
+
+ /* Register the EthosU IRQ handler in our vector table.
+ * Note, this handler comes from the EthosU driver */
+ NVIC_SetVector(ethosu_irqnum, (uint32_t)arm_ethosu_npu_irq_handler);
+
+ /* Enable the IRQ */
+ NVIC_EnableIRQ(ethosu_irqnum);
+
+ debug("EthosU IRQ#: %u, Handler: 0x%p\n",
+ ethosu_irqnum, arm_ethosu_npu_irq_handler);
+}
+
+int arm_ethosu_npu_init(void)
+{
+ int err = 0;
+
+ /* Initialise the IRQ */
+ arm_ethosu_npu_irq_init();
+
+ /* Initialise Ethos-U device */
+ const void *ethosu_base_address = (void *)(SEC_ETHOS_U_NPU_BASE);
+
+ if (0 != (err = ethosu_init(
+ ðosu_drv, /* Ethos-U driver device pointer */
+ ethosu_base_address, /* Ethos-U NPU's base address. */
+ get_cache_arena(), /* Pointer to fast mem area - NULL for U55. */
+ get_cache_arena_size(), /* Fast mem region size. */
+ 1, /* Security enable. */
+ 1))) /* Privilege enable. */
+ {
+ printf_err("failed to initialise Ethos-U device\n");
+ return err;
+ }
+
+ info("Ethos-U device initialised\n");
+
+ /* Get Ethos-U version */
+ struct ethosu_driver_version driver_version;
+ struct ethosu_hw_info hw_info;
+
+ ethosu_get_driver_version(&driver_version);
+ ethosu_get_hw_info(ðosu_drv, &hw_info);
+
+ info("Ethos-U version info:\n");
+ info("\tArch: v%" PRIu32 ".%" PRIu32 ".%" PRIu32 "\n",
+ hw_info.version.arch_major_rev,
+ hw_info.version.arch_minor_rev,
+ hw_info.version.arch_patch_rev);
+ info("\tDriver: v%" PRIu8 ".%" PRIu8 ".%" PRIu8 "\n",
+ driver_version.major,
+ driver_version.minor,
+ driver_version.patch);
+ info("\tMACs/cc: %" PRIu32 "\n", (uint32_t)(1 << hw_info.cfg.macs_per_cc));
+ info("\tCmd stream: v%" PRIu32 "\n", hw_info.cfg.cmd_stream_version);
+
+ return 0;
+}
diff --git a/source/hal/source/components/npu/include/ethosu_cpu_cache.h b/source/hal/source/components/npu/include/ethosu_cpu_cache.h
new file mode 100644
index 0000000..9f21acf
--- /dev/null
+++ b/source/hal/source/components/npu/include/ethosu_cpu_cache.h
@@ -0,0 +1,39 @@
+/*
+ * Copyright (c) 2022 Arm Limited. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef ETHOSU_CPU_CACHE
+#define ETHOSU_CPU_CACHE
+
+#include <stdint.h>
+#include <stddef.h>
+
+/**
+ * @brief Flush/clean the data cache by address and size. Passing NULL as p argument
+ * expects the whole cache to be flushed.
+ * @param[in] p Pointer to the start address.
+ * @param[in] bytes Number of bytes to flush beginning at start address.
+ */
+void ethosu_flush_dcache(uint32_t *p, size_t bytes);
+
+/**
+ * @brief Invalidate the data cache by address and size. Passing NULL as p argument
+ * expects the whole cache to be invalidated.
+ * @param[in] p Pointer to the start address.
+ * @param[in] bytes Number of bytes to flush beginning at start address.
+ */
+void ethosu_invalidate_dcache(uint32_t *p, size_t bytes);
+
+#endif /* ETHOSU_CPU_CACHE */
diff --git a/source/hal/source/components/npu/include/ethosu_mem_config.h b/source/hal/source/components/npu/include/ethosu_mem_config.h
new file mode 100644
index 0000000..aa0cfda
--- /dev/null
+++ b/source/hal/source/components/npu/include/ethosu_mem_config.h
@@ -0,0 +1,58 @@
+/*
+ * Copyright (c) 2022 Arm Limited. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef ETHOS_U_NPU_MEM_CONFIG_H
+#define ETHOS_U_NPU_MEM_CONFIG_H
+
+#define ETHOS_U_NPU_MEMORY_MODE_SRAM_ONLY 0
+#define ETHOS_U_NPU_MEMORY_MODE_SHARED_SRAM 1
+#define ETHOS_U_NPU_MEMORY_MODE_DEDICATED_SRAM 2
+
+#define ETHOS_U_MEM_BYTE_ALIGNMENT 16
+
+#ifndef ETHOS_U_NPU_MEMORY_MODE
+ #define ETHOS_U_NPU_MEMORY_MODE ETHOS_U_MEMORY_MODE_SHARED_SRAM
+#endif /* ETHOS_U_NPU_MEMORY_MODE */
+
+#if (ETHOS_U_NPU_MEMORY_MODE==ETHOS_U_NPU_MEMORY_MODE_DEDICATED_SRAM)
+ #ifndef ETHOS_U_NPU_CACHE_SIZE
+ #define ETHOS_U_CACHE_BUF_SZ (393216U) /* See vela doc for reference */
+ #else
+ #define ETHOS_U_CACHE_BUF_SZ ETHOS_U_NPU_CACHE_SIZE
+ #endif /* ETHOS_U_NPU_CACHE_SIZE */
+#else
+ #define ETHOS_U_CACHE_BUF_SZ (0U)
+#endif /* CACHE_BUF_SZ */
+
+/**
+ * Activation buffer aka tensor arena section name
+ * We have to place the tensor arena in different region based on the memory config.
+ **/
+#if (ETHOS_U_NPU_MEMORY_MODE==ETHOS_U_NPU_MEMORY_MODE_SHARED_SRAM)
+ #define ACTIVATION_BUF_SECTION section(".bss.NoInit.activation_buf_sram")
+ #define ACTIVATION_BUF_SECTION_NAME ("SRAM")
+#elif (ETHOS_U_NPU_MEMORY_MODE==ETHOS_U_NPU_MEMORY_MODE_SRAM_ONLY)
+ #define ACTIVATION_BUF_SECTION section(".bss.NoInit.activation_buf_sram")
+ #define ACTIVATION_BUF_SECTION_NAME ("SRAM")
+#elif (ETHOS_U_NPU_MEMORY_MODE==ETHOS_U_NPU_MEMORY_MODE_DEDICATED_SRAM)
+ #define ACTIVATION_BUF_SECTION section("activation_buf_dram")
+ #define CACHE_BUF_SECTION section(".bss.NoInit.ethos_u_cache")
+ #define ACTIVATION_BUF_SECTION_NAME ("DDR/DRAM")
+ #define CACHE_BUF_ATTRIBUTE __attribute__((aligned(ETHOS_U_MEM_BYTE_ALIGNMENT), CACHE_BUF_SECTION))
+#endif
+
+#endif /* ETHOS_U_NPU_MEM_CONFIG_H */
diff --git a/source/hal/source/components/npu/include/ethosu_npu_init.h b/source/hal/source/components/npu/include/ethosu_npu_init.h
new file mode 100644
index 0000000..c562f6c
--- /dev/null
+++ b/source/hal/source/components/npu/include/ethosu_npu_init.h
@@ -0,0 +1,30 @@
+/*
+ * Copyright (c) 2022 Arm Limited. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef ETHOS_U_NPU_INIT_H
+#define ETHOS_U_NPU_INIT_H
+
+#if defined(ARM_NPU)
+
+/**
+ * @brief Initialises the Arm Ethos-U NPU
+ * @return 0 if successful, error code otherwise
+ **/
+int arm_ethosu_npu_init(void);
+
+#endif /* ARM_NPU */
+
+#endif /* ETHOS_U_NPU_INIT_H */
diff --git a/source/hal/source/components/npu_ta/CMakeLists.txt b/source/hal/source/components/npu_ta/CMakeLists.txt
new file mode 100644
index 0000000..fdda723
--- /dev/null
+++ b/source/hal/source/components/npu_ta/CMakeLists.txt
@@ -0,0 +1,77 @@
+#----------------------------------------------------------------------------
+# Copyright (c) 2022 Arm Limited. All rights reserved.
+# SPDX-License-Identifier: Apache-2.0
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#----------------------------------------------------------------------------
+
+#########################################################
+# Ethos-U NPU timing adapter initialization library #
+#########################################################
+
+# Timing adapter component is only available on certain implementations
+# on FPGA and FVP where it is necessary to run bandwidth and latency
+# sweeps on the Arm Ethos-U NPUs. The wrapper library here provides an
+# easy way to add initialisation of the timing adapter block.
+
+cmake_minimum_required(VERSION 3.15.6)
+set(ETHOS_U_NPU_TA_COMPONENT ethos_u_ta)
+project(${ETHOS_U_NPU_TA_COMPONENT}
+ DESCRIPTION "Ethos-U NPU timing adapter initialization library"
+ LANGUAGES C CXX ASM)
+
+# Checks
+## If a TA config file is provided, we generate a settings file
+if (DEFINED TA_CONFIG_FILE)
+ include(${TA_CONFIG_FILE})
+ set(TA_SETTINGS_TEMPLATE ${CMAKE_CURRENT_SOURCE_DIR}/cmake/templates/timing_adapter_settings.template)
+ configure_file("${TA_SETTINGS_TEMPLATE}" "${SOURCE_GEN_DIR}/timing_adapter_settings.h")
+endif()
+
+## Timing adapter Source path check
+if (NOT DEFINED ETHOS_U_NPU_TIMING_ADAPTER_SRC_PATH)
+ message(FATAL_ERROR "ETHOS_U_NPU_TIMING_ADAPTER_SRC_PATH should"
+ " be defined when ETHOS_U_NPU_ENABLED=${ETHOS_U_NPU_ENABLED}")
+endif()
+
+add_subdirectory(${ETHOS_U_NPU_TIMING_ADAPTER_SRC_PATH} ${CMAKE_BINARY_DIR}/timing_adapter)
+
+# Create static library
+add_library(${ETHOS_U_NPU_TA_COMPONENT} STATIC)
+
+## Include directories - public
+target_include_directories(${ETHOS_U_NPU_TA_COMPONENT}
+ PUBLIC
+ include
+ ${SOURCE_GEN_DIR})
+
+## Component sources
+target_sources(${ETHOS_U_NPU_TA_COMPONENT}
+ PRIVATE
+ ethosu_ta_init.c)
+
+## Compile definitions
+target_compile_definitions(${ETHOS_U_NPU_TA_COMPONENT}
+ PUBLIC
+ ETHOS_U_NPU_TIMING_ADAPTER_ENABLED)
+
+## Add dependencies
+target_link_libraries(${ETHOS_U_NPU_TA_COMPONENT} PUBLIC
+ timing_adapter
+ log)
+
+# Display status
+message(STATUS "CMAKE_CURRENT_SOURCE_DIR: " ${CMAKE_CURRENT_SOURCE_DIR})
+message(STATUS "*******************************************************")
+message(STATUS "Library : " ${ETHOS_U_NPU_TA_COMPONENT})
+message(STATUS "*******************************************************")
diff --git a/source/hal/source/components/npu_ta/cmake/templates/timing_adapter_settings.template b/source/hal/source/components/npu_ta/cmake/templates/timing_adapter_settings.template
new file mode 100644
index 0000000..5b6c43d
--- /dev/null
+++ b/source/hal/source/components/npu_ta/cmake/templates/timing_adapter_settings.template
@@ -0,0 +1,64 @@
+/*
+ * Copyright (c) 2021 Arm Limited. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+// Auto-generated file
+// ** DO NOT EDIT **
+
+#ifndef TIMING_ADAPTER_SETTINGS_H
+#define TIMING_ADAPTER_SETTINGS_H
+
+#cmakedefine TA0_BASE (@TA0_BASE@)
+#cmakedefine TA1_BASE (@TA1_BASE@)
+
+/* Timing adapter settings for AXI0 */
+#if defined(TA0_BASE)
+
+#define TA0_MAXR (@TA0_MAXR@)
+#define TA0_MAXW (@TA0_MAXW@)
+#define TA0_MAXRW (@TA0_MAXRW@)
+#define TA0_RLATENCY (@TA0_RLATENCY@)
+#define TA0_WLATENCY (@TA0_WLATENCY@)
+#define TA0_PULSE_ON (@TA0_PULSE_ON@)
+#define TA0_PULSE_OFF (@TA0_PULSE_OFF@)
+#define TA0_BWCAP (@TA0_BWCAP@)
+#define TA0_PERFCTRL (@TA0_PERFCTRL@)
+#define TA0_PERFCNT (@TA0_PERFCNT@)
+#define TA0_MODE (@TA0_MODE@)
+#define TA0_HISTBIN (@TA0_HISTBIN@)
+#define TA0_HISTCNT (@TA0_HISTCNT@)
+
+#endif /* defined(TA0_BASE) */
+
+/* Timing adapter settings for AXI1 */
+#if defined(TA1_BASE)
+
+#define TA1_MAXR (@TA1_MAXR@)
+#define TA1_MAXW (@TA1_MAXW@)
+#define TA1_MAXRW (@TA1_MAXRW@)
+#define TA1_RLATENCY (@TA1_RLATENCY@)
+#define TA1_WLATENCY (@TA1_WLATENCY@)
+#define TA1_PULSE_ON (@TA1_PULSE_ON@)
+#define TA1_PULSE_OFF (@TA1_PULSE_OFF@)
+#define TA1_BWCAP (@TA1_BWCAP@)
+#define TA1_PERFCTRL (@TA1_PERFCTRL@)
+#define TA1_PERFCNT (@TA1_PERFCNT@)
+#define TA1_MODE (@TA1_MODE@)
+#define TA1_HISTBIN (@TA1_HISTBIN@)
+#define TA1_HISTCNT (@TA1_HISTCNT@)
+
+#endif /* defined(TA1_BASE) */
+
+#endif /* TIMING_ADAPTER_SETTINGS_H */
diff --git a/source/hal/source/components/npu_ta/ethosu_ta_init.c b/source/hal/source/components/npu_ta/ethosu_ta_init.c
new file mode 100644
index 0000000..323ab73
--- /dev/null
+++ b/source/hal/source/components/npu_ta/ethosu_ta_init.c
@@ -0,0 +1,82 @@
+/*
+ * Copyright (c) 2022 Arm Limited. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ethosu_ta_init.h"
+
+#include "log_macros.h" /* Logging functions */
+
+#include "timing_adapter.h" /* Arm Ethos-U timing adapter driver header */
+#include "timing_adapter_settings.h" /* Arm Ethos-U timing adapter settings */
+
+int arm_ethosu_timing_adapter_init(void)
+{
+#if defined(TA0_BASE)
+ struct timing_adapter ta_0;
+ struct timing_adapter_settings ta_0_settings = {
+ .maxr = TA0_MAXR,
+ .maxw = TA0_MAXW,
+ .maxrw = TA0_MAXRW,
+ .rlatency = TA0_RLATENCY,
+ .wlatency = TA0_WLATENCY,
+ .pulse_on = TA0_PULSE_ON,
+ .pulse_off = TA0_PULSE_OFF,
+ .bwcap = TA0_BWCAP,
+ .perfctrl = TA0_PERFCTRL,
+ .perfcnt = TA0_PERFCNT,
+ .mode = TA0_MODE,
+ .maxpending = 0, /* This is a read-only parameter */
+ .histbin = TA0_HISTBIN,
+ .histcnt = TA0_HISTCNT};
+
+ if (0 != ta_init(&ta_0, TA0_BASE))
+ {
+ printf_err("TA0 initialisation failed\n");
+ return 1;
+ }
+
+ ta_set_all(&ta_0, &ta_0_settings);
+#endif /* defined (TA0_BASE) */
+
+#if defined(TA1_BASE)
+ struct timing_adapter ta_1;
+ struct timing_adapter_settings ta_1_settings = {
+ .maxr = TA1_MAXR,
+ .maxw = TA1_MAXW,
+ .maxrw = TA1_MAXRW,
+ .rlatency = TA1_RLATENCY,
+ .wlatency = TA1_WLATENCY,
+ .pulse_on = TA1_PULSE_ON,
+ .pulse_off = TA1_PULSE_OFF,
+ .bwcap = TA1_BWCAP,
+ .perfctrl = TA1_PERFCTRL,
+ .perfcnt = TA1_PERFCNT,
+ .mode = TA1_MODE,
+ .maxpending = 0, /* This is a read-only parameter */
+ .histbin = TA1_HISTBIN,
+ .histcnt = TA1_HISTCNT};
+
+ if (0 != ta_init(&ta_1, TA1_BASE))
+ {
+ printf_err("TA1 initialisation failed\n");
+ return 1;
+ }
+
+ ta_set_all(&ta_1, &ta_1_settings);
+#endif /* defined (TA1_BASE) */
+
+ return 0;
+}
diff --git a/source/hal/source/components/npu_ta/include/ethosu_ta_init.h b/source/hal/source/components/npu_ta/include/ethosu_ta_init.h
new file mode 100644
index 0000000..7e6df6c
--- /dev/null
+++ b/source/hal/source/components/npu_ta/include/ethosu_ta_init.h
@@ -0,0 +1,26 @@
+/*
+ * Copyright (c) 2022 Arm Limited. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef ETHOS_U_TA_INIT_H
+#define ETHOS_U_TA_INIT_H
+
+/**
+ * @brief Initialises the Arm Ethos-U NPU timing adapter
+ * @return 0 if successful, error code otherwise
+ **/
+int arm_ethosu_timing_adapter_init(void);
+
+#endif /* ETHOS_U_TA_INIT_H */
diff --git a/source/hal/source/components/stdout/CMakeLists.txt b/source/hal/source/components/stdout/CMakeLists.txt
new file mode 100644
index 0000000..f1e26ff
--- /dev/null
+++ b/source/hal/source/components/stdout/CMakeLists.txt
@@ -0,0 +1,110 @@
+#----------------------------------------------------------------------------
+# Copyright (c) 2022 Arm Limited. All rights reserved.
+# SPDX-License-Identifier: Apache-2.0
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#----------------------------------------------------------------------------
+
+#########################################################
+# Wrapper for enabling stdout and stderr facility #
+#########################################################
+# This is a wrapper around the UART module for CMSDK #
+# and PL011 UART drivers with retarget functions. #
+#########################################################
+
+cmake_minimum_required(VERSION 3.15.6)
+
+project(stdout
+ DESCRIPTION "Standard output and err redirection over UART"
+ LANGUAGES C CXX)
+
+
+set(STDOUT_RETARGET OFF CACHE BOOL "Retarget stdout/err to UART")
+
+# Interface library for standard output:
+set(STDOUT_IFACE_TARGET stdout_iface)
+add_library(${STDOUT_IFACE_TARGET} INTERFACE)
+target_include_directories(${STDOUT_IFACE_TARGET} INTERFACE include)
+
+if (STDOUT_RETARGET)
+
+ set(STDOUT_COMPONENT_CMSDK stdout_retarget_cmsdk)
+ set(STDOUT_COMPONENT_PL011 stdout_retarget_pl011)
+
+ add_library(${STDOUT_COMPONENT_CMSDK} STATIC)
+ add_library(${STDOUT_COMPONENT_PL011} STATIC)
+
+ # Check prerequisites
+ ## Core platform directory is required to add the UART library project.
+ if (NOT DEFINED CORE_PLATFORM_DIR)
+ message(FATAL_ERROR "CORE_PLATFORM_DIR undefined")
+ endif()
+
+ ## UART0_BASE is the base address for UART configuration. The platform
+ ## should define it prior to including this library.
+ if (NOT DEFINED UART0_BASE)
+ message(WARNING "UART0_BASE undefined, default will be used.")
+ endif()
+
+ ## Platform component: UART
+ add_subdirectory(${CORE_PLATFORM_DIR}/drivers/uart ${CMAKE_BINARY_DIR}/uart)
+
+ ## Component sources - public
+ target_sources(${STDOUT_COMPONENT_CMSDK}
+ PUBLIC
+ source/retarget.c)
+
+ ## Component sources - public
+ target_sources(${STDOUT_COMPONENT_PL011}
+ PUBLIC
+ source/retarget.c)
+
+ # Link
+ target_link_libraries(${STDOUT_COMPONENT_CMSDK}
+ PUBLIC
+ ${STDOUT_IFACE_TARGET}
+ ethosu_uart_cmsdk_apb)
+
+ target_link_libraries(${STDOUT_COMPONENT_PL011}
+ PUBLIC
+ ${STDOUT_IFACE_TARGET}
+ ethosu_uart_pl011)
+
+ # Display status
+ message(STATUS "CMAKE_CURRENT_SOURCE_DIR: " ${CMAKE_CURRENT_SOURCE_DIR})
+ message(STATUS "*******************************************************")
+ message(STATUS "Library: " ${STDOUT_COMPONENT_CMSDK})
+ message(STATUS "Library: " ${STDOUT_COMPONENT_PL011})
+ message(STATUS "*******************************************************")
+
+else()
+
+ # Create static library for retarget (stdout/err over UART)
+ set(STDOUT_COMPONENT stdout)
+ add_library(${STDOUT_COMPONENT} STATIC)
+
+ ## Component sources - public
+ target_sources(${STDOUT_COMPONENT}
+ PUBLIC
+ source/user_input.c)
+
+ target_link_libraries(${STDOUT_COMPONENT}
+ PUBLIC
+ ${STDOUT_IFACE_TARGET})
+
+ # Display status
+ message(STATUS "CMAKE_CURRENT_SOURCE_DIR: " ${CMAKE_CURRENT_SOURCE_DIR})
+ message(STATUS "*******************************************************")
+ message(STATUS "Library: " ${STDOUT_COMPONENT})
+ message(STATUS "*******************************************************")
+endif()
diff --git a/source/hal/source/components/stdout/include/user_input.h b/source/hal/source/components/stdout/include/user_input.h
new file mode 100644
index 0000000..e76b418
--- /dev/null
+++ b/source/hal/source/components/stdout/include/user_input.h
@@ -0,0 +1,30 @@
+/*
+ * Copyright (c) 2022 Arm Limited. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef STDOUT_USER_INPUT_H
+#define STDOUT_USER_INPUT_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+unsigned int GetLine(char *user_input, unsigned int size);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* STDOUT_USER_INPUT_H */
diff --git a/source/hal/source/components/stdout/source/retarget.c b/source/hal/source/components/stdout/source/retarget.c
new file mode 100644
index 0000000..ac9b282
--- /dev/null
+++ b/source/hal/source/components/stdout/source/retarget.c
@@ -0,0 +1,278 @@
+/*
+ * Copyright (c) 2022 Arm Limited. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#if !defined(USE_SEMIHOSTING)
+
+#include "uart_stdout.h"
+
+#include <stdio.h>
+#include <string.h>
+#include <time.h>
+
+#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100)
+/* Arm compiler re-targeting */
+
+#include <rt_misc.h>
+#include <rt_sys.h>
+
+
+/* Standard IO device handles. */
+#define STDIN 0x8001
+#define STDOUT 0x8002
+#define STDERR 0x8003
+
+#define RETARGET(fun) _sys##fun
+
+#else
+/* GNU compiler re-targeting */
+
+/*
+ * This type is used by the _ I/O functions to denote an open
+ * file.
+ */
+typedef int FILEHANDLE;
+
+/*
+ * Open a file. May return -1 if the file failed to open.
+ */
+extern FILEHANDLE _open(const char * /*name*/, int /*openmode*/);
+
+/* Standard IO device handles. */
+#define STDIN 0x00
+#define STDOUT 0x01
+#define STDERR 0x02
+
+#define RETARGET(fun) fun
+
+#endif
+
+/* Standard IO device name defines. */
+const char __stdin_name[] __attribute__((aligned(4))) = "STDIN";
+const char __stdout_name[] __attribute__((aligned(4))) = "STDOUT";
+const char __stderr_name[] __attribute__((aligned(4))) = "STDERR";
+
+__attribute__((noreturn)) static void UartEndSimulation(int code)
+{
+ UartPutc((char) 0x4); // End of simulation
+ UartPutc((char) code); // Exit code
+ while(1);
+}
+
+void _ttywrch(int ch) {
+ (void)fputc(ch, stdout);
+}
+
+FILEHANDLE RETARGET(_open)(const char *name, int openmode)
+{
+ (void)(openmode);
+
+ if (strcmp(name, __stdin_name) == 0) {
+ return (STDIN);
+ }
+
+ if (strcmp(name, __stdout_name) == 0) {
+ return (STDOUT);
+ }
+
+ if (strcmp(name, __stderr_name) == 0) {
+ return (STDERR);
+ }
+
+ return -1;
+}
+
+int RETARGET(_write)(FILEHANDLE fh, const unsigned char *buf, unsigned int len, int mode)
+{
+ (void)(mode);
+
+ switch (fh) {
+ case STDOUT:
+ case STDERR: {
+ int c;
+
+ while (len-- > 0) {
+ c = fputc(*buf++, stdout);
+ if (c == EOF) {
+ return EOF;
+ }
+ }
+
+ return 0;
+ }
+ default:
+ return EOF;
+ }
+}
+
+int RETARGET(_read)(FILEHANDLE fh, unsigned char *buf, unsigned int len, int mode)
+{
+ (void)(mode);
+
+ switch (fh) {
+ case STDIN: {
+ int c;
+
+ while (len-- > 0) {
+ c = fgetc(stdin);
+ if (c == EOF) {
+ return EOF;
+ }
+
+ *buf++ = (unsigned char)c;
+ }
+
+ return 0;
+ }
+ default:
+ return EOF;
+ }
+}
+
+int RETARGET(_istty)(FILEHANDLE fh)
+{
+ switch (fh) {
+ case STDIN:
+ case STDOUT:
+ case STDERR:
+ return 1;
+ default:
+ return 0;
+ }
+}
+
+int RETARGET(_close)(FILEHANDLE fh)
+{
+ if (RETARGET(_istty(fh))) {
+ return 0;
+ }
+
+ return -1;
+}
+
+int RETARGET(_seek)(FILEHANDLE fh, long pos)
+{
+ (void)(fh);
+ (void)(pos);
+
+ return -1;
+}
+
+int RETARGET(_ensure)(FILEHANDLE fh)
+{
+ (void)(fh);
+
+ return -1;
+}
+
+long RETARGET(_flen)(FILEHANDLE fh)
+{
+ if (RETARGET(_istty)(fh)) {
+ return 0;
+ }
+
+ return -1;
+}
+
+int RETARGET(_tmpnam)(char *name, int sig, unsigned int maxlen)
+{
+ (void)(name);
+ (void)(sig);
+ (void)(maxlen);
+
+ return 1;
+}
+
+char *RETARGET(_command_string)(char *cmd, int len)
+{
+ (void)(len);
+
+ return cmd;
+}
+
+void RETARGET(_exit)(int return_code)
+{
+ UartEndSimulation(return_code);
+ while(1);
+}
+
+int system(const char *cmd)
+{
+ (void)(cmd);
+
+ return 0;
+}
+
+time_t time(time_t *timer)
+{
+ time_t current;
+
+ current = 0; // To Do !! No RTC implemented
+
+ if (timer != NULL) {
+ *timer = current;
+ }
+
+ return current;
+}
+
+void _clock_init(void) {}
+
+clock_t clock(void)
+{
+ return (clock_t)-1;
+}
+
+int remove(const char *arg) {
+ (void)(arg);
+
+ return 0;
+}
+
+int rename(const char *oldn, const char *newn)
+{
+ (void)(oldn);
+ (void)(newn);
+
+ return 0;
+}
+
+int fputc(int ch, FILE *f)
+{
+ (void)(f);
+
+ return UartPutc(ch);
+}
+
+int fgetc(FILE *f)
+{
+ (void)(f);
+
+ return UartPutc(UartGetc());
+}
+
+#ifndef ferror
+
+/* arm-none-eabi-gcc with newlib uses a define for ferror */
+int ferror(FILE *f)
+{
+ (void)(f);
+
+ return EOF;
+}
+
+#endif /* #ifndef ferror */
+
+#endif /* !defined(USE_SEMIHOSTING) */
diff --git a/source/hal/source/components/stdout/source/user_input.c b/source/hal/source/components/stdout/source/user_input.c
new file mode 100644
index 0000000..e5fe1b9
--- /dev/null
+++ b/source/hal/source/components/stdout/source/user_input.c
@@ -0,0 +1,33 @@
+/*
+ * Copyright (c) 2022 Arm Limited. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdio.h>
+
+unsigned int GetLine(char *user_input, unsigned int size)
+{
+ if (NULL != fgets(user_input, size, stdin)) {
+ return 1;
+ }
+ return 0;
+}
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/source/hal/source/data_acq.c b/source/hal/source/data_acq.c
new file mode 100644
index 0000000..ec6c725
--- /dev/null
+++ b/source/hal/source/data_acq.c
@@ -0,0 +1,61 @@
+/*
+ * Copyright (c) 2022 Arm Limited. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "data_acq.h"
+
+#include "log_macros.h"
+#include "platform_drivers.h"
+
+#include <assert.h>
+#include <stdlib.h>
+#include <string.h>
+
+/**
+ * @brief Get the user input from USART.
+ * @param[out] user_input String read from the UART block.
+ * @param[in] size String read length.
+ * @return 0 if successful, error code otherwise.
+ **/
+static int get_uart_user_input(char* user_input, int size)
+{
+ if (1 != GetLine(user_input, size - 1)) {
+ return 1;
+ }
+ return 0;
+}
+
+int data_acq_channel_init(data_acq_module* module)
+{
+ assert(module);
+
+ /* UART should have been initialised with low level initialisation
+ * routines. */
+ module->system_init = NULL;
+
+ strncpy(module->system_name, "UART", sizeof(module->system_name));
+ module->get_input = get_uart_user_input;
+ module->inited = 1;
+
+ return !(module->inited);
+}
+
+int data_acq_channel_release(data_acq_module* module)
+{
+ assert(module);
+ module->inited = 0;
+ module->get_input = NULL;
+ return 0;
+}
diff --git a/source/hal/source/data_psn.c b/source/hal/source/data_psn.c
new file mode 100644
index 0000000..de088d7
--- /dev/null
+++ b/source/hal/source/data_psn.c
@@ -0,0 +1,46 @@
+/*
+ * Copyright (c) 2022 Arm Limited. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "data_psn.h"
+
+#include "lcd_img.h"
+#include "platform_drivers.h"
+
+#include <assert.h>
+#include <string.h>
+
+int data_psn_system_init(data_psn_module* module)
+{
+ assert(module);
+
+ /* LCD output supported. */
+ module->system_init = lcd_init;
+ module->present_data_image = lcd_display_image;
+ module->present_data_text = lcd_display_text;
+ module->present_box = lcd_display_box;
+ module->set_text_color = lcd_set_text_color;
+ module->clear = lcd_clear;
+ strncpy(module->system_name, "lcd", sizeof(module->system_name));
+ module->inited = !module->system_init();
+ return !module->inited;
+}
+
+int data_psn_system_release(data_psn_module* module)
+{
+ assert(module);
+ module->inited = 0;
+ return 0;
+}
diff --git a/source/hal/source/hal.c b/source/hal/source/hal.c
new file mode 100644
index 0000000..2715a17
--- /dev/null
+++ b/source/hal/source/hal.c
@@ -0,0 +1,104 @@
+/*
+ * Copyright (c) 2022 Arm Limited. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "hal.h" /* API */
+
+#include "platform_drivers.h" /* Platform drivers */
+#include "log_macros.h" /* Logging macros */
+
+#include <stdio.h>
+#include <assert.h>
+#include <string.h>
+
+int hal_init(hal_platform* platform, data_acq_module* data_acq,
+ data_psn_module* data_psn, platform_timer* timer)
+{
+ assert(platform && data_acq && data_psn);
+
+ platform->data_acq = data_acq;
+ platform->data_psn = data_psn;
+ platform->timer = timer;
+ platform->platform_init = platform_init;
+ platform->platform_release = platform_release;
+ platform_name(platform->plat_name, sizeof(platform->plat_name));
+
+ return 0;
+}
+
+/**
+ * @brief Local helper function to clean the slate for current platform.
+ **/
+static void hal_platform_clear(hal_platform* platform)
+{
+ assert(platform);
+ platform->inited = 0;
+}
+
+int hal_platform_init(hal_platform* platform)
+{
+ int state;
+ assert(platform && platform->platform_init);
+ hal_platform_clear(platform);
+
+ /* Initialise platform */
+ if (0 != (state = platform->platform_init())) {
+ printf_err("Failed to initialise platform %s\n", platform->plat_name);
+ return state;
+ }
+
+ /* Initialise the data acquisition module */
+ if (0 != (state = data_acq_channel_init(platform->data_acq))) {
+ if (!platform->data_acq->inited) {
+ printf_err("Failed to initialise data acq module: %s\n",
+ platform->data_acq->system_name);
+ }
+ hal_platform_release(platform);
+ return state;
+ }
+
+ /* Initialise the presentation module */
+ if (0 != (state = data_psn_system_init(platform->data_psn))) {
+ printf_err("Failed to initialise data psn module: %s\n",
+ platform->data_psn->system_name);
+ data_acq_channel_release(platform->data_acq);
+ hal_platform_release(platform);
+ return state;
+ }
+
+ /* Followed by the timer module */
+ init_timer(platform->timer);
+
+ info("%s platform initialised\n", platform->plat_name);
+ debug("Using %s module for data acquisition\n",
+ platform->data_acq->system_name);
+ debug("Using %s module for data presentation\n",
+ platform->data_psn->system_name);
+
+ platform->inited = !state;
+
+ return state;
+}
+
+void hal_platform_release(hal_platform *platform)
+{
+ assert(platform && platform->platform_release);
+ data_acq_channel_release(platform->data_acq);
+ data_psn_system_release(platform->data_psn);
+
+ hal_platform_clear(platform);
+ info("Releasing platform %s\n", platform->plat_name);
+ platform->platform_release();
+}
diff --git a/source/hal/source/platform/mps3/CMakeLists.txt b/source/hal/source/platform/mps3/CMakeLists.txt
new file mode 100644
index 0000000..8bd51dc
--- /dev/null
+++ b/source/hal/source/platform/mps3/CMakeLists.txt
@@ -0,0 +1,138 @@
+#----------------------------------------------------------------------------
+# Copyright (c) 2022 Arm Limited. All rights reserved.
+# SPDX-License-Identifier: Apache-2.0
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#----------------------------------------------------------------------------
+
+#########################################################
+# MPS3 platform support library #
+#########################################################
+
+cmake_minimum_required(VERSION 3.15.6)
+set(PLATFORM_DRIVERS_TARGET platform_drivers)
+project(${PLATFORM_DRIVERS_TARGET}
+ DESCRIPTION "Platform drivers library for MPS3 FPGA/FVP targets"
+ LANGUAGES C CXX ASM)
+
+# 1. We should be cross-compiling (MPS3 taregt only runs Cortex-M targets)
+if (NOT ${CMAKE_CROSSCOMPILING})
+ message(FATAL_ERROR "No ${PLATFORM_DRIVERS_TARGET} support for this target.")
+endif()
+
+# 2. Set the platform cmake descriptor file
+if (NOT DEFINED PLATFORM_CMAKE_DESCRIPTOR_FILE)
+ set(PLATFORM_CMAKE_DESCRIPTOR_FILE
+ cmake/subsystem-profiles/${TARGET_SUBSYSTEM}.cmake
+ CACHE PATH
+ "Platform's CMake descriptor file path")
+endif()
+
+## Include the platform cmake descriptor file
+include(${PLATFORM_CMAKE_DESCRIPTOR_FILE})
+
+# Define target specific base addresses here (before adding the components)
+if (TARGET_SUBSYSTEM STREQUAL sse-300)
+ set(UART0_BASE "0x49303000" CACHE STRING "UART base address")
+ set(UART0_BAUDRATE "115200" CACHE STRING "UART baudrate")
+ set(SYSTEM_CORE_CLOCK "25000000" CACHE STRING "System peripheral clock (Hz)")
+ set(CLCD_CONFIG_BASE "0x4930A000" CACHE STRING "LCD configuration base address")
+endif()
+
+# 3. Generate sources:
+if (NOT DEFINED SOURCE_GEN_DIR)
+ set(SOURCE_GEN_DIR ${CMAKE_BINARY_DIR}/generated/bsp)
+endif()
+
+set(MEM_PROFILE_TEMPLATE ${CMAKE_CURRENT_SOURCE_DIR}/cmake/templates/peripheral_memmap.h.template)
+set(IRQ_PROFILE_TEMPLATE ${CMAKE_CURRENT_SOURCE_DIR}/cmake/templates/peripheral_irqs.h.template)
+set(MEM_REGIONS_TEMPLATE ${CMAKE_CURRENT_SOURCE_DIR}/cmake/templates/mem_regions.h.template)
+
+configure_file("${MEM_PROFILE_TEMPLATE}" "${SOURCE_GEN_DIR}/peripheral_memmap.h")
+configure_file("${IRQ_PROFILE_TEMPLATE}" "${SOURCE_GEN_DIR}/peripheral_irqs.h")
+configure_file("${MEM_REGIONS_TEMPLATE}" "${SOURCE_GEN_DIR}/mem_regions.h")
+
+# Create static library
+add_library(${PLATFORM_DRIVERS_TARGET} STATIC)
+
+## Include directories - private
+target_include_directories(${PLATFORM_DRIVERS_TARGET}
+ PRIVATE
+ source)
+
+## Include directories - public
+target_include_directories(${PLATFORM_DRIVERS_TARGET}
+ PUBLIC
+ include
+ ${SOURCE_GEN_DIR})
+
+## Platform sources
+target_sources(${PLATFORM_DRIVERS_TARGET}
+ PRIVATE
+ source/timer_mps3.c
+ source/platform_drivers.c)
+
+## Compile definitions
+target_compile_definitions(${PLATFORM_DRIVERS_TARGET}
+ PUBLIC
+ ACTIVATION_BUF_SRAM_SZ=${ACTIVATION_BUF_SRAM_SZ})
+
+## Directory for additional components required by MPS3:
+if (NOT DEFINED COMPONENTS_DIR)
+ set(COMPONENTS_DIR ${CMAKE_CURRENT_SOURCE_DIR}/../../components)
+endif()
+
+## Platform component: cmsis_device (provides generic Cortex-M start up library)
+add_subdirectory(${COMPONENTS_DIR}/cmsis_device ${CMAKE_BINARY_DIR}/cmsis_device)
+
+## Platform component: stdout
+set(STDOUT_RETARGET ON CACHE BOOL "Retarget stdout/err to UART")
+add_subdirectory(${COMPONENTS_DIR}/stdout ${CMAKE_BINARY_DIR}/stdout)
+
+## Platform component: lcd
+add_subdirectory(${COMPONENTS_DIR}/lcd ${CMAKE_BINARY_DIR}/lcd)
+
+# Add dependencies:
+target_link_libraries(${PLATFORM_DRIVERS_TARGET} PUBLIC
+ log
+ cmsis_device
+ lcd_mps3
+ $<IF:$<BOOL:STDOUT_RETARGET>,stdout_retarget_cmsdk,stdout>)
+
+# If Ethos-U is enabled, we need the driver library too
+if (ETHOS_U_NPU_ENABLED)
+
+ ## Platform component: Ethos-U initialization
+ add_subdirectory(${COMPONENTS_DIR}/npu ${CMAKE_BINARY_DIR}/npu)
+
+ target_link_libraries(${PLATFORM_DRIVERS_TARGET}
+ PUBLIC
+ ethos_u_npu)
+
+ if (ETHOS_U_NPU_TIMING_ADAPTER_ENABLED)
+ ## Platform component: Ethos-U timing adapter initialization
+ add_subdirectory(${COMPONENTS_DIR}/npu_ta ${CMAKE_BINARY_DIR}/npu_ta)
+
+ target_link_libraries(${PLATFORM_DRIVERS_TARGET}
+ PUBLIC
+ ethos_u_ta)
+ endif()
+
+endif()
+
+# 5. Display status:
+message(STATUS "CMAKE_CURRENT_SOURCE_DIR: " ${CMAKE_CURRENT_SOURCE_DIR})
+message(STATUS "*******************************************************")
+message(STATUS "Library : " ${PLATFORM_DRIVERS_TARGET})
+message(STATUS "CMAKE_SYSTEM_PROCESSOR : " ${CMAKE_SYSTEM_PROCESSOR})
+message(STATUS "*******************************************************")
diff --git a/source/hal/source/platform/mps3/cmake/subsystem-profiles/sse-300.cmake b/source/hal/source/platform/mps3/cmake/subsystem-profiles/sse-300.cmake
new file mode 100644
index 0000000..eec6fde
--- /dev/null
+++ b/source/hal/source/platform/mps3/cmake/subsystem-profiles/sse-300.cmake
@@ -0,0 +1,319 @@
+#----------------------------------------------------------------------------
+# Copyright (c) 2021 Arm Limited. All rights reserved.
+# SPDX-License-Identifier: Apache-2.0
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#----------------------------------------------------------------------------
+
+# CMake configuration file for peripheral memory map for MPS3 as per SSE-300 design
+###################################################################################################
+# Mem sizes #
+###################################################################################################
+set(ITCM_SIZE "0x00080000" CACHE STRING "ITCM size: 512 kiB")
+set(DTCM_BLK_SIZE "0x00020000" CACHE STRING "DTCM size: 128 kiB, 4 banks")
+set(BRAM_SIZE "0x00100000" CACHE STRING "BRAM size: 1 MiB")
+set(ISRAM0_SIZE "0x00100000" CACHE STRING "ISRAM0 size: 1 MiB")
+set(ISRAM1_SIZE "0x00100000" CACHE STRING "ISRAM1 size: 1 MiB")
+set(QSPI_SRAM_SIZE "0x00800000" CACHE STRING "QSPI Flash size: 8 MiB")
+set(DDR4_BLK_SIZE "0x10000000" CACHE STRING "DDR4 block size: 256 MiB")
+
+###################################################################################################
+# Base addresses for memory regions #
+###################################################################################################
+set(ITCM_BASE_NS "0x00000000" CACHE STRING "Instruction TCM Non-Secure base address")
+set(BRAM_BASE_NS "0x01000000" CACHE STRING "CODE SRAM Non-Secure base address")
+set(DTCM0_BASE_NS "0x20000000" CACHE STRING "Data TCM block 0 Non-Secure base address")
+set(DTCM1_BASE_NS "0x20020000" CACHE STRING "Data TCM block 1 Non-Secure base address")
+set(DTCM2_BASE_NS "0x20040000" CACHE STRING "Data TCM block 2 Non-Secure base address")
+set(DTCM3_BASE_NS "0x20060000" CACHE STRING "Data TCM block 3 Non-Secure base address")
+set(ISRAM0_BASE_NS "0x21000000" CACHE STRING "Internal SRAM Area Non-Secure base address")
+set(ISRAM1_BASE_NS "0x21100000" CACHE STRING "Internal SRAM Area Non-Secure base address")
+set(QSPI_SRAM_BASE_NS "0x28000000" CACHE STRING "QSPI SRAM Non-Secure base address")
+set(DDR4_BLK0_BASE_NS "0x60000000" CACHE STRING "DDR4 block 0 Non-Secure base address")
+set(DDR4_BLK1_BASE_NS "0x80000000" CACHE STRING "DDR4 block 1 Non-Secure base address")
+set(DDR4_BLK2_BASE_NS "0xA0000000" CACHE STRING "DDR4 block 2 Non-Secure base address")
+set(DDR4_BLK3_BASE_NS "0xC0000000" CACHE STRING "DDR4 block 3 Non-Secure base address")
+
+set(ITCM_BASE_S "0x10000000" CACHE STRING "Instruction TCM Secure base address")
+set(BRAM_BASE_S "0x11000000" CACHE STRING "CODE SRAM Secure base address")
+set(DTCM0_BASE_S "0x30000000" CACHE STRING "Data TCM block 0 Secure base address")
+set(DTCM1_BASE_S "0x30020000" CACHE STRING "Data TCM block 1 Secure base address")
+set(DTCM2_BASE_S "0x30040000" CACHE STRING "Data TCM block 2 Secure base address")
+set(DTCM3_BASE_S "0x30060000" CACHE STRING "Data TCM block 3 Secure base address")
+set(ISRAM0_BASE_S "0x31000000" CACHE STRING "Internal SRAM Area Secure base address")
+set(ISRAM1_BASE_S "0x31100000" CACHE STRING "Internal SRAM Area Secure base address")
+set(QSPI_SRAM_BASE_S "0x38000000" CACHE STRING "QSPI SRAM Non-Secure base address")
+set(DDR4_BLK0_BASE_S "0x70000000" CACHE STRING "DDR4 block 0 Secure base address")
+set(DDR4_BLK1_BASE_S "0x90000000" CACHE STRING "DDR4 block 1 Secure base address")
+set(DDR4_BLK2_BASE_S "0xB0000000" CACHE STRING "DDR4 block 2 Secure base address")
+set(DDR4_BLK3_BASE_S "0xD0000000" CACHE STRING "DDR4 block 3 Secure base address")
+
+###################################################################################################
+# Application specific config #
+###################################################################################################
+set(APP_NOTE "AN552")
+set(DESIGN_NAME "Arm Corstone-300 - ${APP_NOTE}" CACHE STRING "Design name")
+
+# The following parameter is based on the linker/scatter script for SSE-300.
+# Do not change this parameter in isolation.
+# SRAM size reserved for activation buffers
+math(EXPR ACTIVATION_BUF_SRAM_SZ "${ISRAM0_SIZE} + ${ISRAM1_SIZE}" OUTPUT_FORMAT HEXADECIMAL)
+
+###################################################################################################
+# Base addresses for dynamic loads (to be used for FVP form only) #
+###################################################################################################
+# This parameter is also mentioned in the linker/scatter script for SSE-300. Do not change these
+# parameters in isolation.
+set(DYNAMIC_MODEL_BASE "${DDR4_BLK1_BASE_S}" CACHE STRING
+ "Region to be used for dynamic load of model into memory")
+set(DYNAMIC_MODEL_SIZE "0x02000000" CACHE STRING "Size of the space reserved for the model")
+math(EXPR DYNAMIC_IFM_BASE "${DYNAMIC_MODEL_BASE} + ${DYNAMIC_MODEL_SIZE}" OUTPUT_FORMAT HEXADECIMAL)
+set(DYNAMIC_IFM_SIZE "0x01000000" CACHE STRING "Size of the space reserved for the IFM")
+math(EXPR DYNAMIC_OFM_BASE "${DYNAMIC_IFM_BASE} + ${DYNAMIC_IFM_SIZE}" OUTPUT_FORMAT HEXADECIMAL)
+set(DYNAMIC_OFM_SIZE "0x01000000" CACHE STRING "Size of the space reserved for the OFM")
+
+###################################################################################################
+# Base addresses for peripherals - non secure #
+###################################################################################################
+set(CMSDK_GPIO0_BASE "0x41100000" CACHE STRING "User GPIO 0 Base Address (4KB)")
+set(CMSDK_GPIO1_BASE "0x41101000" CACHE STRING "User GPIO 1 Base Address (4KB)")
+set(CMSDK_GPIO2_BASE "0x41102000" CACHE STRING "User GPIO 2 Base Address (4KB)")
+set(CMSDK_GPIO3_BASE "0x41103000" CACHE STRING "User GPIO 3 Base Address (4KB)")
+set(FMC_CMDSK_GPIO_BASE0 "0x41104000" CACHE STRING "FMC CMDSK GPIO 0 Base Address (4KB)")
+set(FMC_CMDSK_GPIO_BASE1 "0x41105000" CACHE STRING "FMC CMDSK GPIO 1 Base Address (4KB)")
+set(FMC_CMDSK_GPIO_BASE2 "0x41106000" CACHE STRING "FMC CMDSK GPIO 2 Base Address (4KB)")
+set(FMC_USER_AHB_BASE "0x41107000" CACHE STRING "FMC USER AHB Base Address (4KB)")
+set(DMA0_BASE "0x41200000" CACHE STRING "DMA0 ExternalManager0 (4KB)")
+set(DMA1_BASE "0x41201000" CACHE STRING "DMA1 ExternalManager1 (4KB)")
+set(DMA2_BASE "0x41202000" CACHE STRING "DMA2 ExternalManager2 (4KB)")
+set(DMA3_BASE "0x41203000" CACHE STRING "DMA3 ExternalManager3 (4KB)")
+
+set(SMSC9220_BASE "0x41400000" CACHE STRING "Ethernet SMSC9220 Base Address (1MB)")
+set(USB_BASE "0x41500000" CACHE STRING "USB Base Address (1MB)")
+
+set(USER_APB0_BASE "0x41700000" CACHE STRING "User APB0")
+set(USER_APB1_BASE "0x41701000" CACHE STRING "User APB1")
+set(USER_APB2_BASE "0x41702000" CACHE STRING "User APB2")
+set(USER_APB3_BASE "0x41703000" CACHE STRING "User APB3")
+
+set(QSPI_XIP_BASE "0x41800000" CACHE STRING "QSPI XIP config Base Address ")
+set(QSPI_WRITE_BASE "0x41801000" CACHE STRING "QSPI write config Base Address ")
+
+if (ETHOS_U_NPU_ENABLED)
+ set(ETHOS_U_NPU_BASE "0x48102000" CACHE STRING "Ethos-U NPU base address")
+ set(ETHOS_U_NPU_TA0_BASE "0x48103000" CACHE STRING "Ethos-U NPU's timing adapter 0 base address")
+ set(ETHOS_U_NPU_TA1_BASE "0x48103200" CACHE STRING "Ethos-U NPU's timing adapter 1 base address")
+endif (ETHOS_U_NPU_ENABLED)
+
+set(MPS3_I2C0_BASE "0x49200000" CACHE STRING "Touch Screen I2C Base Address ")
+set(MPS3_I2C1_BASE "0x49201000" CACHE STRING "Audio Interface I2C Base Address ")
+set(MPS3_SSP2_BASE "0x49202000" CACHE STRING "ADC SPI PL022 Base Address")
+set(MPS3_SSP3_BASE "0x49203000" CACHE STRING "Shield 0 SPI PL022 Base Address")
+set(MPS3_SSP4_BASE "0x49204000" CACHE STRING "Shield 1 SPI PL022 Base Address")
+set(MPS3_I2C2_BASE "0x49205000" CACHE STRING "Shield 0 SBCon Base Address ")
+set(MPS3_I2C3_BASE "0x49206000" CACHE STRING "Shield 1 SBCon Base Address ")
+
+set(USER_APB_BASE "0x49207000" CACHE STRING "User APB")
+set(MPS3_I2C5_BASE "0x49208000" CACHE STRING "DDR EPROM I2C SBCon Base Address ")
+
+set(MPS3_SCC_BASE "0x49300000" CACHE STRING "SCC Base Address ")
+set(MPS3_AAIC_I2S_BASE "0x49301000" CACHE STRING "Audio Interface I2S Base Address ")
+set(MPS3_FPGAIO_BASE "0x49302000" CACHE STRING "FPGA IO Base Address ")
+
+set(CMSDK_UART0_BASE "0x49303000" CACHE STRING "UART 0 Base Address ")
+set(CMSDK_UART1_BASE "0x49304000" CACHE STRING "UART 1 Base Address ")
+set(CMSDK_UART2_BASE "0x49305000" CACHE STRING "UART 2 Base Address ")
+set(CMSDK_UART3_BASE "0x49306000" CACHE STRING "UART 3 Base Address Shield 0")
+set(CMSDK_UART4_BASE "0x49307000" CACHE STRING "UART 4 Base Address Shield 1")
+set(CMSDK_UART5_BASE "0x49308000" CACHE STRING "UART 5 Base Address ")
+
+set(CLCD_CONFIG_BASE "0x4930A000" CACHE STRING "CLCD CONFIG Base Address ")
+set(RTC_BASE "0x4930B000" CACHE STRING "RTC Base address ")
+
+###################################################################################################
+# Base addresses for peripherals - secure #
+###################################################################################################
+set(SEC_CMSDK_GPIO0_BASE "0x51100000" CACHE STRING "User GPIO 0 Base Address (4KB)")
+set(SEC_CMSDK_GPIO1_BASE "0x51101000" CACHE STRING "User GPIO 1 Base Address (4KB)")
+set(SEC_CMSDK_GPIO2_BASE "0x51102000" CACHE STRING "User GPIO 2 Base Address (4KB)")
+set(SEC_CMSDK_GPIO3_BASE "0x51103000" CACHE STRING "User GPIO 3 Base Address (4KB)")
+
+set(SEC_AHB_USER0_BASE "0x51104000" CACHE STRING "AHB USER 0 Base Address (4KB)")
+set(SEC_AHB_USER1_BASE "0x51105000" CACHE STRING "AHB USER 1 Base Address (4KB)")
+set(SEC_AHB_USER2_BASE "0x51106000" CACHE STRING "AHB USER 2 Base Address (4KB)")
+set(SEC_AHB_USER3_BASE "0x51107000" CACHE STRING "AHB USER 3 Base Address (4KB)")
+
+set(SEC_DMA0_BASE "0x51200000" CACHE STRING "DMA0 ExternalManager0 (4KB)")
+set(SEC_DMA1_BASE "0x51201000" CACHE STRING "DMA1 ExternalManager1 (4KB)")
+set(SEC_DMA2_BASE "0x51202000" CACHE STRING "DMA2 ExternalManager2 (4KB)")
+set(SEC_DMA3_BASE "0x51203000" CACHE STRING "DMA3 ExternalManager3 (4KB)")
+
+set(SEC_SMSC9220_BASE "0x51400000" CACHE STRING "Ethernet SMSC9220 Base Address (1MB)")
+set(SEC_USB_BASE "0x51500000" CACHE STRING "USB Base Address (1MB)")
+
+set(SEC_USER_APB0_BASE "0x51700000" CACHE STRING "User APB0 Base Address")
+set(SEC_USER_APB1_BASE "0x51701000" CACHE STRING "User APB1 Base Address")
+set(SEC_USER_APB2_BASE "0x51702000" CACHE STRING "User APB2 Base Address")
+set(SEC_USER_APB3_BASE "0x51703000" CACHE STRING "User APB3 Base Address")
+
+set(SEC_QSPI_XIP_BASE "0x51800000" CACHE STRING "QSPI XIP config Base Address ")
+set(SEC_QSPI_WRITE_BASE "0x51801000" CACHE STRING "QSPI write config Base Address ")
+
+if (ETHOS_U_NPU_ENABLED)
+ set(SEC_ETHOS_U_NPU_BASE "0x58102000" CACHE STRING "Ethos-U NPU base address")
+ set(SEC_ETHOS_U_NPU_TA0_BASE "0x58103000" CACHE STRING "Ethos-U NPU's timing adapter 0 base address")
+ set(SEC_ETHOS_U_NPU_TA1_BASE "0x58103200" CACHE STRING "Ethos-U NPU's timing adapter 1 base address")
+endif (ETHOS_U_NPU_ENABLED)
+
+set(SEC_MPS3_I2C0_BASE "0x59200000" CACHE STRING "Touch Screen I2C Base Address ")
+set(SEC_MPS3_I2C1_BASE "0x59201000" CACHE STRING "Audio Interface I2C Base Address ")
+set(SEC_MPS3_SSP2_BASE "0x59202000" CACHE STRING "ADC SPI PL022 Base Address")
+set(SEC_MPS3_SSP3_BASE "0x59203000" CACHE STRING "Shield 0 SPI PL022 Base Address")
+set(SEC_MPS3_SSP4_BASE "0x59204000" CACHE STRING "Shield 1 SPI PL022 Base Address")
+set(SEC_MPS3_I2C2_BASE "0x59205000" CACHE STRING "Shield 0 SBCon Base Address ")
+set(SEC_MPS3_I2C3_BASE "0x59206000" CACHE STRING "Shield 1 SBCon Base Address ")
+set(SEC_USER_APB_BASE "0x59207000" CACHE STRING "User APB Base Address")
+set(SEC_MPS3_I2C5_BASE "0x59208000" CACHE STRING "DDR EPROM I2C SBCon Base Address ")
+
+set(SEC_MPS3_SCC_BASE "0x59300000" CACHE STRING "SCC Base Address ")
+set(SEC_MPS3_AAIC_I2S_BASE "0x59301000" CACHE STRING "Audio Interface I2S Base Address ")
+set(SEC_MPS3_FPGAIO_BASE "0x59302000" CACHE STRING "FPGA IO Base Address ")
+
+set(SEC_CMSDK_UART0_BASE "0x59303000" CACHE STRING "UART 0 Base Address ")
+set(SEC_CMSDK_UART1_BASE "0x59304000" CACHE STRING "UART 1 Base Address ")
+set(SEC_CMSDK_UART2_BASE "0x59305000" CACHE STRING "UART 2 Base Address ")
+set(SEC_CMSDK_UART3_BASE "0x59306000" CACHE STRING "UART 3 Base Address Shield 0")
+set(SEC_CMSDK_UART4_BASE "0x59307000" CACHE STRING "UART 4 Base Address Shield 1")
+set(SEC_CMSDK_UART5_BASE "0x59308000" CACHE STRING "UART 5 Base Address ")
+
+set(SEC_CLCD_CONFIG_BASE "0x5930A000" CACHE STRING "CLCD CONFIG Base Address ")
+set(SEC_RTC_BASE "0x5930B000" CACHE STRING "RTC Base address ")
+
+###################################################################################################
+# MPCs #
+###################################################################################################
+set(MPC_ISRAM0_BASE_S "0x50083000" CACHE STRING "ISRAM0 Memory Protection Controller Secure base address")
+set(MPC_ISRAM1_BASE_S "0x50084000" CACHE STRING "ISRAM1 Memory Protection Controller Secure base address")
+set(MPC_BRAM_BASE_S "0x57000000" CACHE STRING "SRAM Memory Protection Controller Secure base address")
+set(MPC_QSPI_BASE_S "0x57001000" CACHE STRING "QSPI Memory Protection Controller Secure base address")
+set(MPC_DDR4_BASE_S "0x57002000" CACHE STRING "DDR4 Memory Protection Controller Secure base address")
+
+###################################################################################################
+# IRQ numbers #
+###################################################################################################
+set(NONSEC_WATCHDOG_RESET_IRQn " 0" CACHE STRING " Non-Secure Watchdog Reset Interrupt")
+set(NONSEC_WATCHDOG_IRQn " 1" CACHE STRING " Non-Secure Watchdog Interrupt ")
+set(S32K_TIMER_IRQn " 2" CACHE STRING " S32K SLOWCLK Timer Interrupt ")
+set(TIMER0_IRQn " 3" CACHE STRING " TIMER 0 Interrupt ")
+set(TIMER1_IRQn " 4" CACHE STRING " TIMER 1 Interrupt ")
+set(TIMER2_IRQn " 5" CACHE STRING " TIMER 2 Interrupt ")
+set(MPC_IRQn " 9" CACHE STRING " MPC Combined (Secure) Interrupt ")
+set(PPC_IRQn "10" CACHE STRING " PPC Combined (Secure) Interrupt ")
+set(MSC_IRQn "11" CACHE STRING " MSC Combined (Secure) Interrput ")
+set(BRIDGE_ERROR_IRQn "12" CACHE STRING " Bridge Error Combined (Secure) Interrupt ")
+set(MGMT_PPU_IRQn "14" CACHE STRING " MGMT_PPU" )
+set(SYS_PPU_IRQn "15" CACHE STRING " SYS_PPU" )
+set(CPU0_PPU_IRQn "16" CACHE STRING " CPU0_PPU" )
+set(DEBUG_PPU_IRQn "26" CACHE STRING " DEBUG_PPU" )
+set(TIMER3_AON_IRQn "27" CACHE STRING " TIMER3_AON" )
+set(CPU0CTIIQ0_IRQn "28" CACHE STRING " CPU0CTIIQ0" )
+set(CPU0CTIIQ01_IRQn "29" CACHE STRING " CPU0CTIIQ01" )
+
+set(SYS_TSTAMP_COUNTER_IRQn "32" CACHE STRING " System timestamp counter interrupt ")
+set(UARTRX0_IRQn "33" CACHE STRING " UART 0 RX Interrupt ")
+set(UARTTX0_IRQn "34" CACHE STRING " UART 0 TX Interrupt ")
+set(UARTRX1_IRQn "35" CACHE STRING " UART 1 RX Interrupt ")
+set(UARTTX1_IRQn "36" CACHE STRING " UART 1 TX Interrupt ")
+set(UARTRX2_IRQn "37" CACHE STRING " UART 2 RX Interrupt ")
+set(UARTTX2_IRQn "38" CACHE STRING " UART 2 TX Interrupt ")
+set(UARTRX3_IRQn "39" CACHE STRING " UART 3 RX Interrupt ")
+set(UARTTX3_IRQn "40" CACHE STRING " UART 3 TX Interrupt ")
+set(UARTRX4_IRQn "41" CACHE STRING " UART 4 RX Interrupt ")
+set(UARTTX4_IRQn "42" CACHE STRING " UART 4 TX Interrupt ")
+set(UART0_IRQn "43" CACHE STRING " UART 0 combined Interrupt ")
+set(UART1_IRQn "44" CACHE STRING " UART 1 combined Interrupt ")
+set(UART2_IRQn "45" CACHE STRING " UART 2 combined Interrupt ")
+set(UART3_IRQn "46" CACHE STRING " UART 3 combined Interrupt ")
+set(UART4_IRQn "47" CACHE STRING " UART 4 combined Interrupt ")
+set(UARTOVF_IRQn "48" CACHE STRING " UART 0,1,2,3,4 Overflow Interrupt ")
+set(ETHERNET_IRQn "49" CACHE STRING " Ethernet Interrupt ")
+set(I2S_IRQn "50" CACHE STRING " Audio I2S Interrupt ")
+set(TSC_IRQn "51" CACHE STRING " Touch Screen Interrupt ")
+set(USB_IRQn "52" CACHE STRING " USB Interrupt ")
+set(SPI2_IRQn "53" CACHE STRING " ADC (SPI) Interrupt ")
+set(SPI3_IRQn "54" CACHE STRING " SPI 3 Interrupt (Shield 0) ")
+set(SPI4_IRQn "55" CACHE STRING " SPI 4 Interrupt (Sheild 1) ")
+
+if (ETHOS_U_NPU_ENABLED)
+set(EthosU_IRQn "56" CACHE STRING " Ethos-U55 Interrupt ")
+endif ()
+
+set(GPIO0_IRQn "69" CACHE STRING " GPIO 0 Combined Interrupt ")
+set(GPIO1_IRQn "70" CACHE STRING " GPIO 1 Combined Interrupt ")
+set(GPIO2_IRQn "71" CACHE STRING " GPIO 2 Combined Interrupt ")
+set(GPIO3_IRQn "72" CACHE STRING " GPIO 3 Combined Interrupt ")
+set(GPIO0_0_IRQn "73" CACHE STRING "")
+set(GPIO0_1_IRQn "74" CACHE STRING "")
+set(GPIO0_2_IRQn "75" CACHE STRING "")
+set(GPIO0_3_IRQn "76" CACHE STRING "")
+set(GPIO0_4_IRQn "77" CACHE STRING "")
+set(GPIO0_5_IRQn "78" CACHE STRING "")
+set(GPIO0_6_IRQn "79" CACHE STRING "")
+set(GPIO0_7_IRQn "80" CACHE STRING "")
+set(GPIO0_8_IRQn "81" CACHE STRING "")
+set(GPIO0_9_IRQn "82" CACHE STRING "")
+set(GPIO0_10_IRQn "83" CACHE STRING "")
+set(GPIO0_11_IRQn "84" CACHE STRING "")
+set(GPIO0_12_IRQn "85" CACHE STRING "")
+set(GPIO0_13_IRQn "86" CACHE STRING "")
+set(GPIO0_14_IRQn "87" CACHE STRING "")
+set(GPIO0_15_IRQn "88" CACHE STRING "")
+set(GPIO1_0_IRQn "89" CACHE STRING "")
+set(GPIO1_1_IRQn "90" CACHE STRING "")
+set(GPIO1_2_IRQn "91" CACHE STRING "")
+set(GPIO1_3_IRQn "92" CACHE STRING "")
+set(GPIO1_4_IRQn "93" CACHE STRING "")
+set(GPIO1_5_IRQn "94" CACHE STRING "")
+set(GPIO1_6_IRQn "95" CACHE STRING "")
+set(GPIO1_7_IRQn "96" CACHE STRING "")
+set(GPIO1_8_IRQn "97" CACHE STRING "")
+set(GPIO1_9_IRQn "98" CACHE STRING "")
+set(GPIO1_10_IRQn "99" CACHE STRING "")
+set(GPIO1_11_IRQn "100" CACHE STRING "")
+set(GPIO1_12_IRQn "101" CACHE STRING "")
+set(GPIO1_13_IRQn "102" CACHE STRING "")
+set(GPIO1_14_IRQn "103" CACHE STRING "")
+set(GPIO1_15_IRQn "104" CACHE STRING "")
+set(GPIO2_0_IRQn "105" CACHE STRING "")
+set(GPIO2_1_IRQn "106" CACHE STRING "")
+set(GPIO2_2_IRQn "107" CACHE STRING "")
+set(GPIO2_3_IRQn "108" CACHE STRING "")
+set(GPIO2_4_IRQn "109" CACHE STRING "")
+set(GPIO2_5_IRQn "110" CACHE STRING "")
+set(GPIO2_6_IRQn "111" CACHE STRING "")
+set(GPIO2_7_IRQn "112" CACHE STRING "")
+set(GPIO2_8_IRQn "113" CACHE STRING "")
+set(GPIO2_9_IRQn "114" CACHE STRING "")
+set(GPIO2_10_IRQn "115" CACHE STRING "")
+set(GPIO2_11_IRQn "116" CACHE STRING "")
+set(GPIO2_12_IRQn "117" CACHE STRING "")
+set(GPIO2_13_IRQn "118" CACHE STRING "")
+set(GPIO2_14_IRQn "119" CACHE STRING "")
+set(GPIO2_15_IRQn "120" CACHE STRING "")
+set(GPIO3_0_IRQn "121" CACHE STRING "")
+set(GPIO3_1_IRQn "122" CACHE STRING "")
+set(GPIO3_2_IRQn "123" CACHE STRING "")
+set(GPIO3_3_IRQn "124" CACHE STRING "")
+set(UARTRX5_IRQn "125" CACHE STRING "UART 5 RX Interrupt")
+set(UARTTX5_IRQn "126" CACHE STRING "UART 5 TX Interrupt")
+set(UART5_IRQn "127" CACHE STRING "UART 5 combined Interrupt")
diff --git a/source/hal/source/platform/mps3/cmake/templates/mem_regions.h.template b/source/hal/source/platform/mps3/cmake/templates/mem_regions.h.template
new file mode 100644
index 0000000..72978ce
--- /dev/null
+++ b/source/hal/source/platform/mps3/cmake/templates/mem_regions.h.template
@@ -0,0 +1,58 @@
+/*
+ * Copyright (c) 2021 Arm Limited. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+// Auto-generated file
+// ** DO NOT EDIT **
+
+#ifndef MEM_REGION_DEFS_H
+#define MEM_REGION_DEFS_H
+
+#cmakedefine ITCM_SIZE (@ITCM_SIZE@) /* ITCM size */
+#cmakedefine DTCM_BLK_SIZE (@DTCM_BLK_SIZE@) /* DTCM size, 4 banks of this size available */
+#cmakedefine BRAM_SIZE (@BRAM_SIZE@) /* BRAM size */
+#cmakedefine ISRAM0_SIZE (@ISRAM0_SIZE@) /* ISRAM0 size */
+#cmakedefine ISRAM1_SIZE (@ISRAM1_SIZE@) /* ISRAM1 size */
+#cmakedefine QSPI_SRAM_SIZE (@QSPI_SRAM_SIZE@) /* QSPI Flash size */
+#cmakedefine DDR4_BLK_SIZE (@DDR4_BLK_SIZE@) /* DDR4 block size */
+
+#cmakedefine ITCM_BASE_NS (@ITCM_BASE_NS@) /* Instruction TCM Non-Secure base address */
+#cmakedefine BRAM_BASE_NS (@BRAM_BASE_NS@) /* CODE SRAM Non-Secure base address */
+#cmakedefine DTCM0_BASE_NS (@DTCM0_BASE_NS@) /* Data TCM block 0 Non-Secure base address */
+#cmakedefine DTCM1_BASE_NS (@DTCM1_BASE_NS@) /* Data TCM block 1 Non-Secure base address */
+#cmakedefine DTCM2_BASE_NS (@DTCM2_BASE_NS@) /* Data TCM block 2 Non-Secure base address */
+#cmakedefine DTCM3_BASE_NS (@DTCM3_BASE_NS@) /* Data TCM block 3 Non-Secure base address */
+#cmakedefine ISRAM0_BASE_NS (@ISRAM0_BASE_NS@) /* Internal SRAM Area Non-Secure base address */
+#cmakedefine ISRAM1_BASE_NS (@ISRAM1_BASE_NS@) /* Internal SRAM Area Non-Secure base address */
+#cmakedefine QSPI_SRAM_BASE_NS (@QSPI_SRAM_BASE_NS@) /* QSPI SRAM Non-Secure base address */
+#cmakedefine DDR4_BLK0_BASE_NS (@DDR4_BLK0_BASE_NS@) /* DDR4 block 0 Non-Secure base address */
+#cmakedefine DDR4_BLK1_BASE_NS (@DDR4_BLK1_BASE_NS@) /* DDR4 block 1 Non-Secure base address */
+#cmakedefine DDR4_BLK2_BASE_NS (@DDR4_BLK2_BASE_NS@) /* DDR4 block 2 Non-Secure base address */
+#cmakedefine DDR4_BLK3_BASE_NS (@DDR4_BLK3_BASE_NS@) /* DDR4 block 3 Non-Secure base address */
+
+#cmakedefine ITCM_BASE_S (@ITCM_BASE_S@) /* Instruction TCM Secure base address */
+#cmakedefine BRAM_BASE_S (@BRAM_BASE_S@) /* CODE SRAM Secure base address */
+#cmakedefine DTCM0_BASE_S (@DTCM0_BASE_S@) /* Data TCM block 0 Secure base address */
+#cmakedefine DTCM1_BASE_S (@DTCM1_BASE_S@) /* Data TCM block 1 Secure base address */
+#cmakedefine DTCM2_BASE_S (@DTCM2_BASE_S@) /* Data TCM block 2 Secure base address */
+#cmakedefine DTCM3_BASE_S (@DTCM3_BASE_S@) /* Data TCM block 3 Secure base address */
+#cmakedefine ISRAM0_BASE_S (@ISRAM0_BASE_S@) /* Internal SRAM Area Secure base address */
+#cmakedefine ISRAM1_BASE_S (@ISRAM1_BASE_S@) /* Internal SRAM Area Secure base address */
+#cmakedefine DDR4_BLK0_BASE_S (@DDR4_BLK0_BASE_S@) /* DDR4 block 0 Secure base address */
+#cmakedefine DDR4_BLK1_BASE_S (@DDR4_BLK1_BASE_S@) /* DDR4 block 1 Secure base address */
+#cmakedefine DDR4_BLK2_BASE_S (@DDR4_BLK2_BASE_S@) /* DDR4 block 2 Secure base address */
+#cmakedefine DDR4_BLK3_BASE_S (@DDR4_BLK3_BASE_S@) /* DDR4 block 3 Secure base address */
+
+#endif /* MEM_REGION_DEFS_H */
diff --git a/source/hal/source/platform/mps3/cmake/templates/peripheral_irqs.h.template b/source/hal/source/platform/mps3/cmake/templates/peripheral_irqs.h.template
new file mode 100644
index 0000000..7696e13
--- /dev/null
+++ b/source/hal/source/platform/mps3/cmake/templates/peripheral_irqs.h.template
@@ -0,0 +1,138 @@
+/*
+ * Copyright (c) 2021 Arm Limited. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+// Auto-generated file
+// ** DO NOT EDIT **
+
+#ifndef PERIPHERAL_IRQS_H
+#define PERIPHERAL_IRQS_H
+
+/******************************************************************************/
+/* Peripheral interrupt numbers */
+/******************************************************************************/
+
+/* ------------------- Cortex-M Processor Exceptions Numbers -------------- */
+/* -14 to -1 should be defined by the system header */
+/* ---------------------- Core Specific Interrupt Numbers ------------------*/
+#cmakedefine NONSEC_WATCHDOG_RESET_IRQn (@NONSEC_WATCHDOG_RESET_IRQn@) /* Non-Secure Watchdog Reset Interrupt */
+#cmakedefine NONSEC_WATCHDOG_IRQn (@NONSEC_WATCHDOG_IRQn@) /* Non-Secure Watchdog Interrupt */
+#cmakedefine S32K_TIMER_IRQn (@S32K_TIMER_IRQn@) /* S32K Timer Interrupt */
+#cmakedefine TIMER0_IRQn (@TIMER0_IRQn@) /* TIMER 0 Interrupt */
+#cmakedefine TIMER1_IRQn (@TIMER1_IRQn@) /* TIMER 1 Interrupt */
+#cmakedefine TIMER2_IRQn (@TIMER2_IRQn@) /* TIMER 2 Interrupt */
+#cmakedefine MPC_IRQn (@MPC_IRQn@) /* MPC Combined (@Secure@) Interrupt */
+#cmakedefine PPC_IRQn (@PPC_IRQn@) /* PPC Combined (@Secure@) Interrupt */
+#cmakedefine MSC_IRQn (@MSC_IRQn@) /* MSC Combined (@Secure@) Interrput */
+#cmakedefine BRIDGE_ERROR_IRQn (@BRIDGE_ERROR_IRQn@) /* Bridge Error Combined (@Secure@) Interrupt */
+#cmakedefine MGMT_PPU_IRQn (@MGMT_PPU_IRQn@) /* MGMT_PPU */
+#cmakedefine SYS_PPU_IRQn (@SYS_PPU_IRQn@) /* SYS_PPU */
+#cmakedefine CPU0_PPU_IRQn (@CPU0_PPU_IRQn@) /* CPU0_PPU */
+#cmakedefine DEBUG_PPU_IRQn (@DEBUG_PPU_IRQn@) /* DEBUG_PPU */
+#cmakedefine TIMER3_AON_IRQn (@TIMER3_AON_IRQn@) /* TIMER3_AON */
+#cmakedefine CPU0CTIIQ0_IRQn (@CPU0CTIIQ0_IRQn@) /* CPU0CTIIQ0 */
+#cmakedefine CPU0CTIIQ01_IRQn (@CPU0CTIIQ01_IRQn@) /* CPU0CTIIQ01 */
+
+#cmakedefine SYS_TSTAMP_COUNTER_IRQn (@SYS_TSTAMP_COUNTER_IRQn@) /* System timestamp counter interrupt */
+
+/* ---------------------- CMSDK Specific Interrupt Numbers ----------------- */
+#cmakedefine UARTRX0_IRQn (@UARTRX0_IRQn@) /* UART 0 RX Interrupt */
+#cmakedefine UARTTX0_IRQn (@UARTTX0_IRQn@) /* UART 0 TX Interrupt */
+#cmakedefine UARTRX1_IRQn (@UARTRX1_IRQn@) /* UART 1 RX Interrupt */
+#cmakedefine UARTTX1_IRQn (@UARTTX1_IRQn@) /* UART 1 TX Interrupt */
+#cmakedefine UARTRX2_IRQn (@UARTRX2_IRQn@) /* UART 2 RX Interrupt */
+#cmakedefine UARTTX2_IRQn (@UARTTX2_IRQn@) /* UART 2 TX Interrupt */
+#cmakedefine UARTRX3_IRQn (@UARTRX3_IRQn@) /* UART 3 RX Interrupt */
+#cmakedefine UARTTX3_IRQn (@UARTTX3_IRQn@) /* UART 3 TX Interrupt */
+#cmakedefine UARTRX4_IRQn (@UARTRX4_IRQn@) /* UART 4 RX Interrupt */
+#cmakedefine UARTTX4_IRQn (@UARTTX4_IRQn@) /* UART 4 TX Interrupt */
+#cmakedefine UART0_IRQn (@UART0_IRQn@) /* UART 0 combined Interrupt */
+#cmakedefine UART1_IRQn (@UART1_IRQn@) /* UART 1 combined Interrupt */
+#cmakedefine UART2_IRQn (@UART2_IRQn@) /* UART 2 combined Interrupt */
+#cmakedefine UART3_IRQn (@UART3_IRQn@) /* UART 3 combined Interrupt */
+#cmakedefine UART4_IRQn (@UART4_IRQn@) /* UART 4 combined Interrupt */
+#cmakedefine UARTOVF_IRQn (@UARTOVF_IRQn@) /* UART 0,1,2,3 and 4 Overflow Interrupt */
+#cmakedefine ETHERNET_IRQn (@ETHERNET_IRQn@) /* Ethernet Interrupt */
+#cmakedefine I2S_IRQn (@I2S_IRQn@) /* I2S Interrupt */
+#cmakedefine TSC_IRQn (@TSC_IRQn@) /* Touch Screen Interrupt */
+#cmakedefine SPI2_IRQn (@SPI2_IRQn@) /* SPI 2 Interrupt */
+#cmakedefine SPI3_IRQn (@SPI3_IRQn@) /* SPI 3 Interrupt */
+#cmakedefine SPI4_IRQn (@SPI4_IRQn@) /* SPI 4 Interrupt */
+
+#cmakedefine EthosU_IRQn (@EthosU_IRQn@) /* Ethos-Uxx Interrupt */
+
+#cmakedefine GPIO0_IRQn (@GPIO0_IRQn@) /* GPIO 0 Combined Interrupt */
+#cmakedefine GPIO1_IRQn (@GPIO1_IRQn@) /* GPIO 1 Combined Interrupt */
+#cmakedefine GPIO2_IRQn (@GPIO2_IRQn@) /* GPIO 2 Combined Interrupt */
+#cmakedefine GPIO3_IRQn (@GPIO3_IRQn@) /* GPIO 3 Combined Interrupt */
+
+#cmakedefine GPIO0_0_IRQn (@GPIO0_0_IRQn@) /* All P0 I/O pins used as irq source */
+#cmakedefine GPIO0_1_IRQn (@GPIO0_1_IRQn@) /* There are 16 pins in total */
+#cmakedefine GPIO0_2_IRQn (@GPIO0_2_IRQn@)
+#cmakedefine GPIO0_3_IRQn (@GPIO0_3_IRQn@)
+#cmakedefine GPIO0_4_IRQn (@GPIO0_4_IRQn@)
+#cmakedefine GPIO0_5_IRQn (@GPIO0_5_IRQn@)
+#cmakedefine GPIO0_6_IRQn (@GPIO0_6_IRQn@)
+#cmakedefine GPIO0_7_IRQn (@GPIO0_7_IRQn@)
+#cmakedefine GPIO0_8_IRQn (@GPIO0_8_IRQn@)
+#cmakedefine GPIO0_9_IRQn (@GPIO0_9_IRQn@)
+#cmakedefine GPIO0_10_IRQn (@GPIO0_10_IRQn@)
+#cmakedefine GPIO0_11_IRQn (@GPIO0_11_IRQn@)
+#cmakedefine GPIO0_12_IRQn (@GPIO0_12_IRQn@)
+#cmakedefine GPIO0_13_IRQn (@GPIO0_13_IRQn@)
+#cmakedefine GPIO0_14_IRQn (@GPIO0_14_IRQn@)
+#cmakedefine GPIO0_15_IRQn (@GPIO0_15_IRQn@)
+#cmakedefine GPIO1_0_IRQn (@GPIO1_0_IRQn@) /* All P1 I/O pins used as irq source */
+#cmakedefine GPIO1_1_IRQn (@GPIO1_1_IRQn@) /* There are 16 pins in total */
+#cmakedefine GPIO1_2_IRQn (@GPIO1_2_IRQn@)
+#cmakedefine GPIO1_3_IRQn (@GPIO1_3_IRQn@)
+#cmakedefine GPIO1_4_IRQn (@GPIO1_4_IRQn@)
+#cmakedefine GPIO1_5_IRQn (@GPIO1_5_IRQn@)
+#cmakedefine GPIO1_6_IRQn (@GPIO1_6_IRQn@)
+#cmakedefine GPIO1_7_IRQn (@GPIO1_7_IRQn@)
+#cmakedefine GPIO1_8_IRQn (@GPIO1_8_IRQn@)
+#cmakedefine GPIO1_9_IRQn (@GPIO1_9_IRQn@)
+#cmakedefine GPIO1_10_IRQn (@GPIO1_10_IRQn@)
+#cmakedefine GPIO1_11_IRQn (@GPIO1_11_IRQn@)
+#cmakedefine GPIO1_12_IRQn (@GPIO1_12_IRQn@)
+#cmakedefine GPIO1_13_IRQn (@GPIO1_13_IRQn@)
+#cmakedefine GPIO1_14_IRQn (@GPIO1_14_IRQn@)
+#cmakedefine GPIO1_15_IRQn (@GPIO1_15_IRQn@)
+#cmakedefine GPIO2_0_IRQn (@GPIO2_0_IRQn@) /* All P2 I/O pins used as irq source */
+#cmakedefine GPIO2_1_IRQn (@GPIO2_1_IRQn@) /* There are 15 pins in total */
+#cmakedefine GPIO2_2_IRQn (@GPIO2_2_IRQn@)
+#cmakedefine GPIO2_3_IRQn (@GPIO2_3_IRQn@)
+#cmakedefine GPIO2_4_IRQn (@GPIO2_4_IRQn@)
+#cmakedefine GPIO2_5_IRQn (@GPIO2_5_IRQn@)
+#cmakedefine GPIO2_6_IRQn (@GPIO2_6_IRQn@)
+#cmakedefine GPIO2_7_IRQn (@GPIO2_7_IRQn@)
+#cmakedefine GPIO2_8_IRQn (@GPIO2_8_IRQn@)
+#cmakedefine GPIO2_9_IRQn (@GPIO2_9_IRQn@)
+#cmakedefine GPIO2_10_IRQn (@GPIO2_10_IRQn@)
+#cmakedefine GPIO2_11_IRQn (@GPIO2_11_IRQn@)
+#cmakedefine GPIO2_12_IRQn (@GPIO2_12_IRQn@)
+#cmakedefine GPIO2_13_IRQn (@GPIO2_13_IRQn@)
+#cmakedefine GPIO2_14_IRQn (@GPIO2_14_IRQn@)
+#cmakedefine GPIO2_15_IRQn (@GPIO2_15_IRQn@)
+#cmakedefine GPIO3_0_IRQn (@GPIO3_0_IRQn@) /* All P3 I/O pins used as irq source */
+#cmakedefine GPIO3_1_IRQn (@GPIO3_1_IRQn@) /* There are 4 pins in total */
+#cmakedefine GPIO3_2_IRQn (@GPIO3_2_IRQn@)
+#cmakedefine GPIO3_3_IRQn (@GPIO3_3_IRQn@)
+#cmakedefine UARTRX5_IRQn (@UARTRX5_IRQn@) /* UART 5 RX Interrupt */
+#cmakedefine UARTTX5_IRQn (@UARTTX5_IRQn@) /* UART 5 TX Interrupt */
+#cmakedefine UART5_IRQn (@UART5_IRQn@) /* UART 5 combined Interrupt */
+#cmakedefine HDCLCD_IRQn (@HDCLCD_IRQn@) /* HDCLCD Interrupt */
+
+#endif /* PERIPHERAL_IRQS_H */
diff --git a/source/hal/source/platform/mps3/cmake/templates/peripheral_memmap.h.template b/source/hal/source/platform/mps3/cmake/templates/peripheral_memmap.h.template
new file mode 100644
index 0000000..d7f0b3a
--- /dev/null
+++ b/source/hal/source/platform/mps3/cmake/templates/peripheral_memmap.h.template
@@ -0,0 +1,162 @@
+/*
+ * Copyright (c) 2021 Arm Limited. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+// Auto-generated file
+// ** DO NOT EDIT **
+
+#ifndef PERIPHERAL_MEMMAP_H
+#define PERIPHERAL_MEMMAP_H
+
+#cmakedefine DESIGN_NAME "@DESIGN_NAME@"
+
+/******************************************************************************/
+/* Peripheral memory map */
+/******************************************************************************/
+
+#cmakedefine CMSDK_GPIO0_BASE (@CMSDK_GPIO0_BASE@) /* User GPIO 0 Base Address */
+#cmakedefine CMSDK_GPIO1_BASE (@CMSDK_GPIO1_BASE@) /* User GPIO 1 Base Address */
+#cmakedefine CMSDK_GPIO2_BASE (@CMSDK_GPIO2_BASE@) /* User GPIO 2 Base Address */
+#cmakedefine CMSDK_GPIO3_BASE (@CMSDK_GPIO3_BASE@) /* User GPIO 3 Base Address */
+
+#cmakedefine FMC_CMDSK_GPIO_BASE0 (@FMC_CMDSK_GPIO_BASE0@) /* FMC_CMDSK_GPIO_BASE 0 Base Address (4KB) */
+#cmakedefine FMC_CMDSK_GPIO_BASE1 (@FMC_CMDSK_GPIO_BASE1@) /* FMC_CMDSK_GPIO_BASE 1 Base Address (4KB)*/
+#cmakedefine FMC_CMDSK_GPIO_BASE2 (@FMC_CMDSK_GPIO_BASE2@) /* FMC_CMDSK_GPIO_BASE 2 Base Address (4KB)*/
+#cmakedefine FMC_USER_AHB_BASE (@FMC_USER_AHB_BASE@) /* FMC_USER_AHB_BASE Base Address (4KB)*/
+
+#cmakedefine DMA0_BASE (@DMA0_BASE@) /* DMA0 (4KB) */
+#cmakedefine DMA1_BASE (@DMA1_BASE@) /* DMA1 (4KB) */
+#cmakedefine DMA2_BASE (@DMA2_BASE@) /* DMA2 (4KB) */
+#cmakedefine DMA3_BASE (@DMA3_BASE@) /* DMA3 (4KB) */
+
+#cmakedefine USER_APB0_BASE (@USER_APB0_BASE@) /* User APB0 */
+#cmakedefine USER_APB1_BASE (@USER_APB1_BASE@) /* User APB1 */
+#cmakedefine USER_APB2_BASE (@USER_APB2_BASE@) /* User APB2 */
+#cmakedefine USER_APB3_BASE (@USER_APB3_BASE@) /* User APB3 */
+
+#cmakedefine MPS3_I2C0_BASE (@MPS3_I2C0_BASE@) /* Touch Screen I2C Base Address */
+#cmakedefine MPS3_I2C1_BASE (@MPS3_I2C1_BASE@) /* Audio Interface I2C Base Address */
+#cmakedefine MPS3_SSP2_BASE (@MPS3_SSP2_BASE@) /* ADC SPI PL022 Base Address */
+#cmakedefine MPS3_SSP3_BASE (@MPS3_SSP3_BASE@) /* Shield 0 SPI PL022 Base Address */
+
+#cmakedefine MPS3_SSP4_BASE (@MPS3_SSP4_BASE@) /* Shield 1 SPI PL022 Base Address */
+#cmakedefine MPS3_I2C2_BASE (@MPS3_I2C2_BASE@) /* Shield 0 SBCon Base Address */
+#cmakedefine MPS3_I2C3_BASE (@MPS3_I2C3_BASE@) /* Shield 1 SBCon Base Address */
+
+#cmakedefine USER_APB_BASE (@USER_APB_BASE@) /* User APB Base Address */
+#cmakedefine MPS3_I2C4_BASE (@MPS3_I2C4_BASE@) /* HDMI I2C SBCon Base Address */
+#cmakedefine MPS3_I2C5_BASE (@MPS3_I2C5_BASE@) /* DDR EPROM I2C SBCon Base Address */
+#cmakedefine MPS3_SCC_BASE (@MPS3_SCC_BASE@) /* SCC Base Address */
+#cmakedefine MPS3_AAIC_I2S_BASE (@MPS3_AAIC_I2S_BASE@) /* Audio Interface I2S Base Address */
+#cmakedefine MPS3_FPGAIO_BASE (@MPS3_FPGAIO_BASE@) /* FPGA IO Base Address */
+#cmakedefine PL011_UART0_BASE (@PL011_UART0_BASE@) /* PL011 UART0 Base Address */
+#cmakedefine CMSDK_UART0_BASE (@CMSDK_UART0_BASE@) /* UART 0 Base Address */
+#cmakedefine CMSDK_UART1_BASE (@CMSDK_UART1_BASE@) /* UART 1 Base Address */
+#cmakedefine CMSDK_UART2_BASE (@CMSDK_UART2_BASE@) /* UART 2 Base Address */
+#cmakedefine CMSDK_UART3_BASE (@CMSDK_UART3_BASE@) /* UART 3 Base Address Shield 0*/
+
+#cmakedefine ETHOS_U_NPU_BASE (@ETHOS_U_NPU_BASE@) /* Ethos-U NPU base address*/
+#cmakedefine ETHOS_U_NPU_TA0_BASE (@ETHOS_U_NPU_TA0_BASE@) /* Ethos-U NPU's timing adapter 0 base address */
+#cmakedefine ETHOS_U_NPU_TA1_BASE (@ETHOS_U_NPU_TA1_BASE@) /* Ethos-U NPU's timing adapter 1 base address */
+
+#cmakedefine CMSDK_UART4_BASE (@CMSDK_UART4_BASE@) /* UART 4 Base Address Shield 1*/
+#cmakedefine CMSDK_UART5_BASE (@CMSDK_UART5_BASE@) /* UART 5 Base Address */
+#cmakedefine HDMI_AUDIO_BASE (@HDMI_AUDIO_BASE@) /* HDMI AUDIO Base Address */
+#cmakedefine CLCD_CONFIG_BASE (@CLCD_CONFIG_BASE@) /* CLCD CONFIG Base Address */
+#cmakedefine RTC_BASE (@RTC_BASE@) /* RTC Base address */
+#cmakedefine SMSC9220_BASE (@SMSC9220_BASE@) /* Ethernet SMSC9220 Base Address */
+#cmakedefine USB_BASE (@USB_BASE@) /* USB Base Address */
+#cmakedefine CMSDK_SDIO_BASE (@CMSDK_SDIO_BASE@) /* User SDIO Base Address */
+#cmakedefine MPS3_CLCD_BASE (@MPS3_CLCD_BASE@) /* HDLCD Base Address */
+#cmakedefine MPS3_eMMC_BASE (@MPS3_eMMC_BASE@) /* User eMMC Base Address */
+#cmakedefine USER_BASE (@USER_BASE@) /* User ? Base Address */
+
+#cmakedefine QSPI_XIP_BASE (@QSPI_XIP_BASE@) /* QSPI XIP config Base Address */
+#cmakedefine QSPI_WRITE_BASE (@QSPI_WRITE_BASE@) /* QSPI write config Base Address */
+
+/******************************************************************************/
+/* Secure Peripheral memory map */
+/******************************************************************************/
+
+#cmakedefine MPC_ISRAM0_BASE_S (@MPC_ISRAM0_BASE_S@) /* ISRAM0 Memory Protection Controller Secure base address */
+#cmakedefine MPC_ISRAM1_BASE_S (@MPC_ISRAM1_BASE_S@) /* ISRAM1 Memory Protection Controller Secure base address */
+
+#cmakedefine SEC_CMSDK_GPIO0_BASE (@SEC_CMSDK_GPIO0_BASE@) /* User GPIO 0 Base Address */
+#cmakedefine SEC_CMSDK_GPIO1_BASE (@SEC_CMSDK_GPIO1_BASE@) /* User GPIO 0 Base Address */
+#cmakedefine SEC_CMSDK_GPIO2_BASE (@SEC_CMSDK_GPIO2_BASE@) /* User GPIO 0 Base Address */
+#cmakedefine SEC_CMSDK_GPIO3_BASE (@SEC_CMSDK_GPIO3_BASE@) /* User GPIO 0 Base Address */
+
+#cmakedefine SEC_AHB_USER0_BASE (@SEC_AHB_USER0_BASE@) /* AHB USER 0 Base Address (4KB) */
+#cmakedefine SEC_AHB_USER1_BASE (@SEC_AHB_USER1_BASE@) /* AHB USER 1 Base Address (4KB)*/
+#cmakedefine SEC_AHB_USER2_BASE (@SEC_AHB_USER2_BASE@) /* AHB USER 2 Base Address (4KB)*/
+#cmakedefine SEC_AHB_USER3_BASE (@SEC_AHB_USER3_BASE@) /* AHB USER 3 Base Address (4KB)*/
+
+#cmakedefine SEC_DMA0_BASE (@SEC_DMA0_BASE@) /* DMA0 (4KB) */
+#cmakedefine SEC_DMA1_BASE (@SEC_DMA1_BASE@) /* DMA1 (4KB) */
+#cmakedefine SEC_DMA2_BASE (@SEC_DMA2_BASE@) /* DMA2 (4KB) */
+#cmakedefine SEC_DMA3_BASE (@SEC_DMA3_BASE@) /* DMA3 (4KB) */
+
+#cmakedefine SEC_USER_APB0_BASE (@SEC_USER_APB0_BASE@) /* User APB0 */
+#cmakedefine SEC_USER_APB1_BASE (@SEC_USER_APB1_BASE@) /* User APB1 */
+#cmakedefine SEC_USER_APB2_BASE (@SEC_USER_APB2_BASE@) /* User APB2 */
+#cmakedefine SEC_USER_APB3_BASE (@SEC_USER_APB3_BASE@) /* User APB3 */
+
+#cmakedefine SEC_MPS3_I2C0_BASE (@SEC_MPS3_I2C0_BASE@) /* Touch Screen I2C Base Address */
+#cmakedefine SEC_MPS3_I2C1_BASE (@SEC_MPS3_I2C1_BASE@) /* Audio Interface I2C Base Address */
+#cmakedefine SEC_MPS3_SSP2_BASE (@SEC_MPS3_SSP2_BASE@) /* ADC SPI PL022 Base Address */
+#cmakedefine SEC_MPS3_SSP3_BASE (@SEC_MPS3_SSP3_BASE@) /* Shield 0 SPI PL022 Base Address */
+
+#cmakedefine SEC_MPS3_SSP4_BASE (@SEC_MPS3_SSP4_BASE@) /* Shield 1 SPI PL022 Base Address */
+#cmakedefine SEC_MPS3_I2C2_BASE (@SEC_MPS3_I2C2_BASE@) /* Shield 0 SBCon Base Address */
+#cmakedefine SEC_MPS3_I2C3_BASE (@SEC_MPS3_I2C3_BASE@) /* Shield 1 SBCon Base Address */
+
+#cmakedefine SEC_MPS3_I2C4_BASE (@SEC_MPS3_I2C4_BASE@) /* HDMI I2C SBCon Base Address */
+#cmakedefine SEC_MPS3_I2C5_BASE (@SEC_MPS3_I2C5_BASE@) /* DDR EPROM I2C SBCon Base Address */
+#cmakedefine SEC_MPS3_SCC_BASE (@SEC_MPS3_SCC_BASE@) /* SCC Base Address */
+#cmakedefine SEC_MPS3_AAIC_I2S_BASE (@SEC_MPS3_AAIC_I2S_BASE@) /* Audio Interface I2S Base Address */
+#cmakedefine SEC_MPS3_FPGAIO_BASE (@SEC_MPS3_FPGAIO_BASE@) /* FPGA IO Base Address */
+#cmakedefine SEC_CMSDK_UART0_BASE (@SEC_CMSDK_UART0_BASE@) /* UART 0 Base Address */
+#cmakedefine SEC_CMSDK_UART1_BASE (@SEC_CMSDK_UART1_BASE@) /* UART 1 Base Address */
+#cmakedefine SEC_CMSDK_UART2_BASE (@SEC_CMSDK_UART2_BASE@) /* UART 2 Base Address */
+#cmakedefine SEC_CMSDK_UART3_BASE (@SEC_CMSDK_UART3_BASE@) /* UART 3 Base Address Shield 0*/
+
+#cmakedefine SEC_CMSDK_UART4_BASE (@SEC_CMSDK_UART4_BASE@) /* UART 4 Base Address Shield 1*/
+#cmakedefine SEC_CMSDK_UART5_BASE (@SEC_CMSDK_UART5_BASE@) /* UART 5 Base Address */
+#cmakedefine SEC_HDMI_AUDIO_BASE (@SEC_HDMI_AUDIO_BASE@) /* HDMI AUDIO Base Address */
+#cmakedefine SEC_CLCD_CONFIG_BASE (@SEC_CLCD_CONFIG_BASE@) /* CLCD CONFIG Base Address */
+#cmakedefine SEC_RTC_BASE (@SEC_RTC_BASE@) /* RTC Base address */
+#cmakedefine SEC_SMSC9220_BASE (@SEC_SMSC9220_BASE@) /* Ethernet SMSC9220 Base Address */
+#cmakedefine SEC_USB_BASE (@SEC_USB_BASE@) /* USB Base Address */
+
+#cmakedefine SEC_ETHOS_U_NPU_BASE (@SEC_ETHOS_U_NPU_BASE@) /* Ethos-U NPU base address*/
+#cmakedefine SEC_ETHOS_U_NPU_TA0_BASE (@SEC_ETHOS_U_NPU_TA0_BASE@) /* Ethos-U NPU's timing adapter 0 base address */
+#cmakedefine SEC_ETHOS_U_NPU_TA1_BASE (@SEC_ETHOS_U_NPU_TA1_BASE@) /* Ethos-U NPU's timing adapter 1 base address */
+
+#cmakedefine SEC_USER_BASE (@SEC_USER_BASE@) /* User ? Base Address */
+
+#cmakedefine SEC_QSPI_XIP_BASE (@SEC_QSPI_XIP_BASE@) /* QSPI XIP config Base Address */
+#cmakedefine SEC_QSPI_WRITE_BASE (@SEC_QSPI_WRITE_BASE@) /* QSPI write config Base Address */
+
+/******************************************************************************/
+/* MPCs */
+/******************************************************************************/
+
+#cmakedefine MPC_ISRAM0_BASE_S (@MPC_ISRAM0_BASE_S@) /* Internal SRAM 0 MPC */
+#cmakedefine MPC_ISRAM1_BASE_S (@MPC_ISRAM1_BASE_S@) /* Internal SRAM 1 MPC */
+#cmakedefine MPC_BRAM_BASE_S (@MPC_BRAM_BASE_S@) /* SRAM Memory Protection Controller Secure base address */
+#cmakedefine MPC_QSPI_BASE_S (@MPC_QSPI_BASE_S@) /* QSPI Memory Protection Controller Secure base address */
+#cmakedefine MPC_DDR4_BASE_S (@MPC_DDR4_BASE_S@) /* DDR4 Memory Protection Controller Secure base address */
+
+#endif /* PERIPHERAL_MEMMAP_H */
diff --git a/source/hal/source/platform/mps3/cmake/templates/timing_adapter_settings.template b/source/hal/source/platform/mps3/cmake/templates/timing_adapter_settings.template
new file mode 100644
index 0000000..d5e202a
--- /dev/null
+++ b/source/hal/source/platform/mps3/cmake/templates/timing_adapter_settings.template
@@ -0,0 +1,64 @@
+/*
+ * Copyright (c) 2021 Arm Limited. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+// Auto-generated file
+// ** DO NOT EDIT **
+
+#ifndef TIMING_ADAPTER_SETTINGS_H
+#define TIMING_ADAPTER_SETTINGS_H
+
+#cmakedefine TA0_BASE (@TA0_BASE@)
+#cmakedefine TA1_BASE (@TA1_BASE@)
+
+/* Timing adapter settings for AXI0 */
+#if defined(TA0_BASE)
+
+#define TA0_MAXR (@TA0_MAXR@)
+#define TA0_MAXW (@TA0_MAXW@)
+#define TA0_MAXRW (@TA0_MAXRW@)
+#define TA0_RLATENCY (@TA0_RLATENCY@)
+#define TA0_WLATENCY (@TA0_WLATENCY@)
+#define TA0_PULSE_ON (@TA0_PULSE_ON@)
+#define TA0_PULSE_OFF (@TA0_PULSE_OFF@)
+#define TA0_BWCAP (@TA0_BWCAP@)
+#define TA0_PERFCTRL (@TA0_PERFCTRL@)
+#define TA0_PERFCNT (@TA0_PERFCNT@)
+#define TA0_MODE (@TA0_MODE@)
+#define TA0_HISTBIN (@TA0_HISTBIN@)
+#define TA0_HISTCNT (@TA0_HISTCNT@)
+
+#endif /* defined(TA0_BASE) */
+
+/* Timing adapter settings for AXI1 */
+#if defined(TA1_BASE)
+
+#define TA1_MAXR (@TA1_MAXR@)
+#define TA1_MAXW (@TA1_MAXW@)
+#define TA1_MAXRW (@TA1_MAXRW@)
+#define TA1_RLATENCY (@TA1_RLATENCY@)
+#define TA1_WLATENCY (@TA1_WLATENCY@)
+#define TA1_PULSE_ON (@TA1_PULSE_ON@)
+#define TA1_PULSE_OFF (@TA1_PULSE_OFF@)
+#define TA1_BWCAP (@TA1_BWCAP@)
+#define TA1_PERFCTRL (@TA1_PERFCTRL@)
+#define TA1_PERFCNT (@TA1_PERFCNT@)
+#define TA1_MODE (@TA1_MODE@)
+#define TA1_HISTBIN (@TA1_HISTBIN@)
+#define TA1_HISTCNT (@TA1_HISTCNT@)
+
+#endif /* defined(TA1_BASE) */
+
+#endif /* TIMING_ADAPTER_SETTINGS_H */
\ No newline at end of file
diff --git a/source/hal/source/platform/mps3/include/platform_drivers.h b/source/hal/source/platform/mps3/include/platform_drivers.h
new file mode 100644
index 0000000..8b699d5
--- /dev/null
+++ b/source/hal/source/platform/mps3/include/platform_drivers.h
@@ -0,0 +1,47 @@
+/*
+ * Copyright (c) 2021-2022 Arm Limited. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef PLATFORM_DRIVERS_H
+#define PLATFORM_DRIVERS_H
+
+#include "log_macros.h" /* Logging related helpers. */
+
+/* Platform components */
+#include "RTE_Components.h" /* For CPU related defintiions */
+#include "timer_mps3.h" /* Timer functions. */
+#include "user_input.h" /* User input function */
+#include "lcd_img.h" /* LCD functions. */
+
+/**
+ * @brief Initialises the platform components.
+ * @return 0 if successful, error code otherwise.
+ */
+int platform_init(void);
+
+/**
+ * @brief Teardown for platform components.
+ */
+void platform_release(void);
+
+/**
+ * @brief Sets the platform name.
+ * @param[out] name Name of the platform to be set
+ * @param[in] size Size of the input buffer
+ */
+void platform_name(char* name, size_t size);
+
+#endif /* PLATFORM_DRIVERS_H */
diff --git a/source/hal/source/platform/mps3/include/timer_mps3.h b/source/hal/source/platform/mps3/include/timer_mps3.h
new file mode 100644
index 0000000..e1faf69
--- /dev/null
+++ b/source/hal/source/platform/mps3/include/timer_mps3.h
@@ -0,0 +1,97 @@
+/*
+ * Copyright (c) 2021-2022 Arm Limited. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef TIMER_MPS3_H
+#define TIMER_MPS3_H
+
+#include <stdint.h>
+
+/* Container for timestamp up-counters. */
+typedef struct _mps3_time_counter {
+ uint32_t counter_1Hz;
+ uint32_t counter_100Hz;
+
+ /* Running at FPGA clock rate. See get_mps3_core_clock(). */
+ uint32_t counter_fpga;
+
+ /* Running at processor core's internal clock rate, triggered by SysTick. */
+ uint64_t counter_systick;
+} base_time_counter;
+
+
+/**
+ * @brief Gets the MPS3 core clock
+ * @return Clock rate in Hz expressed as 32 bit unsigned integer.
+ */
+uint32_t get_mps3_core_clock(void);
+
+/**
+ * @brief Resets the counters.
+ */
+void timer_reset(void);
+
+/**
+ * @brief Gets the current counter values.
+ * @returns Mps3 timer counter.
+ **/
+base_time_counter get_time_counter(void);
+
+/**
+ * @brief Gets the duration elapsed between two counters in milliseconds.
+ * @param[in] start Pointer to base_time_counter value at start time.
+ * @param[in] end Pointer to base_time_counter value at end.
+ * @returns Difference in milliseconds between the two give counters
+ * expressed as an unsigned integer.
+ **/
+uint32_t get_duration_milliseconds(base_time_counter *start,
+ base_time_counter *end);
+
+/**
+ * @brief Gets the duration elapsed between two counters in microseconds.
+ * @param[in] start Pointer to base_time_counter value at start time.
+ * @param[in] end Pointer to base_time_counter value at end.
+ * @returns Difference in microseconds between the two give counters
+ * expressed as an unsigned integer.
+ **/
+uint32_t get_duration_microseconds(base_time_counter *start,
+ base_time_counter *end);
+
+/**
+ * @brief Gets the cycle counts elapsed between start and end.
+ * @param[in] start Pointer to base_time_counter value at start time.
+ * @param[in] end Pointer to base_time_counter value at end.
+ * @return Difference in counter values as 32 bit unsigned integer.
+ **/
+uint64_t get_cycle_count_diff(base_time_counter *start,
+ base_time_counter *end);
+
+/**
+ * @brief Enables or triggers cycle counting mechanism, if required
+ * by the platform.
+ **/
+void start_cycle_counter(void);
+
+/**
+ * @brief Stops cycle counting mechanism, if required by the platform.
+ **/
+void stop_cycle_counter(void);
+
+/**
+ * @brief System tick interrupt handler.
+ **/
+void SysTick_Handler(void);
+
+#endif /* TIMER_MPS3_H */
diff --git a/source/hal/source/platform/mps3/source/device_mps3.h b/source/hal/source/platform/mps3/source/device_mps3.h
new file mode 100644
index 0000000..9447c07
--- /dev/null
+++ b/source/hal/source/platform/mps3/source/device_mps3.h
@@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2022 Arm Limited. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef DEVICE_MPS3_H
+#define DEVICE_MPS3_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdio.h>
+#include <stdint.h>
+
+/**
+ * @brief Gets the core clock set for MPS3.
+ * @return Clock value in Hz.
+ **/
+uint32_t GetMPS3CoreClock(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* DEVICE_MPS3_H */
diff --git a/source/hal/source/platform/mps3/source/platform_drivers.c b/source/hal/source/platform/mps3/source/platform_drivers.c
new file mode 100644
index 0000000..5de41c2
--- /dev/null
+++ b/source/hal/source/platform/mps3/source/platform_drivers.c
@@ -0,0 +1,161 @@
+/*
+ * Copyright (c) 2022 Arm Limited. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "platform_drivers.h"
+
+#include "log_macros.h" /* Logging functions */
+#include "uart_stdout.h" /* stdout over UART. */
+#include "smm_mps3.h" /* Memory map for MPS3. */
+
+#include <string.h> /* For strncpy */
+
+#if defined(ARM_NPU)
+#include "ethosu_npu_init.h"
+
+#if defined(ETHOS_U_NPU_TIMING_ADAPTER_ENABLED)
+#include "ethosu_ta_init.h"
+#endif /* ETHOS_U_NPU_TIMING_ADAPTER_ENABLED */
+
+#endif /* ARM_NPU */
+
+/**
+ * @brief Checks if the platform is valid by checking
+ * the CPU ID for the FPGA implementation against
+ * the register from the CPU core.
+ * @return 0 if successful, 1 otherwise
+ */
+static int verify_platform(void);
+
+int platform_init(void)
+{
+ int err = 0;
+
+ SystemCoreClockUpdate(); /* From start up code */
+
+ /* UART init - will enable valid use of printf (stdout
+ * re-directed at this UART (UART0) */
+ UartStdOutInit();
+
+ if (0 != (err = verify_platform())) {
+ return err;
+ }
+
+#if defined(ARM_NPU)
+
+#if defined(ETHOS_U_NPU_TIMING_ADAPTER_ENABLED)
+ /* If the platform has timing adapter blocks along with Ethos-U core
+ * block, initialise them here. */
+ if (0 != (err = arm_ethosu_timing_adapter_init())) {
+ return err;
+ }
+#endif /* ETHOS_U_NPU_TIMING_ADAPTER_ENABLED */
+
+ int state;
+
+ /* If Arm Ethos-U NPU is to be used, we initialise it here */
+ if (0 != (state = arm_ethosu_npu_init())) {
+ return state;
+ }
+
+#endif /* ARM_NPU */
+
+ /* Print target design info */
+ info("Target system design: %s\n", DESIGN_NAME);
+
+ return 0;
+}
+
+void platform_release(void)
+{
+ __disable_irq();
+}
+
+void platform_name(char* name, size_t size)
+{
+ strncpy(name, DESIGN_NAME, size);
+}
+
+#define CREATE_MASK(msb, lsb) (int)(((1U << ((msb) - (lsb) + 1)) - 1) << (lsb))
+#define MASK_BITS(arg, msb, lsb) (int)((arg) & CREATE_MASK(msb, lsb))
+#define EXTRACT_BITS(arg, msb, lsb) (int)(MASK_BITS(arg, msb, lsb) >> (lsb))
+
+static int verify_platform(void)
+{
+ uint32_t id = 0;
+ uint32_t fpgaid = 0;
+ uint32_t apnote = 0;
+ uint32_t rev = 0;
+ uint32_t aid = 0;
+ uint32_t fpga_clk = 0;
+ const uint32_t ascii_A = (uint32_t)('A');
+
+ /* Initialise the LEDs as the switches are */
+ MPS3_FPGAIO->LED = MPS3_FPGAIO->SWITCHES & 0xFF;
+
+ info("Processor internal clock: %" PRIu32 "Hz\n", get_mps3_core_clock());
+
+ /* Get revision information from various registers */
+ rev = MPS3_SCC->CFG_REG4;
+ fpgaid = MPS3_SCC->SCC_ID;
+ aid = MPS3_SCC->SCC_AID;
+ apnote = EXTRACT_BITS(fpgaid, 15, 4);
+ fpga_clk = get_mps3_core_clock();
+
+ info("V2M-MPS3 revision %c\n\n", (char)(rev + ascii_A));
+ info("Application Note AN%" PRIx32 ", Revision %c\n", apnote,
+ (char)(EXTRACT_BITS(aid, 23, 20) + ascii_A));
+ info("MPS3 build %d\n", EXTRACT_BITS(aid, 31, 24));
+ info("MPS3 core clock has been set to: %" PRIu32 "Hz\n", fpga_clk);
+
+ /* Display CPU ID */
+ id = SCB->CPUID;
+ info("CPU ID: 0x%08" PRIx32 "\n", id);
+
+ if(EXTRACT_BITS(id, 15, 8) == 0xD2) {
+ if (EXTRACT_BITS(id, 7, 4) == 2) {
+ info ("CPU: Cortex-M55 r%dp%d\n\n",
+ EXTRACT_BITS(id, 23, 20),EXTRACT_BITS(id, 3, 0));
+#if defined (CPU_CORTEX_M55)
+ /* CPU ID should be "0x_41_0f_d2_20" for Cortex-M55 */
+ return 0;
+#endif /* CPU_CORTEX_M55 */
+ } else if (EXTRACT_BITS(id, 7, 4) == 1) {
+ info ("CPU: Cortex-M33 r%dp%d\n\n",
+ EXTRACT_BITS(id, 23, 20),EXTRACT_BITS(id, 3, 0));
+#if defined (CPU_CORTEX_M33)
+ return 0;
+#endif /* CPU_CORTEX_M33 */
+ } else if (EXTRACT_BITS(id, 7, 4) == 0) {
+ info ("CPU: Cortex-M23 r%dp%d\n\n",
+ EXTRACT_BITS(id, 23, 20),EXTRACT_BITS(id, 3, 0));
+ } else {
+ info ("CPU: Cortex-M processor family");
+ }
+ } else if (EXTRACT_BITS(id, 15, 8) == 0xC6) {
+ info ("CPU: Cortex-M%d+ r%dp%d\n\n",
+ EXTRACT_BITS(id, 7, 4), EXTRACT_BITS(id, 23, 20),
+ EXTRACT_BITS(id, 3, 0));
+ } else {
+ info ("CPU: Cortex-M%d r%dp%d\n\n",
+ EXTRACT_BITS(id, 7, 4), EXTRACT_BITS(id, 23, 20),
+ EXTRACT_BITS(id, 3, 0));
+ }
+
+ /* If the CPU is anything other than M33 or M55, we return 1 */
+ printf_err("CPU mismatch!\n");
+ return 1;
+}
diff --git a/source/hal/source/platform/mps3/source/smm_mps3.h b/source/hal/source/platform/mps3/source/smm_mps3.h
new file mode 100644
index 0000000..8d5614a
--- /dev/null
+++ b/source/hal/source/platform/mps3/source/smm_mps3.h
@@ -0,0 +1,616 @@
+/*
+ * Copyright (c) 2022 Arm Limited. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef SMM_MPS3_H
+#define SMM_MPS3_H
+
+#include "peripheral_memmap.h" /* Peripheral memory map definitions. */
+
+#include "RTE_Components.h"
+
+#if defined ( __CC_ARM )
+#pragma anon_unions
+#endif
+
+/******************************************************************************/
+/* FPGA System Register declaration */
+/******************************************************************************/
+
+typedef struct
+{
+ __IO uint32_t LED; /* Offset: 0x000 (R/W) LED connections
+ * [31:2] : Reserved
+ * [1:0] : LEDs
+ */
+ uint32_t RESERVED1[1];
+ __IO uint32_t BUTTON; /* Offset: 0x008 (R/W) Buttons
+ * [31:2] : Reserved
+ * [1:0] : Buttons
+ */
+ uint32_t RESERVED2[1];
+ __IO uint32_t CLK1HZ; /* Offset: 0x010 (R/W) 1Hz up counter */
+ __IO uint32_t CLK100HZ; /* Offset: 0x014 (R/W) 100Hz up counter */
+ __IO uint32_t COUNTER; /* Offset: 0x018 (R/W) Cycle Up Counter
+ * Increments when 32-bit prescale counter reach zero
+ */
+ __IO uint32_t PRESCALE; /* Offset: 0x01C (R/W) Prescaler
+ * Bit[31:0] : reload value for prescale counter
+ */
+ __IO uint32_t PSCNTR; /* Offset: 0x020 (R/W) 32-bit Prescale counter
+ * current value of the pre-scaler counter
+ * The Cycle Up Counter increment when the prescale down counter reach 0
+ * The pre-scaler counter is reloaded with PRESCALE after reaching 0.
+ */
+ uint32_t RESERVED3[1];
+ __IO uint32_t SWITCHES; /* Offset: 0x028 (R/W) Switches
+ * [31:8] : Reserved
+ * [7:0] : Switches
+ */
+ uint32_t RESERVED4[8];
+ __IO uint32_t MISC; /* Offset: 0x04C (R/W) Misc control
+ * [31:10] : Reserved
+ * [9] :
+ * [8] :
+ * [7] : ADC_SPI_nCS
+ * [6] : CLCD_BL_CTRL
+ * [5] : CLCD_RD
+ * [4] : CLCD_RS
+ * [3] : CLCD_RESET
+ * [2] : SHIELD_1_SPI_nCS
+ * [1] : SHIELD_0_SPI_nCS
+ * [0] : CLCD_CS
+ */
+} MPS3_FPGAIO_TypeDef;
+
+/* MISC register bit definitions. */
+
+#define CLCD_CS_Pos 0
+#define CLCD_CS_Msk (1UL<<CLCD_CS_Pos)
+#define SHIELD_0_nCS_Pos 1
+#define SHIELD_0_nCS_Msk (1UL<<SHIELD_0_nCS_Pos)
+#define SHIELD_1_nCS_Pos 2
+#define SHIELD_1_nCS_Msk (1UL<<SHIELD_1_nCS_Pos)
+#define CLCD_RESET_Pos 3
+#define CLCD_RESET_Msk (1UL<<CLCD_RESET_Pos)
+#define CLCD_RS_Pos 4
+#define CLCD_RS_Msk (1UL<<CLCD_RS_Pos)
+#define CLCD_RD_Pos 5
+#define CLCD_RD_Msk (1UL<<CLCD_RD_Pos)
+#define CLCD_BL_Pos 6
+#define CLCD_BL_Msk (1UL<<CLCD_BL_Pos)
+#define ADC_nCS_Pos 7
+#define ADC_nCS_Msk (1UL<<ADC_nCS_Pos)
+
+/******************************************************************************/
+/* SCC Register declaration */
+/******************************************************************************/
+
+typedef struct
+{
+ __IO uint32_t CFG_REG0; /* Offset: 0x000 (R/W) Remaps block RAM to ZBT
+ * [31:1] : Reserved
+ * [0] 1 : REMAP BlockRam to ZBT
+ */
+ __IO uint32_t LEDS; /* Offset: 0x004 (R/W) Controls the MCC user LEDs
+ * [31:8] : Reserved
+ * [7:0] : MCC LEDs
+ */
+ uint32_t RESERVED0[1];
+ __I uint32_t SWITCHES; /* Offset: 0x00C (R/ ) Denotes the state of the MCC user switches
+ * [31:8] : Reserved
+ * [7:0] : These bits indicate state of the MCC switches
+ */
+ __I uint32_t CFG_REG4; /* Offset: 0x010 (R/ ) Denotes the board revision
+ * [31:4] : Reserved
+ * [3:0] : Used by the MCC to pass PCB revision. 0 = A 1 = B
+ */
+ __I uint32_t CFG_ACLK; /* Offset: 0x014 (R/ ) System Clock
+ */
+ uint32_t RESERVED1[34];
+ __IO uint32_t SYS_CFGDATA_RTN; /* Offset: 0x0A0 (R/W) User data register
+ * [31:0] : Data
+ */
+ __IO uint32_t SYS_CFGDATA_OUT; /* Offset: 0x0A4 (R/W) User data register
+ * [31:0] : Data
+ */
+ __IO uint32_t SYS_CFGCTRL; /* Offset: 0x0A8 (R/W) Control register
+ * [31] : Start (generates interrupt on write to this bit)
+ * [30] : R/W access
+ * [29:26] : Reserved
+ * [25:20] : Function value
+ * [19:12] : Reserved
+ * [11:0] : Device (value of 0/1/2 for supported clocks)
+ */
+ __IO uint32_t SYS_CFGSTAT; /* Offset: 0x0AC (R/W) Contains status information
+ * [31:2] : Reserved
+ * [1] : Error
+ * [0] : Complete
+ */
+ __IO uint32_t RESERVED2[20];
+ __IO uint32_t SCC_DLL; /* Offset: 0x100 (R/W) DLL Lock Register
+ * [31:24] : DLL LOCK MASK[7:0] - Indicate if the DLL locked is masked
+ * [23:16] : DLL LOCK MASK[7:0] - Indicate if the DLLs are locked or unlocked
+ * [15:1] : Reserved
+ * [0] : This bit indicates if all enabled DLLs are locked
+ */
+ uint32_t RESERVED3[957];
+ __I uint32_t SCC_AID; /* Offset: 0xFF8 (R/ ) SCC AID Register
+ * [31:24] : FPGA build number
+ * [23:20] : V2M-MPS3 target board revision (A = 0, B = 1)
+ * [19:11] : Reserved
+ * [10] : if “1” SCC_SW register has been implemented
+ * [9] : if “1” SCC_LED register has been implemented
+ * [8] : if “1” DLL lock register has been implemented
+ * [7:0] : number of SCC configuration register
+ */
+ __I uint32_t SCC_ID; /* Offset: 0xFFC (R/ ) Contains information about the FPGA image
+ * [31:24] : Implementer ID: 0x41 = ARM
+ * [23:20] : Application note IP variant number
+ * [19:16] : IP Architecture: 0x4 =AHB
+ * [15:4] : Primary part number: 386 = AN386
+ * [3:0] : Application note IP revision number
+ */
+} MPS3_SCC_TypeDef;
+
+
+/******************************************************************************/
+/* SSP Peripheral declaration */
+/******************************************************************************/
+
+typedef struct
+{
+ __IO uint32_t CR0; /* Offset: 0x000 (R/W) Control register 0
+ * [31:16] : Reserved
+ * [15:8] : Serial clock rate
+ * [7] : SSPCLKOUT phase, applicable to Motorola SPI frame format only
+ * [6] : SSPCLKOUT polarity, applicable to Motorola SPI frame format only
+ * [5:4] : Frame format
+ * [3:0] : Data Size Select
+ */
+ __IO uint32_t CR1; /* Offset: 0x004 (R/W) Control register 1
+ * [31:4] : Reserved
+ * [3] : Slave-mode output disable
+ * [2] : Master or slave mode select
+ * [1] : Synchronous serial port enable
+ * [0] : Loop back mode
+ */
+ __IO uint32_t DR; /* Offset: 0x008 (R/W) Data register
+ * [31:16] : Reserved
+ * [15:0] : Transmit/Receive FIFO
+ */
+ __I uint32_t SR; /* Offset: 0x00C (R/ ) Status register
+ * [31:5] : Reserved
+ * [4] : PrimeCell SSP busy flag
+ * [3] : Receive FIFO full
+ * [2] : Receive FIFO not empty
+ * [1] : Transmit FIFO not full
+ * [0] : Transmit FIFO empty
+ */
+ __IO uint32_t CPSR; /* Offset: 0x010 (R/W) Clock prescale register
+ * [31:8] : Reserved
+ * [8:0] : Clock prescale divisor
+ */
+ __IO uint32_t IMSC; /* Offset: 0x014 (R/W) Interrupt mask set or clear register
+ * [31:4] : Reserved
+ * [3] : Transmit FIFO interrupt mask
+ * [2] : Receive FIFO interrupt mask
+ * [1] : Receive timeout interrupt mask
+ * [0] : Receive overrun interrupt mask
+ */
+ __I uint32_t RIS; /* Offset: 0x018 (R/ ) Raw interrupt status register
+ * [31:4] : Reserved
+ * [3] : raw interrupt state, prior to masking, of the SSPTXINTR interrupt
+ * [2] : raw interrupt state, prior to masking, of the SSPRXINTR interrupt
+ * [1] : raw interrupt state, prior to masking, of the SSPRTINTR interrupt
+ * [0] : raw interrupt state, prior to masking, of the SSPRORINTR interrupt
+ */
+ __I uint32_t MIS; /* Offset: 0x01C (R/ ) Masked interrupt status register
+ * [31:4] : Reserved
+ * [3] : transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt
+ * [2] : receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt
+ * [1] : receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt
+ * [0] : receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt
+ */
+ __O uint32_t ICR; /* Offset: 0x020 ( /W) Interrupt clear register
+ * [31:2] : Reserved
+ * [1] : Clears the SSPRTINTR interrupt
+ * [0] : Clears the SSPRORINTR interrupt
+ */
+ __IO uint32_t DMACR; /* Offset: 0x024 (R/W) DMA control register
+ * [31:2] : Reserved
+ * [1] : Transmit DMA Enable
+ * [0] : Receive DMA Enable
+ */
+} MPS3_SSP_TypeDef;
+
+
+/* SSP_CR0 Control register 0. */
+#define SSP_CR0_DSS_Pos 0 /* Data Size Select. */
+#define SSP_CR0_DSS_Msk (0xF<<SSP_CR0_DSS_Pos)
+#define SSP_CR0_FRF_Pos 4 /* Frame Format Select. */
+#define SSP_CR0_FRF_Msk (3UL<<SSP_CR0_FRM_Pos)
+#define SSP_CR0_SPO_Pos 6 /* SSPCLKOUT polarity. */
+#define SSP_CR0_SPO_Msk (1UL<<SSP_CR0_SPO_Pos)
+#define SSP_CR0_SPH_Pos 7 /* SSPCLKOUT phase. */
+#define SSP_CR0_SPH_Msk (1UL<<SSP_CR0_SPH_Pos)
+#define SSP_CR0_SCR_Pos 8 /* Serial Clock Rate (divide). */
+#define SSP_CR0_SCR_Msk (0xFF<<SSP_CR0_SCR_Pos)
+
+#define SSP_CR0_SCR_DFLT 0x0300 /* Serial Clock Rate (divide), default set at 3. */
+#define SSP_CR0_FRF_MOT 0x0000 /* Frame format. */
+#define SSP_CR0_DSS_8 0x0007 /* Data packet size, 8bits. */
+#define SSP_CR0_DSS_16 0x000F /* Data packet size, 16bits. */
+
+/* SSP_CR1 Control register 1. */
+#define SSP_CR1_LBM_Pos 0 /* Loop Back Mode. */
+#define SSP_CR1_LBM_Msk (1UL<<SSP_CR1_LBM_Pos)
+#define SSP_CR1_SSE_Pos 1 /* Serial port enable. */
+#define SSP_CR1_SSE_Msk (1UL<<SSP_CR1_SSE_Pos)
+#define SSP_CR1_MS_Pos 2 /* Master or Slave mode. */
+#define SSP_CR1_MS_Msk (1UL<<SSP_CR1_MS_Pos)
+#define SSP_CR1_SOD_Pos 3 /* Slave Output mode Disable. */
+#define SSP_CR1_SOD_Msk (1UL<<SSP_CR1_SOD_Pos)
+
+/* SSP_SR Status register. */
+#define SSP_SR_TFE_Pos 0 /* Transmit FIFO empty. */
+#define SSP_SR_TFE_Msk (1UL<<SSP_SR_TFE_Pos)
+#define SSP_SR_TNF_Pos 1 /* Transmit FIFO not full. */
+#define SSP_SR_TNF_Msk (1UL<<SSP_SR_TNF_Pos)
+#define SSP_SR_RNE_Pos 2 /* Receive FIFO not empty. */
+#define SSP_SR_RNE_Msk (1UL<<SSP_SR_RNE_Pos)
+#define SSP_SR_RFF_Pos 3 /* Receive FIFO full. */
+#define SSP_SR_RFF_Msk (1UL<<SSP_SR_RFF_Pos)
+#define SSP_SR_BSY_Pos 4 /* Busy. */
+#define SSP_SR_BSY_Msk (1UL<<SSP_SR_BSY_Pos)
+
+/* SSP_CPSR Clock prescale register. */
+#define SSP_CPSR_CPD_Pos 0 /* Clock prescale divisor. */
+#define SSP_CPSR_CPD_Msk (0xFF<<SSP_CPSR_CDP_Pos)
+
+#define SSP_CPSR_DFLT 0x0008 /* Clock prescale (use with SCR), default set at 8. */
+
+/* SSPIMSC Interrupt mask set and clear register. */
+#define SSP_IMSC_RORIM_Pos 0 /* Receive overrun not Masked. */
+#define SSP_IMSC_RORIM_Msk (1UL<<SSP_IMSC_RORIM_Pos)
+#define SSP_IMSC_RTIM_Pos 1 /* Receive timeout not Masked. */
+#define SSP_IMSC_RTIM_Msk (1UL<<SSP_IMSC_RTIM_Pos)
+#define SSP_IMSC_RXIM_Pos 2 /* Receive FIFO not Masked. */
+#define SSP_IMSC_RXIM_Msk (1UL<<SSP_IMSC_RXIM_Pos)
+#define SSP_IMSC_TXIM_Pos 3 /* Transmit FIFO not Masked. */
+#define SSP_IMSC_TXIM_Msk (1UL<<SSP_IMSC_TXIM_Pos)
+
+/* SSPRIS Raw interrupt status register. */
+#define SSP_RIS_RORRIS_Pos 0 /* Raw Overrun interrupt flag. */
+#define SSP_RIS_RORRIS_Msk (1UL<<SSP_RIS_RORRIS_Pos)
+#define SSP_RIS_RTRIS_Pos 1 /* Raw Timemout interrupt flag. */
+#define SSP_RIS_RTRIS_Msk (1UL<<SSP_RIS_RTRIS_Pos)
+#define SSP_RIS_RXRIS_Pos 2 /* Raw Receive interrupt flag. */
+#define SSP_RIS_RXRIS_Msk (1UL<<SSP_RIS_RXRIS_Pos)
+#define SSP_RIS_TXRIS_Pos 3 /* Raw Transmit interrupt flag. */
+#define SSP_RIS_TXRIS_Msk (1UL<<SSP_RIS_TXRIS_Pos)
+
+/* SSPMIS Masked interrupt status register. */
+#define SSP_MIS_RORMIS_Pos 0 /* Masked Overrun interrupt flag. */
+#define SSP_MIS_RORMIS_Msk (1UL<<SSP_MIS_RORMIS_Pos)
+#define SSP_MIS_RTMIS_Pos 1 /* Masked Timemout interrupt flag. */
+#define SSP_MIS_RTMIS_Msk (1UL<<SSP_MIS_RTMIS_Pos)
+#define SSP_MIS_RXMIS_Pos 2 /* Masked Receive interrupt flag. */
+#define SSP_MIS_RXMIS_Msk (1UL<<SSP_MIS_RXMIS_Pos)
+#define SSP_MIS_TXMIS_Pos 3 /* Masked Transmit interrupt flag. */
+#define SSP_MIS_TXMIS_Msk (1UL<<SSP_MIS_TXMIS_Pos)
+
+/* SSPICR Interrupt clear register. */
+#define SSP_ICR_RORIC_Pos 0 /* Clears Overrun interrupt flag. */
+#define SSP_ICR_RORIC_Msk (1UL<<SSP_ICR_RORIC_Pos)
+#define SSP_ICR_RTIC_Pos 1 /* Clears Timemout interrupt flag. */
+#define SSP_ICR_RTIC_Msk (1UL<<SSP_ICR_RTIC_Pos)
+
+/* SSPDMACR DMA control register. */
+#define SSP_DMACR_RXDMAE_Pos 0 /* Enable Receive FIFO DMA. */
+#define SSP_DMACR_RXDMAE_Msk (1UL<<SSP_DMACR_RXDMAE_Pos)
+#define SSP_DMACR_TXDMAE_Pos 1 /* Enable Transmit FIFO DMA. */
+#define SSP_DMACR_TXDMAE_Msk (1UL<<SSP_DMACR_TXDMAE_Pos)
+
+/******************************************************************************/
+/* Audio and Touch Screen (I2C) Peripheral declaration */
+/******************************************************************************/
+
+typedef struct
+{
+ union {
+ __O uint32_t CONTROLS; /* Offset: 0x000 CONTROL Set Register ( /W). */
+ __I uint32_t CONTROL; /* Offset: 0x000 CONTROL Status Register (R/ ). */
+ };
+ __O uint32_t CONTROLC; /* Offset: 0x004 CONTROL Clear Register ( /W). */
+} MPS3_I2C_TypeDef;
+
+#define SDA 1 << 1
+#define SCL 1 << 0
+
+
+/******************************************************************************/
+/* Audio I2S Peripheral declaration */
+/******************************************************************************/
+
+typedef struct
+{
+ /*!< Offset: 0x000 CONTROL Register (R/W) */
+ __IO uint32_t CONTROL; /* <h> CONTROL </h>
+ * <o.0> TX Enable
+ * <0=> TX disabled
+ * <1=> TX enabled
+ * <o.1> TX IRQ Enable
+ * <0=> TX IRQ disabled
+ * <1=> TX IRQ enabled
+ * <o.2> RX Enable
+ * <0=> RX disabled
+ * <1=> RX enabled
+ * <o.3> RX IRQ Enable
+ * <0=> RX IRQ disabled
+ * <1=> RX IRQ enabled
+ * <o.10..8> TX Buffer Water Level
+ * <0=> / IRQ triggers when any space available
+ * <1=> / IRQ triggers when more than 1 space available
+ * <2=> / IRQ triggers when more than 2 space available
+ * <3=> / IRQ triggers when more than 3 space available
+ * <4=> Undefined!
+ * <5=> Undefined!
+ * <6=> Undefined!
+ * <7=> Undefined!
+ * <o.14..12> RX Buffer Water Level
+ * <0=> Undefined!
+ * <1=> / IRQ triggers when less than 1 space available
+ * <2=> / IRQ triggers when less than 2 space available
+ * <3=> / IRQ triggers when less than 3 space available
+ * <4=> / IRQ triggers when less than 4 space available
+ * <5=> Undefined!
+ * <6=> Undefined!
+ * <7=> Undefined!
+ * <o.16> FIFO reset
+ * <0=> Normal operation
+ * <1=> FIFO reset
+ * <o.17> Audio Codec reset
+ * <0=> Normal operation
+ * <1=> Assert audio Codec reset
+ */
+ /*!< Offset: 0x004 STATUS Register (R/ ) */
+ __I uint32_t STATUS; /* <h> STATUS </h>
+ * <o.0> TX Buffer alert
+ * <0=> TX buffer don't need service yet
+ * <1=> TX buffer need service
+ * <o.1> RX Buffer alert
+ * <0=> RX buffer don't need service yet
+ * <1=> RX buffer need service
+ * <o.2> TX Buffer Empty
+ * <0=> TX buffer have data
+ * <1=> TX buffer empty
+ * <o.3> TX Buffer Full
+ * <0=> TX buffer not full
+ * <1=> TX buffer full
+ * <o.4> RX Buffer Empty
+ * <0=> RX buffer have data
+ * <1=> RX buffer empty
+ * <o.5> RX Buffer Full
+ * <0=> RX buffer not full
+ * <1=> RX buffer full
+ */
+ union {
+ /*!< Offset: 0x008 Error Status Register (R/ ) */
+ __I uint32_t ERROR; /* <h> ERROR </h>
+ * <o.0> TX error
+ * <0=> Okay
+ * <1=> TX overrun/underrun
+ * <o.1> RX error
+ * <0=> Okay
+ * <1=> RX overrun/underrun
+ */
+ /*!< Offset: 0x008 Error Clear Register ( /W) */
+ __O uint32_t ERRORCLR; /* <h> ERRORCLR </h>
+ * <o.0> TX error
+ * <0=> Okay
+ * <1=> Clear TX error
+ * <o.1> RX error
+ * <0=> Okay
+ * <1=> Clear RX error
+ */
+ };
+ /*!< Offset: 0x00C Divide ratio Register (R/W) */
+ __IO uint32_t DIVIDE; /* <h> Divide ratio for Left/Right clock </h>
+ * <o.9..0> TX error (default 0x80)
+ */
+ /*!< Offset: 0x010 Transmit Buffer ( /W) */
+ __O uint32_t TXBUF; /* <h> Transmit buffer </h>
+ * <o.15..0> Right channel
+ * <o.31..16> Left channel
+ */
+
+ /*!< Offset: 0x014 Receive Buffer (R/ ) */
+ __I uint32_t RXBUF; /* <h> Receive buffer </h>
+ * <o.15..0> Right channel
+ * <o.31..16> Left channel
+ */
+ uint32_t RESERVED1[186];
+ __IO uint32_t ITCR; /* <h> Integration Test Control Register </h>
+ * <o.0> ITEN
+ * <0=> Normal operation
+ * <1=> Integration Test mode enable
+ */
+ __O uint32_t ITIP1; /* <h> Integration Test Input Register 1</h>
+ * <o.0> SDIN
+ */
+ __O uint32_t ITOP1; /* <h> Integration Test Output Register 1</h>
+ * <o.0> SDOUT
+ * <o.1> SCLK
+ * <o.2> LRCK
+ * <o.3> IRQOUT
+ */
+} MPS3_I2S_TypeDef;
+
+#define I2S_CONTROL_TXEN_Pos 0
+#define I2S_CONTROL_TXEN_Msk (1UL<<I2S_CONTROL_TXEN_Pos)
+
+#define I2S_CONTROL_TXIRQEN_Pos 1
+#define I2S_CONTROL_TXIRQEN_Msk (1UL<<I2S_CONTROL_TXIRQEN_Pos)
+
+#define I2S_CONTROL_RXEN_Pos 2
+#define I2S_CONTROL_RXEN_Msk (1UL<<I2S_CONTROL_RXEN_Pos)
+
+#define I2S_CONTROL_RXIRQEN_Pos 3
+#define I2S_CONTROL_RXIRQEN_Msk (1UL<<I2S_CONTROL_RXIRQEN_Pos)
+
+#define I2S_CONTROL_TXWLVL_Pos 8
+#define I2S_CONTROL_TXWLVL_Msk (7UL<<I2S_CONTROL_TXWLVL_Pos)
+
+#define I2S_CONTROL_RXWLVL_Pos 12
+#define I2S_CONTROL_RXWLVL_Msk (7UL<<I2S_CONTROL_RXWLVL_Pos)
+/* FIFO reset. */
+#define I2S_CONTROL_FIFORST_Pos 16
+#define I2S_CONTROL_FIFORST_Msk (1UL<<I2S_CONTROL_FIFORST_Pos)
+/* Codec reset. */
+#define I2S_CONTROL_CODECRST_Pos 17
+#define I2S_CONTROL_CODECRST_Msk (1UL<<I2S_CONTROL_CODECRST_Pos)
+
+#define I2S_STATUS_TXIRQ_Pos 0
+#define I2S_STATUS_TXIRQ_Msk (1UL<<I2S_STATUS_TXIRQ_Pos)
+
+#define I2S_STATUS_RXIRQ_Pos 1
+#define I2S_STATUS_RXIRQ_Msk (1UL<<I2S_STATUS_RXIRQ_Pos)
+
+#define I2S_STATUS_TXEmpty_Pos 2
+#define I2S_STATUS_TXEmpty_Msk (1UL<<I2S_STATUS_TXEmpty_Pos)
+
+#define I2S_STATUS_TXFull_Pos 3
+#define I2S_STATUS_TXFull_Msk (1UL<<I2S_STATUS_TXFull_Pos)
+
+#define I2S_STATUS_RXEmpty_Pos 4
+#define I2S_STATUS_RXEmpty_Msk (1UL<<I2S_STATUS_RXEmpty_Pos)
+
+#define I2S_STATUS_RXFull_Pos 5
+#define I2S_STATUS_RXFull_Msk (1UL<<I2S_STATUS_RXFull_Pos)
+
+#define I2S_ERROR_TXERR_Pos 0
+#define I2S_ERROR_TXERR_Msk (1UL<<I2S_ERROR_TXERR_Pos)
+
+#define I2S_ERROR_RXERR_Pos 1
+#define I2S_ERROR_RXERR_Msk (1UL<<I2S_ERROR_RXERR_Pos)
+
+/******************************************************************************/
+/* SMSC9220 Register Definitions */
+/******************************************************************************/
+
+typedef struct /* SMSC LAN9220 */
+{
+__I uint32_t RX_DATA_PORT; /* Receive FIFO Ports (offset 0x0). */
+ uint32_t RESERVED1[0x7];
+__O uint32_t TX_DATA_PORT; /* Transmit FIFO Ports (offset 0x20). */
+ uint32_t RESERVED2[0x7];
+
+__I uint32_t RX_STAT_PORT; /* Receive FIFO status port (offset 0x40). */
+__I uint32_t RX_STAT_PEEK; /* Receive FIFO status peek (offset 0x44). */
+__I uint32_t TX_STAT_PORT; /* Transmit FIFO status port (offset 0x48). */
+__I uint32_t TX_STAT_PEEK; /* Transmit FIFO status peek (offset 0x4C). */
+
+__I uint32_t ID_REV; /* Chip ID and Revision (offset 0x50). */
+__IO uint32_t IRQ_CFG; /* Main Interrupt Configuration (offset 0x54). */
+__IO uint32_t INT_STS; /* Interrupt Status (offset 0x58). */
+__IO uint32_t INT_EN; /* Interrupt Enable Register (offset 0x5C). */
+ uint32_t RESERVED3; /* Reserved for future use (offset 0x60). */
+__I uint32_t BYTE_TEST; /* Read-only byte order testing register 87654321h (offset 0x64). */
+__IO uint32_t FIFO_INT; /* FIFO Level Interrupts (offset 0x68). */
+__IO uint32_t RX_CFG; /* Receive Configuration (offset 0x6C). */
+__IO uint32_t TX_CFG; /* Transmit Configuration (offset 0x70). */
+__IO uint32_t HW_CFG; /* Hardware Configuration (offset 0x74). */
+__IO uint32_t RX_DP_CTL; /* RX Datapath Control (offset 0x78). */
+__I uint32_t RX_FIFO_INF; /* Receive FIFO Information (offset 0x7C). */
+__I uint32_t TX_FIFO_INF; /* Transmit FIFO Information (offset 0x80). */
+__IO uint32_t PMT_CTRL; /* Power Management Control (offset 0x84). */
+__IO uint32_t GPIO_CFG; /* General Purpose IO Configuration (offset 0x88). */
+__IO uint32_t GPT_CFG; /* General Purpose Timer Configuration (offset 0x8C). */
+__I uint32_t GPT_CNT; /* General Purpose Timer Count (offset 0x90). */
+ uint32_t RESERVED4; /* Reserved for future use (offset 0x94). */
+__IO uint32_t ENDIAN; /* WORD SWAP Register (offset 0x98). */
+__I uint32_t FREE_RUN; /* Free Run Counter (offset 0x9C). */
+__I uint32_t RX_DROP; /* RX Dropped Frames Counter (offset 0xA0). */
+__IO uint32_t MAC_CSR_CMD; /* MAC CSR Synchronizer Command (offset 0xA4). */
+__IO uint32_t MAC_CSR_DATA; /* MAC CSR Synchronizer Data (offset 0xA8). */
+__IO uint32_t AFC_CFG; /* Automatic Flow Control Configuration (offset 0xAC). */
+__IO uint32_t E2P_CMD; /* EEPROM Command (offset 0xB0). */
+__IO uint32_t E2P_DATA; /* EEPROM Data (offset 0xB4). */
+
+} SMSC9220_TypeDef;
+
+/* SMSC9220 MAC Registers Indices. */
+#define SMSC9220_MAC_CR 0x1
+#define SMSC9220_MAC_ADDRH 0x2
+#define SMSC9220_MAC_ADDRL 0x3
+#define SMSC9220_MAC_HASHH 0x4
+#define SMSC9220_MAC_HASHL 0x5
+#define SMSC9220_MAC_MII_ACC 0x6
+#define SMSC9220_MAC_MII_DATA 0x7
+#define SMSC9220_MAC_FLOW 0x8
+#define SMSC9220_MAC_VLAN1 0x9
+#define SMSC9220_MAC_VLAN2 0xA
+#define SMSC9220_MAC_WUFF 0xB
+#define SMSC9220_MAC_WUCSR 0xC
+
+/* SMSC9220 PHY Registers Indices. */
+#define SMSC9220_PHY_BCONTROL 0x0
+#define SMSC9220_PHY_BSTATUS 0x1
+#define SMSC9220_PHY_ID1 0x2
+#define SMSC9220_PHY_ID2 0x3
+#define SMSC9220_PHY_ANEG_ADV 0x4
+#define SMSC9220_PHY_ANEG_LPA 0x5
+#define SMSC9220_PHY_ANEG_EXP 0x6
+#define SMSC9220_PHY_MCONTROL 0x17
+#define SMSC9220_PHY_MSTATUS 0x18
+#define SMSC9220_PHY_CSINDICATE 0x27
+#define SMSC9220_PHY_INTSRC 0x29
+#define SMSC9220_PHY_INTMASK 0x30
+#define SMSC9220_PHY_CS 0x31
+
+/******************************************************************************/
+/* Peripheral declaration */
+/******************************************************************************/
+
+#define MPS3_TS_I2C ((MPS3_I2C_TypeDef *) MPS3_I2C0_BASE )
+#define MPS3_AAIC_I2C ((MPS3_I2C_TypeDef *) MPS3_I2C1_BASE )
+#define MPS3_CAM_I2C2 ((MPS3_I2C_TypeDef *) MPS3_I2C2_BASE )
+#define MPS3_CAM_I2C3 ((MPS3_I2C_TypeDef *) MPS3_I2C3_BASE )
+#define MPS3_AAIC_I2S ((MPS3_I2S_TypeDef *) MPS3_AAIC_I2S_BASE )
+#define MPS3_FPGAIO ((MPS3_FPGAIO_TypeDef *) MPS3_FPGAIO_BASE )
+#define MPS3_SCC ((MPS3_SCC_TypeDef *) MPS3_SCC_BASE )
+#define MPS3_SSP0 ((MPS3_SSP_TypeDef *) MPS3_SSP0_BASE )
+#define MPS3_SSP1 ((MPS3_SSP_TypeDef *) MPS3_SSP1_BASE )
+#define MPS3_SSP2 ((MPS3_SSP_TypeDef *) MPS3_SSP2_BASE )
+#define MPS3_SSP3 ((MPS3_SSP_TypeDef *) MPS3_SSP3_BASE )
+#define MPS3_SSP4 ((MPS3_SSP_TypeDef *) MPS3_SSP4_BASE )
+#define SMSC9220 ((SMSC9220_TypeDef *) SMSC9220_BASE)
+
+/******************************************************************************/
+/* Secure Peripheral declaration */
+/******************************************************************************/
+
+#define SEC_TS_I2C ((MPS3_I2C_TypeDef *) SEC_MPS3_I2C0_BASE )
+#define SEC_AAIC_I2C ((MPS3_I2C_TypeDef *) SEC_MPS3_I2C1_BASE )
+#define SEC_AAIC_I2S ((MPS3_I2S_TypeDef *) SEC_MPS3_AAIC_I2S_BASE )
+#define SEC_FPGAIO ((MPS3_FPGAIO_TypeDef *) SEC_MPS3_FPGAIO_BASE )
+#define SEC_SCC ((MPS3_SCC_TypeDef *) SEC_MPS3_SCC_BASE )
+#define SEC_SSP0 ((MPS3_SSP_TypeDef *) SEC_SSP0_BASE )
+#define SEC_SSP1 ((MPS3_SSP_TypeDef *) SEC_SSP1_BASE )
+#define SEC_SSP2 ((MPS3_SSP_TypeDef *) SEC_MPS3_SSP2_BASE )
+#define SEC_SMSC9220 ((SMSC9220_TypeDef *) SEC_SMSC9220_BASE)
+
+#endif /* SMM_MPS3_H */
diff --git a/source/hal/source/platform/mps3/source/timer_mps3.c b/source/hal/source/platform/mps3/source/timer_mps3.c
new file mode 100644
index 0000000..3511883
--- /dev/null
+++ b/source/hal/source/platform/mps3/source/timer_mps3.c
@@ -0,0 +1,193 @@
+/*
+ * Copyright (c) 2022 Arm Limited. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "timer_mps3.h"
+
+#include "log_macros.h"
+#include "smm_mps3.h" /* Memory map for MPS3. */
+
+static uint64_t cpu_cycle_count = 0; /* 64-bit cpu cycle counter */
+
+/**
+ * @brief Gets the system tick triggered cycle counter for the CPU.
+ * @return 64-bit counter value.
+ **/
+static uint64_t Get_SysTick_Cycle_Count(void);
+
+/**
+ * SysTick initialisation
+ */
+static int Init_SysTick(void);
+
+void timer_reset(void)
+{
+ MPS3_FPGAIO->CLK1HZ = 0;
+ MPS3_FPGAIO->CLK100HZ = 0;
+ MPS3_FPGAIO->COUNTER = 0;
+
+ if (0 != Init_SysTick()) {
+ printf_err("Failed to initialise system tick config\n");
+ }
+ debug("system tick config ready\n");
+}
+
+base_time_counter get_time_counter(void)
+{
+ base_time_counter t = {
+ .counter_1Hz = MPS3_FPGAIO->CLK1HZ,
+ .counter_100Hz = MPS3_FPGAIO->CLK100HZ,
+ .counter_fpga = MPS3_FPGAIO->COUNTER,
+ .counter_systick = Get_SysTick_Cycle_Count()
+ };
+ debug("Timestamp:\n");
+ debug("\tCounter 1 Hz: %" PRIu32 "\n", t.counter_1Hz);
+ debug("\tCounter 100 Hz: %" PRIu32 "\n", t.counter_100Hz);
+ debug("\tCounter FPGA: %" PRIu32 "\n", t.counter_fpga);
+ debug("\tCounter CPU: %" PRIu64 "\n", t.counter_systick);
+ return t;
+}
+
+/**
+ * Please note, that there are no checks for overflow in this function => if
+ * the time elapsed has been big (in days) this could happen and is currently
+ * not handled.
+ **/
+uint32_t get_duration_milliseconds(base_time_counter *start,
+ base_time_counter *end)
+{
+ uint32_t time_elapsed = 0;
+ if (end->counter_100Hz > start->counter_100Hz) {
+ time_elapsed = (end->counter_100Hz - start->counter_100Hz) * 10;
+ } else {
+ time_elapsed = (end->counter_1Hz - start->counter_1Hz) * 1000 +
+ ((0xFFFFFFFF - start->counter_100Hz) + end->counter_100Hz + 1) * 10;
+ }
+
+ /* If the time elapsed is less than 100ms, use microseconds count to be
+ * more precise */
+ if (time_elapsed < 100) {
+ debug("Using the microsecond function instead..\n");
+ return get_duration_microseconds(start, end)/1000;
+ }
+
+ return time_elapsed;
+}
+
+/**
+ * Like the microsecond counterpart, this function could return wrong results when
+ * the counter (MAINCLK) overflows. There are no overflow counters available.
+ **/
+uint32_t get_duration_microseconds(base_time_counter *start,
+ base_time_counter *end)
+{
+ const int divisor = get_mps3_core_clock()/1000000;
+ uint32_t time_elapsed = 0;
+ if (end->counter_fpga > start->counter_fpga) {
+ time_elapsed = (end->counter_fpga - start->counter_fpga)/divisor;
+ } else {
+ time_elapsed = ((0xFFFFFFFF - end->counter_fpga)
+ + start->counter_fpga + 1)/divisor;
+ }
+ return time_elapsed;
+}
+
+uint64_t get_cycle_count_diff(base_time_counter *start,
+ base_time_counter *end)
+{
+ if (start->counter_systick > end->counter_systick) {
+ warn("start > end; counter might have overflown\n");
+ }
+ return end->counter_systick - start->counter_systick;
+}
+
+void start_cycle_counter(void)
+{
+ /* Nothing to do for FPGA */
+}
+
+void stop_cycle_counter(void)
+{
+ /* Nothing to do for FPGA */
+}
+
+void SysTick_Handler(void)
+{
+ /* Increment the cycle counter based on load value. */
+ cpu_cycle_count += SysTick->LOAD + 1;
+}
+
+/**
+ * Gets the current SysTick derived counter value
+ */
+static uint64_t Get_SysTick_Cycle_Count(void)
+{
+ uint32_t systick_val;
+
+ NVIC_DisableIRQ(SysTick_IRQn);
+ systick_val = SysTick->VAL & SysTick_VAL_CURRENT_Msk;
+ NVIC_EnableIRQ(SysTick_IRQn);
+
+ return cpu_cycle_count + (SysTick->LOAD - systick_val);
+}
+
+
+/**
+ * SysTick initialisation
+ */
+static int Init_SysTick(void)
+{
+ const uint32_t ticks_10ms = get_mps3_core_clock()/100 + 1;
+ int err = 0;
+
+ /* Reset CPU cycle count value. */
+ cpu_cycle_count = 0;
+
+ /* Changing configuration for sys tick => guard from being
+ * interrupted. */
+ NVIC_DisableIRQ(SysTick_IRQn);
+
+ /* SysTick init - this will enable interrupt too. */
+ err = SysTick_Config(ticks_10ms);
+
+ /* Enable interrupt again. */
+ NVIC_EnableIRQ(SysTick_IRQn);
+
+ /* Wait for SysTick to kick off */
+ while (!err && !SysTick->VAL) {
+ __NOP();
+ }
+
+ return err;
+}
+
+uint32_t get_mps3_core_clock(void)
+{
+ const uint32_t default_clock = 32000000 /* 32 MHz clock */;
+ static int warned_once = 0;
+ if (0 != MPS3_SCC->CFG_ACLK) {
+ if (default_clock != MPS3_SCC->CFG_ACLK) {
+ warn("System clock is different to the MPS3 config set clock.\n");
+ }
+ return MPS3_SCC->CFG_ACLK;
+ }
+
+ if (!warned_once) {
+ warn("MPS3_SCC->CFG_ACLK reads 0. Assuming default clock of %" PRIu32 "\n",
+ default_clock);
+ warned_once = 1;
+ }
+ return default_clock;
+}
\ No newline at end of file
diff --git a/source/hal/source/platform/native/CMakeLists.txt b/source/hal/source/platform/native/CMakeLists.txt
new file mode 100644
index 0000000..fef5d5e
--- /dev/null
+++ b/source/hal/source/platform/native/CMakeLists.txt
@@ -0,0 +1,76 @@
+#----------------------------------------------------------------------------
+# Copyright (c) 2022 Arm Limited. All rights reserved.
+# SPDX-License-Identifier: Apache-2.0
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#----------------------------------------------------------------------------
+
+#########################################################
+# Native target platform support library #
+#########################################################
+
+cmake_minimum_required(VERSION 3.15.6)
+
+set(PLATFORM_DRIVERS_TARGET platform_drivers)
+
+project(${PLATFORM_DRIVERS_TARGET}
+ DESCRIPTION "Platform drivers library for native target"
+ LANGUAGES C CXX)
+
+# We should not be cross-compiling
+if (${CMAKE_CROSSCOMPILING})
+ message(FATAL_ERROR "Native drivers not available when cross-compiling.")
+endif()
+
+# Create static library
+add_library(${PLATFORM_DRIVERS_TARGET} STATIC)
+
+## Include directories - public
+target_include_directories(${PLATFORM_DRIVERS_TARGET}
+ PUBLIC
+ include)
+
+## Platform sources
+target_sources(${PLATFORM_DRIVERS_TARGET}
+ PRIVATE
+ source/platform_drivers.c)
+
+## Platform definitions:
+target_compile_definitions(${PLATFORM_DRIVERS_TARGET}
+ PUBLIC
+ ACTIVATION_BUF_SRAM_SZ=0)
+
+## Platform component directory
+if (NOT DEFINED COMPONENTS_DIR)
+ set(COMPONENTS_DIR ${CMAKE_CURRENT_SOURCE_DIR}/../../components)
+endif()
+
+## Platform component: stdout
+set(STDOUT_RETARGET OFF CACHE BOOL "Retarget stdout/err to UART")
+add_subdirectory(${COMPONENTS_DIR}/stdout ${CMAKE_BINARY_DIR}/stdout)
+
+## Platform component: lcd
+add_subdirectory(${COMPONENTS_DIR}/lcd ${CMAKE_BINARY_DIR}/lcd)
+
+# Add dependencies:
+target_link_libraries(${PLATFORM_DRIVERS_TARGET}
+ PUBLIC
+ log
+ stdout
+ lcd_stubs)
+
+# Display status:
+message(STATUS "*******************************************************")
+message(STATUS "Library : " ${PLATFORM_DRIVERS_TARGET})
+message(STATUS "CMAKE_SYSTEM_PROCESSOR : " ${CMAKE_SYSTEM_PROCESSOR})
+message(STATUS "*******************************************************")
diff --git a/source/hal/source/platform/native/include/platform_drivers.h b/source/hal/source/platform/native/include/platform_drivers.h
new file mode 100644
index 0000000..d93e31c
--- /dev/null
+++ b/source/hal/source/platform/native/include/platform_drivers.h
@@ -0,0 +1,43 @@
+/*
+ * Copyright (c) 2022 Arm Limited. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef PLATFORM_DRIVERS_H
+#define PLATFORM_DRIVERS_H
+
+#include "log_macros.h" /* Logging related helpers. */
+#include "lcd_img.h" /* LCD functions */
+#include "user_input.h" /* User input function */
+
+/**
+ * @brief Initialises the platform components.
+ * @return 0 if successful, error code otherwise.
+ */
+int platform_init(void);
+
+/**
+ * @brief Teardown for platform components.
+ */
+void platform_release(void);
+
+/**
+ * @brief Sets the platform name.
+ * @param[out] name Name of the platform to be set
+ * @param[in] size Size of the input buffer
+ */
+void platform_name(char* name, size_t size);
+
+#endif /* PLATFORM_DRIVERS_H */
diff --git a/source/hal/source/platform/native/source/platform_drivers.c b/source/hal/source/platform/native/source/platform_drivers.c
new file mode 100644
index 0000000..10db99a
--- /dev/null
+++ b/source/hal/source/platform/native/source/platform_drivers.c
@@ -0,0 +1,33 @@
+/*
+ * Copyright (c) 2022 Arm Limited. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "platform_drivers.h"
+
+#include <string.h>
+
+int platform_init(void)
+{
+ return 0;
+}
+
+void platform_release(void)
+{}
+
+void platform_name(char* name, size_t size)
+{
+ strncpy(name, "native", size);
+}
\ No newline at end of file
diff --git a/source/hal/source/platform/simple/CMakeLists.txt b/source/hal/source/platform/simple/CMakeLists.txt
new file mode 100644
index 0000000..c8d4953
--- /dev/null
+++ b/source/hal/source/platform/simple/CMakeLists.txt
@@ -0,0 +1,130 @@
+#----------------------------------------------------------------------------
+# Copyright (c) 2022 Arm Limited. All rights reserved.
+# SPDX-License-Identifier: Apache-2.0
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#----------------------------------------------------------------------------
+
+#########################################################
+# A generic (simple) platform support library #
+#########################################################
+
+cmake_minimum_required(VERSION 3.15.6)
+set(PLATFORM_DRIVERS_TARGET platform_drivers)
+project(${PLATFORM_DRIVERS_TARGET}
+ DESCRIPTION "Platform drivers library for a generic target"
+ LANGUAGES C CXX ASM)
+
+# 1. We should be cross-compiling (MPS3 taregt only runs Cortex-M targets)
+if (NOT ${CMAKE_CROSSCOMPILING})
+ message(FATAL_ERROR "No ${PLATFORM_DRIVERS_TARGET} support for this target.")
+endif()
+
+# 2. Set the platform cmake descriptor file
+if (NOT DEFINED PLATFORM_CMAKE_DESCRIPTOR_FILE)
+ set(PLATFORM_CMAKE_DESCRIPTOR_FILE
+ ${CMAKE_CURRENT_SOURCE_DIR}/cmake/subsystem-profiles/simple_platform.cmake)
+endif()
+
+## Include the platform cmake descriptor file
+include(${PLATFORM_CMAKE_DESCRIPTOR_FILE})
+
+# Define target specific values here (before adding the components)
+set(UART0_BASE "0x49303000" CACHE STRING "UART base address")
+set(UART0_BAUDRATE "115200" CACHE STRING "UART baudrate")
+set(SYSTEM_CORE_CLOCK "25000000" CACHE STRING "System peripheral clock (Hz)")
+set(ACTIVATION_BUF_SRAM_SZ "0x200000" CACHE STRING "Maximum SRAM size for activation buffers")
+
+# 3. Generate sources:
+if (NOT DEFINED SOURCE_GEN_DIR)
+ set(SOURCE_GEN_DIR ${CMAKE_BINARY_DIR}/generated/bsp)
+endif()
+
+set(MEM_PROFILE_TEMPLATE ${CMAKE_CURRENT_SOURCE_DIR}/cmake/templates/peripheral_memmap.h.template)
+set(IRQ_PROFILE_TEMPLATE ${CMAKE_CURRENT_SOURCE_DIR}/cmake/templates/peripheral_irqs.h.template)
+set(MEM_REGIONS_TEMPLATE ${CMAKE_CURRENT_SOURCE_DIR}/cmake/templates/mem_regions.h.template)
+
+configure_file("${MEM_PROFILE_TEMPLATE}" "${SOURCE_GEN_DIR}/peripheral_memmap.h")
+configure_file("${IRQ_PROFILE_TEMPLATE}" "${SOURCE_GEN_DIR}/peripheral_irqs.h")
+configure_file("${MEM_REGIONS_TEMPLATE}" "${SOURCE_GEN_DIR}/mem_regions.h")
+
+# 4. Create static library
+add_library(${PLATFORM_DRIVERS_TARGET} STATIC)
+
+## Include directories - public
+target_include_directories(${PLATFORM_DRIVERS_TARGET}
+ PUBLIC
+ include
+ ${SOURCE_GEN_DIR})
+
+## Platform sources
+target_sources(${PLATFORM_DRIVERS_TARGET}
+ PRIVATE
+ source/timer_simple_platform.c
+ source/platform_drivers.c)
+
+## Directory for additional components required by generic platform:
+if (NOT DEFINED COMPONENTS_DIR)
+ set(COMPONENTS_DIR ${CMAKE_CURRENT_SOURCE_DIR}/../../components)
+endif()
+
+
+## Platform component: cmsis_device (provides generic Cortex-M start up library)
+add_subdirectory(${COMPONENTS_DIR}/cmsis_device ${CMAKE_BINARY_DIR}/cmsis_device)
+
+## Platform component: stdout
+set(STDOUT_RETARGET ON CACHE BOOL "Retarget stdout/err to UART")
+add_subdirectory(${COMPONENTS_DIR}/stdout ${CMAKE_BINARY_DIR}/stdout)
+
+## Platform component: lcd
+add_subdirectory(${COMPONENTS_DIR}/lcd ${CMAKE_BINARY_DIR}/lcd)
+
+## Compile defs
+target_compile_definitions(${PLATFORM_DRIVERS_TARGET}
+ PUBLIC
+ ACTIVATION_BUF_SRAM_SZ=${ACTIVATION_BUF_SRAM_SZ})
+
+# Add dependencies:
+target_link_libraries(${PLATFORM_DRIVERS_TARGET} PUBLIC
+ cmsis_device
+ log
+ lcd_stubs
+ $<IF:$<BOOL:STDOUT_RETARGET>,stdout_retarget_pl011,stdout>)
+
+# If Ethos-U is enabled, we need the driver library too
+if (ETHOS_U_NPU_ENABLED)
+
+ ## Platform component: Ethos-U initialization
+ add_subdirectory(${COMPONENTS_DIR}/npu ${CMAKE_BINARY_DIR}/npu)
+
+ target_link_libraries(${PLATFORM_DRIVERS_TARGET}
+ PUBLIC
+ ethos_u_npu)
+
+ if (ETHOS_U_NPU_TIMING_ADAPTER_ENABLED)
+ ## Platform component: Ethos-U timing apadpter initialization
+ add_subdirectory(${COMPONENTS_DIR}/npu_ta ${CMAKE_BINARY_DIR}/npu_ta)
+
+ target_link_libraries(${PLATFORM_DRIVERS_TARGET}
+ PUBLIC
+ ethos_u_ta)
+ endif()
+
+endif()
+
+# 5. Display status:
+message(STATUS "CMAKE_CURRENT_SOURCE_DIR: " ${CMAKE_CURRENT_SOURCE_DIR})
+message(STATUS "*******************************************************")
+message(STATUS "Library : " ${PLATFORM_DRIVERS_TARGET})
+message(STATUS "CMAKE_SYSTEM_PROCESSOR : " ${CMAKE_SYSTEM_PROCESSOR})
+message(STATUS "*******************************************************")
diff --git a/source/hal/source/platform/simple/cmake/subsystem-profiles/simple_platform.cmake b/source/hal/source/platform/simple/cmake/subsystem-profiles/simple_platform.cmake
new file mode 100644
index 0000000..e6cfef3
--- /dev/null
+++ b/source/hal/source/platform/simple/cmake/subsystem-profiles/simple_platform.cmake
@@ -0,0 +1,93 @@
+#----------------------------------------------------------------------------
+# Copyright (c) 2021 Arm Limited. All rights reserved.
+# SPDX-License-Identifier: Apache-2.0
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+# http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#----------------------------------------------------------------------------
+
+# CMake configuration file for peripheral memory map for simple platform. This is a stripped down
+# version of Arm Corstone-300 platform with minimal peripherals to be able to use Ethos-U55. However,
+# for ease of integration with Arm FastModel Tools, it uses PL011 as the UART component instead of
+# the CMSDK UART block used by the MPS3 FPGA and FVP implementations.
+###################################################################################################
+# Mem sizes #
+###################################################################################################
+set(ITCM_SIZE "0x00080000" CACHE STRING "ITCM size: 512 kiB")
+set(DTCM_BLK_SIZE "0x00020000" CACHE STRING "DTCM size: 128 kiB, 4 banks")
+set(BRAM_SIZE "0x00100000" CACHE STRING "BRAM size: 1 MiB")
+set(ISRAM0_SIZE "0x00100000" CACHE STRING "ISRAM0 size: 1 MiB")
+set(ISRAM1_SIZE "0x00100000" CACHE STRING "ISRAM1 size: 1 MiB")
+set(DDR4_BLK_SIZE "0x10000000" CACHE STRING "DDR4 block size: 256 MiB")
+
+###################################################################################################
+# Base addresses for memory regions #
+###################################################################################################
+set(ITCM_BASE_NS "0x00000000" CACHE STRING "Instruction TCM Non-Secure base address")
+set(BRAM_BASE_NS "0x01000000" CACHE STRING "CODE SRAM Non-Secure base address")
+set(DTCM0_BASE_NS "0x20000000" CACHE STRING "Data TCM block 0 Non-Secure base address")
+set(DTCM1_BASE_NS "0x20020000" CACHE STRING "Data TCM block 1 Non-Secure base address")
+set(DTCM2_BASE_NS "0x20040000" CACHE STRING "Data TCM block 2 Non-Secure base address")
+set(DTCM3_BASE_NS "0x20060000" CACHE STRING "Data TCM block 3 Non-Secure base address")
+set(ISRAM0_BASE_NS "0x21000000" CACHE STRING "Internal SRAM Area Non-Secure base address")
+set(ISRAM1_BASE_NS "0x21100000" CACHE STRING "Internal SRAM Area Non-Secure base address")
+set(QSPI_SRAM_BASE_NS "0x28000000" CACHE STRING "QSPI SRAM Non-Secure base address")
+set(DDR4_BLK0_BASE_NS "0x60000000" CACHE STRING "DDR4 block 0 Non-Secure base address")
+set(DDR4_BLK1_BASE_NS "0x80000000" CACHE STRING "DDR4 block 1 Non-Secure base address")
+set(DDR4_BLK2_BASE_NS "0xA0000000" CACHE STRING "DDR4 block 2 Non-Secure base address")
+set(DDR4_BLK3_BASE_NS "0xC0000000" CACHE STRING "DDR4 block 3 Non-Secure base address")
+
+set(ITCM_BASE_S "0x10000000" CACHE STRING "Instruction TCM Secure base address")
+set(BRAM_BASE_S "0x11000000" CACHE STRING "CODE SRAM Secure base address")
+set(DTCM0_BASE_S "0x30000000" CACHE STRING "Data TCM block 0 Secure base address")
+set(DTCM1_BASE_S "0x30020000" CACHE STRING "Data TCM block 1 Secure base address")
+set(DTCM2_BASE_S "0x30040000" CACHE STRING "Data TCM block 2 Secure base address")
+set(DTCM3_BASE_S "0x30060000" CACHE STRING "Data TCM block 3 Secure base address")
+set(ISRAM0_BASE_S "0x31000000" CACHE STRING "Internal SRAM Area Secure base address")
+set(ISRAM1_BASE_S "0x31100000" CACHE STRING "Internal SRAM Area Secure base address")
+set(DDR4_BLK0_BASE_S "0x70000000" CACHE STRING "DDR4 block 0 Secure base address")
+set(DDR4_BLK1_BASE_S "0x90000000" CACHE STRING "DDR4 block 1 Secure base address")
+set(DDR4_BLK2_BASE_S "0xB0000000" CACHE STRING "DDR4 block 2 Secure base address")
+set(DDR4_BLK3_BASE_S "0xD0000000" CACHE STRING "DDR4 block 3 Secure base address")
+
+###################################################################################################
+# Application specific config #
+###################################################################################################
+
+# This parameter is based on the linker/scatter script for simple platform. Do not change this
+# parameter in isolation.
+set(DESIGN_NAME "Simple platform" CACHE STRING "Design name")
+
+# SRAM size reserved for activation buffers
+math(EXPR ACTIVATION_BUF_SRAM_SZ "${ISRAM0_SIZE} + ${ISRAM1_SIZE}" OUTPUT_FORMAT HEXADECIMAL)
+
+
+###################################################################################################
+# Base addresses #
+###################################################################################################
+set(PL011_UART0_BASE "0x49303000" CACHE STRING "PL011 UART 0 Base Address")
+
+if (ETHOS_U_NPU_ENABLED)
+ set(ETHOS_U_NPU_BASE "0x48102000" CACHE STRING "Ethos-U NPU base address")
+ set(ETHOS_U_NPU_TA0_BASE "0x48103000" CACHE STRING "Ethos-U NPU's timing adapter 0 base address")
+ set(ETHOS_U_NPU_TA1_BASE "0x48103200" CACHE STRING "Ethos-U NPU's timing adapter 1 base address")
+ set(SEC_ETHOS_U_NPU_BASE "0x58102000" CACHE STRING "Ethos-U NPU base address")
+ set(SEC_ETHOS_U_NPU_TA0_BASE "0x58103000" CACHE STRING "Ethos-U NPU's timing adapter 0 base address")
+ set(SEC_ETHOS_U_NPU_TA1_BASE "0x58103200" CACHE STRING "Ethos-U NPU's timing adapter 1 base address")
+endif ()
+
+###################################################################################################
+# IRQ numbers #
+###################################################################################################
+if (ETHOS_U_NPU_ENABLED)
+ set(EthosU_IRQn "56" CACHE STRING "Ethos-U NPU Interrupt")
+endif ()
diff --git a/source/hal/source/platform/simple/cmake/templates/mem_regions.h.template b/source/hal/source/platform/simple/cmake/templates/mem_regions.h.template
new file mode 100644
index 0000000..72978ce
--- /dev/null
+++ b/source/hal/source/platform/simple/cmake/templates/mem_regions.h.template
@@ -0,0 +1,58 @@
+/*
+ * Copyright (c) 2021 Arm Limited. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+// Auto-generated file
+// ** DO NOT EDIT **
+
+#ifndef MEM_REGION_DEFS_H
+#define MEM_REGION_DEFS_H
+
+#cmakedefine ITCM_SIZE (@ITCM_SIZE@) /* ITCM size */
+#cmakedefine DTCM_BLK_SIZE (@DTCM_BLK_SIZE@) /* DTCM size, 4 banks of this size available */
+#cmakedefine BRAM_SIZE (@BRAM_SIZE@) /* BRAM size */
+#cmakedefine ISRAM0_SIZE (@ISRAM0_SIZE@) /* ISRAM0 size */
+#cmakedefine ISRAM1_SIZE (@ISRAM1_SIZE@) /* ISRAM1 size */
+#cmakedefine QSPI_SRAM_SIZE (@QSPI_SRAM_SIZE@) /* QSPI Flash size */
+#cmakedefine DDR4_BLK_SIZE (@DDR4_BLK_SIZE@) /* DDR4 block size */
+
+#cmakedefine ITCM_BASE_NS (@ITCM_BASE_NS@) /* Instruction TCM Non-Secure base address */
+#cmakedefine BRAM_BASE_NS (@BRAM_BASE_NS@) /* CODE SRAM Non-Secure base address */
+#cmakedefine DTCM0_BASE_NS (@DTCM0_BASE_NS@) /* Data TCM block 0 Non-Secure base address */
+#cmakedefine DTCM1_BASE_NS (@DTCM1_BASE_NS@) /* Data TCM block 1 Non-Secure base address */
+#cmakedefine DTCM2_BASE_NS (@DTCM2_BASE_NS@) /* Data TCM block 2 Non-Secure base address */
+#cmakedefine DTCM3_BASE_NS (@DTCM3_BASE_NS@) /* Data TCM block 3 Non-Secure base address */
+#cmakedefine ISRAM0_BASE_NS (@ISRAM0_BASE_NS@) /* Internal SRAM Area Non-Secure base address */
+#cmakedefine ISRAM1_BASE_NS (@ISRAM1_BASE_NS@) /* Internal SRAM Area Non-Secure base address */
+#cmakedefine QSPI_SRAM_BASE_NS (@QSPI_SRAM_BASE_NS@) /* QSPI SRAM Non-Secure base address */
+#cmakedefine DDR4_BLK0_BASE_NS (@DDR4_BLK0_BASE_NS@) /* DDR4 block 0 Non-Secure base address */
+#cmakedefine DDR4_BLK1_BASE_NS (@DDR4_BLK1_BASE_NS@) /* DDR4 block 1 Non-Secure base address */
+#cmakedefine DDR4_BLK2_BASE_NS (@DDR4_BLK2_BASE_NS@) /* DDR4 block 2 Non-Secure base address */
+#cmakedefine DDR4_BLK3_BASE_NS (@DDR4_BLK3_BASE_NS@) /* DDR4 block 3 Non-Secure base address */
+
+#cmakedefine ITCM_BASE_S (@ITCM_BASE_S@) /* Instruction TCM Secure base address */
+#cmakedefine BRAM_BASE_S (@BRAM_BASE_S@) /* CODE SRAM Secure base address */
+#cmakedefine DTCM0_BASE_S (@DTCM0_BASE_S@) /* Data TCM block 0 Secure base address */
+#cmakedefine DTCM1_BASE_S (@DTCM1_BASE_S@) /* Data TCM block 1 Secure base address */
+#cmakedefine DTCM2_BASE_S (@DTCM2_BASE_S@) /* Data TCM block 2 Secure base address */
+#cmakedefine DTCM3_BASE_S (@DTCM3_BASE_S@) /* Data TCM block 3 Secure base address */
+#cmakedefine ISRAM0_BASE_S (@ISRAM0_BASE_S@) /* Internal SRAM Area Secure base address */
+#cmakedefine ISRAM1_BASE_S (@ISRAM1_BASE_S@) /* Internal SRAM Area Secure base address */
+#cmakedefine DDR4_BLK0_BASE_S (@DDR4_BLK0_BASE_S@) /* DDR4 block 0 Secure base address */
+#cmakedefine DDR4_BLK1_BASE_S (@DDR4_BLK1_BASE_S@) /* DDR4 block 1 Secure base address */
+#cmakedefine DDR4_BLK2_BASE_S (@DDR4_BLK2_BASE_S@) /* DDR4 block 2 Secure base address */
+#cmakedefine DDR4_BLK3_BASE_S (@DDR4_BLK3_BASE_S@) /* DDR4 block 3 Secure base address */
+
+#endif /* MEM_REGION_DEFS_H */
diff --git a/source/hal/source/platform/simple/cmake/templates/peripheral_irqs.h.template b/source/hal/source/platform/simple/cmake/templates/peripheral_irqs.h.template
new file mode 100644
index 0000000..8126cb4
--- /dev/null
+++ b/source/hal/source/platform/simple/cmake/templates/peripheral_irqs.h.template
@@ -0,0 +1,29 @@
+/*
+ * Copyright (c) 2021 Arm Limited. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+// Auto-generated file
+// ** DO NOT EDIT **
+
+#ifndef PERIPHERAL_IRQS_H
+#define PERIPHERAL_IRQS_H
+
+/******************************************************************************/
+/* Peripheral interrupt numbers */
+/******************************************************************************/
+
+#cmakedefine EthosU_IRQn (@EthosU_IRQn@) /* Ethos-Uxx Interrupt */
+
+#endif /* PERIPHERAL_IRQS_H */
diff --git a/source/hal/source/platform/simple/cmake/templates/peripheral_memmap.h.template b/source/hal/source/platform/simple/cmake/templates/peripheral_memmap.h.template
new file mode 100644
index 0000000..2bfaafc
--- /dev/null
+++ b/source/hal/source/platform/simple/cmake/templates/peripheral_memmap.h.template
@@ -0,0 +1,42 @@
+/*
+ * Copyright (c) 2021 Arm Limited. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+// Auto-generated file
+// ** DO NOT EDIT **
+
+#ifndef PERIPHERAL_MEMMAP_H
+#define PERIPHERAL_MEMMAP_H
+
+#cmakedefine DESIGN_NAME "@DESIGN_NAME@"
+
+/******************************************************************************/
+/* Peripheral memory map */
+/******************************************************************************/
+#cmakedefine PL011_UART0_BASE (@PL011_UART0_BASE@) /* PL011 UART0 Base Address */
+
+#cmakedefine ETHOS_U_NPU_BASE (@ETHOS_U_NPU_BASE@) /* Ethos-U NPU base address*/
+#cmakedefine ETHOS_U_NPU_TA0_BASE (@ETHOS_U_NPU_TA0_BASE@) /* Ethos-U NPU's timing adapter 0 base address */
+#cmakedefine ETHOS_U_NPU_TA1_BASE (@ETHOS_U_NPU_TA1_BASE@) /* Ethos-U NPU's timing adapter 1 base address */
+
+/******************************************************************************/
+/* Secure Peripheral memory map */
+/******************************************************************************/
+
+#cmakedefine SEC_ETHOS_U_NPU_BASE (@SEC_ETHOS_U_NPU_BASE@) /* Ethos-U NPU base address*/
+#cmakedefine SEC_ETHOS_U_NPU_TA0_BASE (@SEC_ETHOS_U_NPU_TA0_BASE@) /* Ethos-U NPU's timing adapter 0 base address */
+#cmakedefine SEC_ETHOS_U_NPU_TA1_BASE (@SEC_ETHOS_U_NPU_TA1_BASE@) /* Ethos-U NPU's timing adapter 1 base address */
+
+#endif /* PERIPHERAL_MEMMAP_H */
diff --git a/source/hal/source/platform/simple/cmake/templates/timing_adapter_settings.template b/source/hal/source/platform/simple/cmake/templates/timing_adapter_settings.template
new file mode 100644
index 0000000..d5e202a
--- /dev/null
+++ b/source/hal/source/platform/simple/cmake/templates/timing_adapter_settings.template
@@ -0,0 +1,64 @@
+/*
+ * Copyright (c) 2021 Arm Limited. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+// Auto-generated file
+// ** DO NOT EDIT **
+
+#ifndef TIMING_ADAPTER_SETTINGS_H
+#define TIMING_ADAPTER_SETTINGS_H
+
+#cmakedefine TA0_BASE (@TA0_BASE@)
+#cmakedefine TA1_BASE (@TA1_BASE@)
+
+/* Timing adapter settings for AXI0 */
+#if defined(TA0_BASE)
+
+#define TA0_MAXR (@TA0_MAXR@)
+#define TA0_MAXW (@TA0_MAXW@)
+#define TA0_MAXRW (@TA0_MAXRW@)
+#define TA0_RLATENCY (@TA0_RLATENCY@)
+#define TA0_WLATENCY (@TA0_WLATENCY@)
+#define TA0_PULSE_ON (@TA0_PULSE_ON@)
+#define TA0_PULSE_OFF (@TA0_PULSE_OFF@)
+#define TA0_BWCAP (@TA0_BWCAP@)
+#define TA0_PERFCTRL (@TA0_PERFCTRL@)
+#define TA0_PERFCNT (@TA0_PERFCNT@)
+#define TA0_MODE (@TA0_MODE@)
+#define TA0_HISTBIN (@TA0_HISTBIN@)
+#define TA0_HISTCNT (@TA0_HISTCNT@)
+
+#endif /* defined(TA0_BASE) */
+
+/* Timing adapter settings for AXI1 */
+#if defined(TA1_BASE)
+
+#define TA1_MAXR (@TA1_MAXR@)
+#define TA1_MAXW (@TA1_MAXW@)
+#define TA1_MAXRW (@TA1_MAXRW@)
+#define TA1_RLATENCY (@TA1_RLATENCY@)
+#define TA1_WLATENCY (@TA1_WLATENCY@)
+#define TA1_PULSE_ON (@TA1_PULSE_ON@)
+#define TA1_PULSE_OFF (@TA1_PULSE_OFF@)
+#define TA1_BWCAP (@TA1_BWCAP@)
+#define TA1_PERFCTRL (@TA1_PERFCTRL@)
+#define TA1_PERFCNT (@TA1_PERFCNT@)
+#define TA1_MODE (@TA1_MODE@)
+#define TA1_HISTBIN (@TA1_HISTBIN@)
+#define TA1_HISTCNT (@TA1_HISTCNT@)
+
+#endif /* defined(TA1_BASE) */
+
+#endif /* TIMING_ADAPTER_SETTINGS_H */
\ No newline at end of file
diff --git a/source/hal/source/platform/simple/include/platform_drivers.h b/source/hal/source/platform/simple/include/platform_drivers.h
new file mode 100644
index 0000000..5f2ed33
--- /dev/null
+++ b/source/hal/source/platform/simple/include/platform_drivers.h
@@ -0,0 +1,47 @@
+/*
+ * Copyright (c) 2021-2022 Arm Limited. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef PLATFORM_DRIVERS_H
+#define PLATFORM_DRIVERS_H
+
+#include "log_macros.h" /* Logging related helpers. */
+
+/* Platform components */
+#include "RTE_Components.h" /* For CPU related defintiions */
+#include "timer_simple_platform.h" /* timer implementation */
+#include "user_input.h" /* User input function */
+#include "lcd_img.h" /* LCD functions */
+
+/**
+ * @brief Initialises the platform components.
+ * @return 0 if successful, error code otherwise.
+ */
+int platform_init(void);
+
+/**
+ * @brief Teardown for platform components.
+ */
+void platform_release(void);
+
+/**
+ * @brief Sets the platform name.
+ * @param[out] name Name of the platform to be set
+ * @param[in] size Size of the input buffer
+ */
+void platform_name(char* name, size_t size);
+
+#endif /* PLATFORM_DRIVERS_H */
diff --git a/source/hal/source/platform/simple/include/timer_simple_platform.h b/source/hal/source/platform/simple/include/timer_simple_platform.h
new file mode 100644
index 0000000..683a207
--- /dev/null
+++ b/source/hal/source/platform/simple/include/timer_simple_platform.h
@@ -0,0 +1,61 @@
+/*
+ * Copyright (c) 2021-2022 Arm Limited. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef TIMER_SIMPLE_PLATFORM_H
+#define TIMER_SIMPLE_PLATFORM_H
+#include <stdint.h>
+
+#include "RTE_Components.h"
+
+/* Container for timestamp for simple platform. */
+typedef struct _generic_time_counter {
+ uint64_t counter_systick;
+} base_time_counter;
+
+/**
+ * @brief Resets the counters.
+ */
+void timer_reset(void);
+
+/**
+ * @brief Gets the current counter values.
+ * @returns counter struct.
+ **/
+base_time_counter get_time_counter(void);
+
+/**
+ * @brief Gets the cycle counts elapsed between start and end.
+ * @return difference in counter values as 32 bit unsigned integer.
+ */
+uint64_t get_cycle_count_diff(base_time_counter *start, base_time_counter *end);
+
+/**
+ * @brief Enables or triggers cycle counting mechanism, if required
+ * by the platform.
+ */
+void start_cycle_counter(void);
+
+/**
+ * @brief Stops cycle counting mechanism, if required by the platform.
+ */
+void stop_cycle_counter(void);
+
+/**
+ * @brief System tick interrupt handler.
+ **/
+void SysTick_Handler(void);
+
+#endif /* TIMER_SIMPLE_PLATFORM_H */
diff --git a/source/hal/source/platform/simple/source/platform_drivers.c b/source/hal/source/platform/simple/source/platform_drivers.c
new file mode 100644
index 0000000..19c0057
--- /dev/null
+++ b/source/hal/source/platform/simple/source/platform_drivers.c
@@ -0,0 +1,80 @@
+/*
+ * Copyright (c) 2022 Arm Limited. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "platform_drivers.h"
+
+#include "uart_stdout.h"
+#include "peripheral_memmap.h"
+
+
+#include <string.h>
+
+#if defined(ARM_NPU)
+#include "ethosu_npu_init.h"
+
+#if defined(ETHOS_U_NPU_TIMING_ADAPTER_ENABLED)
+#include "ethosu_ta_init.h"
+#endif /* ETHOS_U_NPU_TIMING_ADAPTER_ENABLED */
+
+#endif /* ARM_NPU */
+
+int platform_init(void)
+{
+ SystemCoreClockUpdate(); /* From start up code */
+
+ /* UART init - will enable valid use of printf (stdout
+ * re-directed at this UART (UART0) */
+ UartStdOutInit();
+
+ info("%s: complete\n", __FUNCTION__);
+
+#if defined(ARM_NPU)
+
+ int state;
+
+ /* If the platform has timing adapter blocks along with Ethos-U core
+ * block, initialise them here. */
+#if defined(ETHOS_U_NPU_TIMING_ADAPTER_ENABLED)
+ int err;
+
+ if (0 != (err = arm_ethosu_timing_adapter_init())) {
+ return err;
+ }
+#endif /* ETHOS_U_NPU_TIMING_ADAPTER_ENABLED */
+
+ /* If Arm Ethos-U NPU is to be used, we initialise it here */
+ if (0 != (state = arm_ethosu_npu_init())) {
+ return state;
+ }
+
+#endif /* ARM_NPU */
+
+ /* Print target design info */
+ info("Target system design: %s\n", DESIGN_NAME);
+
+ return 0;
+}
+
+void platform_release(void)
+{
+ __disable_irq();
+}
+
+void platform_name(char* name, size_t size)
+{
+ strncpy(name, DESIGN_NAME, size);
+}
diff --git a/source/hal/source/platform/simple/source/timer_simple_platform.c b/source/hal/source/platform/simple/source/timer_simple_platform.c
new file mode 100644
index 0000000..f7917b0
--- /dev/null
+++ b/source/hal/source/platform/simple/source/timer_simple_platform.c
@@ -0,0 +1,123 @@
+/*
+ * Copyright (c) 2021-2022 Arm Limited. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "timer_simple_platform.h"
+
+#include "log_macros.h" /* Logging macros */
+#include "RTE_Components.h" /* For CPU related defintiions */
+
+#include <inttypes.h>
+
+static uint64_t cpu_cycle_count = 0; /* 64-bit cpu cycle counter */
+extern uint32_t SystemCoreClock; /* Expected to come from the cmsis-device lib */
+
+/**
+ * @brief Gets the system tick triggered cycle counter for the CPU.
+ * @return 64-bit counter value.
+ **/
+static uint64_t Get_SysTick_Cycle_Count(void);
+
+/**
+ * SysTick initialisation
+ */
+static int Init_SysTick(void);
+
+
+base_time_counter get_time_counter(void)
+{
+ base_time_counter t = {
+ .counter_systick = Get_SysTick_Cycle_Count()
+ };
+ debug("counter_systick: %" PRIu64 "\n", t.counter_systick);
+ return t;
+}
+
+void timer_reset(void)
+{
+ if (0 != Init_SysTick()) {
+ printf_err("Failed to initialise system tick config\n");
+ }
+ debug("system tick config ready\n");
+}
+
+uint64_t get_cycle_count_diff(base_time_counter *start,
+ base_time_counter *end)
+{
+ if (start->counter_systick > end->counter_systick) {
+ warn("start > end; counter might have overflown\n");
+ }
+ return end->counter_systick - start->counter_systick;
+}
+
+void start_cycle_counter(void)
+{
+ /* Add any custom requirement for this platform here */
+}
+
+void stop_cycle_counter(void)
+{
+ /* Add any custom requirement for this platform here */
+}
+
+
+void SysTick_Handler(void)
+{
+ /* Increment the cycle counter based on load value. */
+ cpu_cycle_count += SysTick->LOAD + 1;
+}
+
+/**
+ * Gets the current SysTick derived counter value
+ */
+static uint64_t Get_SysTick_Cycle_Count(void)
+{
+ uint32_t systick_val;
+
+ NVIC_DisableIRQ(SysTick_IRQn);
+ systick_val = SysTick->VAL & SysTick_VAL_CURRENT_Msk;
+ NVIC_EnableIRQ(SysTick_IRQn);
+
+ return cpu_cycle_count + (SysTick->LOAD - systick_val);
+}
+
+/**
+ * SysTick initialisation
+ */
+static int Init_SysTick(void)
+{
+ const uint32_t ticks_10ms = SystemCoreClock/100 + 1;
+ int err = 0;
+
+ /* Reset CPU cycle count value. */
+ cpu_cycle_count = 0;
+
+ /* Changing configuration for sys tick => guard from being
+ * interrupted. */
+ NVIC_DisableIRQ(SysTick_IRQn);
+
+ /* SysTick init - this will enable interrupt too. */
+ err = SysTick_Config(ticks_10ms);
+
+ /* Enable interrupt again. */
+ NVIC_EnableIRQ(SysTick_IRQn);
+
+ /* Wait for SysTick to kick off */
+ while (!err && !SysTick->VAL) {
+ __NOP();
+ }
+
+ return err;
+}
\ No newline at end of file
diff --git a/source/hal/source/profiles/bare-metal/timer/include/platform_timer.h b/source/hal/source/profiles/bare-metal/timer/include/platform_timer.h
new file mode 100644
index 0000000..dd3934e
--- /dev/null
+++ b/source/hal/source/profiles/bare-metal/timer/include/platform_timer.h
@@ -0,0 +1,38 @@
+/*
+ * Copyright (c) 2022 Arm Limited. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef BAREMETAL_TIMER_H
+#define BAREMETAL_TIMER_H
+
+#include "platform_drivers.h"
+
+#include <stdint.h>
+#include <time.h>
+
+typedef struct bm_time_counter {
+ base_time_counter counter;
+
+#if defined (ARM_NPU)
+ uint64_t npu_total_ccnt;
+ uint32_t npu_idle_ccnt;
+ uint32_t npu_axi0_read_beats;
+ uint32_t npu_axi0_write_beats;
+ uint32_t npu_axi1_read_beats;
+#endif /* ARM_NPU */
+
+} time_counter;
+
+#endif /* BAREMETAL_TIMER_H */
diff --git a/source/hal/source/profiles/bare-metal/timer/platform_timer.c b/source/hal/source/profiles/bare-metal/timer/platform_timer.c
new file mode 100644
index 0000000..0388198
--- /dev/null
+++ b/source/hal/source/profiles/bare-metal/timer/platform_timer.c
@@ -0,0 +1,351 @@
+/*
+ * Copyright (c) 2022 Arm Limited. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "timer.h"
+#include "log_macros.h"
+#include "platform_drivers.h"
+
+#include <assert.h>
+#include <string.h>
+#include <inttypes.h>
+
+#if defined (ARM_NPU)
+
+#include "pmu_ethosu.h"
+
+extern struct ethosu_driver ethosu_drv; /* Default Ethos-U55 device driver */
+
+/**
+ * @brief Initialises the PMU and enables the cycle counter.
+ **/
+static void _init_ethosu_cyclecounter(void);
+
+/**
+ * @brief Gets the difference of total NPU cycle counts.
+ * (includes active and idle)
+ * @param[in] st Pointer to time_counter value at start time.
+ * @param[in] end Pointer to time_counter value at end.
+ * @return Total NPU cycle counts difference between the arguments expressed
+ * as unsigned 64 bit integer.
+ **/
+static uint64_t bm_get_npu_total_cycle_diff(time_counter *st,
+ time_counter *end);
+
+/**
+ * @brief Gets the difference in active NPU cycle counts.
+ * @param[in] st Pointer to time_counter value at start time.
+ * @param[in] end Pointer to time_counter value at end.
+ * @return Active NPU cycle counts difference between the arguments expressed
+ * as unsigned 64 bit integer.
+ **/
+static uint64_t bm_get_npu_active_cycle_diff(time_counter *st,
+ time_counter *end);
+
+/** @brief Gets the difference in idle NPU cycle counts
+ * @param[in] st Pointer to time_counter value at start time.
+ * @param[in] end Pointer to time_counter value at end.
+ * @return Idle NPU cycle counts difference between the arguments expressed
+ * as unsigned 64 bit integer.
+ **/
+static uint64_t bm_get_npu_idle_cycle_diff(time_counter *st,
+ time_counter *end);
+
+/** @brief Gets the difference in axi0 bus reads cycle counts
+ * @param[in] st Pointer to time_counter value at start time.
+ * @param[in] end Pointer to time_counter value at end.
+ * @return NPU AXI0 read cycle counts difference between the arguments expressed
+ * as unsigned 64 bit integer.
+ **/
+static uint64_t bm_get_npu_axi0_read_cycle_diff(time_counter *st,
+ time_counter *end);
+
+/** @brief Gets the difference in axi0 bus writes cycle counts
+ * @param[in] st Pointer to time_counter value at start time.
+ * @param[in] end Pointer to time_counter value at end.
+ * @return NPU AXI0 write cycle counts difference between the arguments expressed
+ * as unsigned 64 bit integer.
+ **/
+static uint64_t bm_get_npu_axi0_write_cycle_diff(time_counter *st,
+ time_counter *end);
+
+/** @brief Gets the difference in axi1 bus reads cycle counts
+ * @param[in] st Pointer to time_counter value at start time.
+ * @param[in] end Pointer to time_counter value at end.
+ * @return NPU AXI1 read cycle counts difference between the arguments expressed
+ * as unsigned 64 bit integer.
+ **/
+static uint64_t bm_get_npu_axi1_read_cycle_diff(time_counter *st,
+ time_counter *end);
+
+/** @brief Gets the difference for 6 collected cycle counts:
+ * 1) total NPU
+ * 2) active NPU
+ * 3) idle NPU
+ * 4) axi0 read
+ * 5) axi0 write
+ * 6) axi1 read
+ * */
+static int bm_get_npu_cycle_diff(time_counter *st, time_counter *end,
+ uint64_t* pmu_counters_values, const size_t size);
+
+#endif /* defined (ARM_NPU) */
+
+#if defined(MPS3_PLATFORM)
+/**
+ * @brief Wrapper for getting milliseconds duration between time counters
+ * @param[in] st Pointer to time_counter value at start time.
+ * @param[in] end Pointer to time_counter value at end.
+ * @return Difference in milliseconds between given time counters.
+ **/
+static time_t bm_get_duration_ms(time_counter *st, time_counter *end);
+
+/**
+ * @brief Wrapper for getting microseconds duration between time counters
+ * @param[in] st Pointer to time_counter value at start time.
+ * @param[in] end Pointer to time_counter value at end.
+ * @return Difference in microseconds between given time counters.
+ **/
+static time_t bm_get_duration_us(time_counter *st, time_counter *end);
+#endif /* defined(MPS3_PLATFORM) */
+
+/**
+ * @brief Wrapper for resetting timer.
+ **/
+static void bm_timer_reset(void);
+
+/**
+ * @brief Wrapper for getting the current timer counter.
+ * @return Current time counter value.
+ **/
+static time_counter bm_get_time_counter(void);
+
+/**
+ * @brief Wrapper for profiler start.
+ * @return Current profiler start timer counter.
+ **/
+static time_counter bm_start_profiling(void);
+
+/**
+ * @brief Wrapper for profiler end.
+ * @return Current profiler end timer counter.
+ **/
+static time_counter bm_stop_profiling(void);
+
+/**
+ * @brief Wrapper for getting CPU cycle difference between time counters.
+ * @return CPU cycle difference between given time counters expressed
+ * as unsigned 32 bit integer.
+ **/
+static uint64_t bm_get_cpu_cycles_diff(time_counter *st, time_counter *end);
+
+/**
+ * @brief Initialiser for bare metal timer.
+ * @param[in] timer Platform timer to initialize.
+ **/
+void init_timer(platform_timer *timer)
+{
+ assert(timer);
+ memset(timer, 0, sizeof(*timer));
+
+ timer->reset = bm_timer_reset;
+ timer->get_time_counter = bm_get_time_counter;
+ timer->start_profiling = bm_start_profiling;
+ timer->stop_profiling = bm_stop_profiling;
+ timer->get_cpu_cycle_diff = bm_get_cpu_cycles_diff;
+ timer->cap.cpu_cycles = 1;
+
+#if defined (MPS3_PLATFORM)
+ timer->cap.duration_ms = 1;
+ timer->cap.duration_us = 1;
+ timer->get_duration_ms = bm_get_duration_ms;
+ timer->get_duration_us = bm_get_duration_us;
+#endif /* defined (MPS3_PLATFORM) */
+
+#if defined (ARM_NPU)
+ /* We are capable of reporting npu cycle counts. */
+ timer->cap.npu_cycles = 1;
+ timer->get_npu_cycles_diff = bm_get_npu_cycle_diff;
+ _init_ethosu_cyclecounter();
+#endif /* defined (ARM_NPU) */
+
+ timer->reset();
+ timer->inited = 1;
+}
+
+#if defined (ARM_NPU)
+static void _reset_ethosu_counters()
+{
+ /* Reset all cycle and event counters. */
+ ETHOSU_PMU_CYCCNT_Reset(ðosu_drv);
+ ETHOSU_PMU_EVCNTR_ALL_Reset(ðosu_drv);
+}
+static void _init_ethosu_cyclecounter()
+{
+ /* Reset overflow status. */
+ ETHOSU_PMU_Set_CNTR_OVS(ðosu_drv, ETHOSU_PMU_CNT1_Msk | ETHOSU_PMU_CCNT_Msk);
+ /* We can retrieve only 4 PMU counters: */
+ ETHOSU_PMU_Set_EVTYPER(ðosu_drv, 0, ETHOSU_PMU_NPU_IDLE);
+ ETHOSU_PMU_Set_EVTYPER(ðosu_drv, 1, ETHOSU_PMU_AXI0_RD_DATA_BEAT_RECEIVED);
+ ETHOSU_PMU_Set_EVTYPER(ðosu_drv, 2, ETHOSU_PMU_AXI0_WR_DATA_BEAT_WRITTEN);
+ ETHOSU_PMU_Set_EVTYPER(ðosu_drv, 3, ETHOSU_PMU_AXI1_RD_DATA_BEAT_RECEIVED);
+ /* Enable PMU. */
+ ETHOSU_PMU_Enable(ðosu_drv);
+ /* Enable counters for cycle and counter# 0. */
+ ETHOSU_PMU_CNTR_Enable(ðosu_drv, ETHOSU_PMU_CNT1_Msk | ETHOSU_PMU_CNT2_Msk | ETHOSU_PMU_CNT3_Msk | ETHOSU_PMU_CNT4_Msk| ETHOSU_PMU_CCNT_Msk);
+ _reset_ethosu_counters();
+}
+
+static int bm_get_npu_cycle_diff(time_counter *st, time_counter *end,
+ uint64_t* pmu_counters_values, const size_t size)
+{
+ if (size == 6) {
+ pmu_counters_values[0] = bm_get_npu_total_cycle_diff(st, end);
+ pmu_counters_values[1] = bm_get_npu_active_cycle_diff(st, end);
+ pmu_counters_values[2] = bm_get_npu_idle_cycle_diff(st, end);
+ pmu_counters_values[3] = bm_get_npu_axi0_read_cycle_diff(st, end);
+ pmu_counters_values[4] = bm_get_npu_axi0_write_cycle_diff(st, end);
+ pmu_counters_values[5] = bm_get_npu_axi1_read_cycle_diff(st, end);
+ return 0;
+ } else {
+ return 1;
+ }
+}
+
+static uint64_t bm_get_npu_total_cycle_diff(time_counter *st, time_counter *end)
+{
+ return end->npu_total_ccnt - st->npu_total_ccnt;
+}
+
+static uint32_t counter_overflow(uint32_t pmu_counter_mask)
+{
+ /* Check for overflow: The idle counter is 32 bit while the
+ total cycle count is 64 bit. */
+ const uint32_t overflow_status = ETHOSU_PMU_Get_CNTR_OVS(ðosu_drv);
+ return pmu_counter_mask & overflow_status;
+}
+
+static uint64_t bm_get_npu_idle_cycle_diff(time_counter *st, time_counter *end)
+{
+ if (counter_overflow(ETHOSU_PMU_CNT1_Msk)) {
+ printf_err("EthosU PMU idle counter overflow.\n");
+ return 0;
+ }
+ return (uint64_t)(end->npu_idle_ccnt - st->npu_idle_ccnt);
+}
+
+static uint64_t bm_get_npu_active_cycle_diff(time_counter *st, time_counter *end)
+{
+ /* Active NPU time = total time - idle time */
+ return bm_get_npu_total_cycle_diff(st, end) - bm_get_npu_idle_cycle_diff(st, end);
+}
+
+static uint64_t bm_get_npu_axi0_read_cycle_diff(time_counter *st, time_counter *end)
+{
+ if (counter_overflow(ETHOSU_PMU_CNT2_Msk)) {
+ printf_err("EthosU PMU axi0 read counter overflow.\n");
+ return 0;
+ }
+ return (uint64_t)(end->npu_axi0_read_beats - st->npu_axi0_read_beats);
+}
+
+static uint64_t bm_get_npu_axi0_write_cycle_diff(time_counter *st, time_counter *end)
+{
+ if (counter_overflow(ETHOSU_PMU_CNT3_Msk)) {
+ printf_err("EthosU PMU axi0 write counter overflow.\n");
+ return 0;
+ }
+ return (uint64_t)(end->npu_axi0_write_beats - st->npu_axi0_write_beats);
+}
+
+static uint64_t bm_get_npu_axi1_read_cycle_diff(time_counter *st, time_counter *end)
+{
+ if (counter_overflow(ETHOSU_PMU_CNT4_Msk)) {
+ printf_err("EthosU PMU axi1 read counter overflow.\n");
+ return 0;
+ }
+ return (uint64_t)(end->npu_axi1_read_beats - st->npu_axi1_read_beats);
+}
+
+#endif /* defined (ARM_NPU) */
+
+static void bm_timer_reset(void)
+{
+#if defined (ARM_NPU)
+ _init_ethosu_cyclecounter();
+#endif /* defined (ARM_NPU) */
+
+ timer_reset();
+}
+
+static time_counter bm_get_time_counter(void)
+{
+ time_counter t = {
+ .counter = get_time_counter(),
+
+#if defined (ARM_NPU)
+ .npu_total_ccnt = ETHOSU_PMU_Get_CCNTR(ðosu_drv),
+ .npu_idle_ccnt = ETHOSU_PMU_Get_EVCNTR(ðosu_drv, 0),
+ .npu_axi0_read_beats = ETHOSU_PMU_Get_EVCNTR(ðosu_drv, 1),
+ .npu_axi0_write_beats = ETHOSU_PMU_Get_EVCNTR(ðosu_drv, 2),
+ .npu_axi1_read_beats = ETHOSU_PMU_Get_EVCNTR(ðosu_drv, 3)
+#endif /* defined (ARM_NPU) */
+
+ };
+
+#if defined (ARM_NPU)
+ debug("NPU total cc: %" PRIu64
+ "; NPU idle cc: %" PRIu32
+ "; NPU axi0 read beats: %" PRIu32
+ "; NPU axi0 write beats: %" PRIu32
+ "; NPU axi1 read beats: %" PRIu32 "\n",
+ t.npu_total_ccnt,
+ t.npu_idle_ccnt,
+ t.npu_axi0_read_beats,
+ t.npu_axi0_write_beats,
+ t.npu_axi1_read_beats);
+#endif /* defined (ARM_NPU) */
+
+ return t;
+}
+
+static time_counter bm_start_profiling(void)
+{
+ start_cycle_counter();
+ return bm_get_time_counter();
+}
+
+static time_counter bm_stop_profiling(void)
+{
+ stop_cycle_counter();
+ return bm_get_time_counter();
+}
+
+static uint64_t bm_get_cpu_cycles_diff(time_counter *st, time_counter *end)
+{
+ return get_cycle_count_diff(&(st->counter), &(end->counter));
+}
+
+#if defined(MPS3_PLATFORM)
+static time_t bm_get_duration_ms(time_counter *st, time_counter *end)
+{
+ return get_duration_milliseconds(&(st->counter), &(end->counter));
+}
+
+static time_t bm_get_duration_us(time_counter *st, time_counter *end)
+{
+ return get_duration_microseconds(&(st->counter), &(end->counter));
+}
+#endif /* defined(MPS3_PLATFORM) */
diff --git a/source/hal/source/profiles/native/timer/include/platform_timer.h b/source/hal/source/profiles/native/timer/include/platform_timer.h
new file mode 100644
index 0000000..df7b493
--- /dev/null
+++ b/source/hal/source/profiles/native/timer/include/platform_timer.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2021 Arm Limited. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef TIMER_H
+#define TIMER_H
+
+#include <stdint.h>
+#include <time.h>
+
+/* Container for time struct */
+typedef struct _time_counter {
+ /* Current POSIX time in secs. */
+ time_t current_secs;
+ /* Nanoseconds expired in current second. */
+ time_t current_nsecs;
+} time_counter;
+
+#endif /* TIMER_H */
\ No newline at end of file
diff --git a/source/hal/source/profiles/native/timer/platform_timer.c b/source/hal/source/profiles/native/timer/platform_timer.c
new file mode 100644
index 0000000..c311125
--- /dev/null
+++ b/source/hal/source/profiles/native/timer/platform_timer.c
@@ -0,0 +1,110 @@
+/*
+ * Copyright (c) 2021 Arm Limited. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "timer.h"
+
+#include <assert.h>
+#include <time.h>
+#include <string.h>
+
+#define MILLISECONDS_IN_SECOND 1000
+#define MICROSECONDS_IN_SECOND 1000000
+#define NANOSECONDS_IN_MILLISECOND 1000000
+#define NANOSECONDS_IN_MICROSECOND 1000
+
+/**
+ * @brief Gets the current time counter value.
+ * @return Counter value expressed in terms of time_counter struct.
+ **/
+static time_counter get_time_counter(void)
+{
+ struct timespec current_time;
+ clock_gettime(1, ¤t_time);
+ time_counter t = {
+ .current_secs = current_time.tv_sec,
+ .current_nsecs = current_time.tv_nsec
+ };
+
+ return t;
+}
+
+/**
+ * @brief Gets the time duration elapsed between start and end.
+ * @param[in] start Pointer to time_counter value at start time.
+ * @param[in] end Pointer to time_counter value at end.
+ * @return Difference in milliseconds between the arguments expressed
+ * as unsigned 32 bit integer.
+ **/
+static time_t get_duration_milliseconds(time_counter *start, time_counter *end)
+{
+ /* Convert both parts of time struct to ms then add for complete time. */
+ time_t seconds_part =
+ (end->current_secs - start->current_secs) * MILLISECONDS_IN_SECOND;
+ time_t nanoseconds_part =
+ (end->current_nsecs - start->current_nsecs) / NANOSECONDS_IN_MILLISECOND;
+
+ return seconds_part + nanoseconds_part;
+}
+
+/**
+ * @brief Gets the time duration elapsed between start and end.
+ * @param[in] start Pointer to time_counter value at start time.
+ * @param[in] end Pointer to time_counter value at end.
+ * @return Difference in microseconds between the arguments expressed
+ * as unsigned 32 bit integer.
+ **/
+static time_t get_duration_microseconds(time_counter *start, time_counter *end)
+{
+ /* Convert both parts of time struct to us then add for complete time. */
+ time_t seconds_part =
+ (end->current_secs - start->current_secs) * MICROSECONDS_IN_SECOND;
+ time_t nanoseconds_part =
+ (end->current_nsecs - start->current_nsecs) / NANOSECONDS_IN_MICROSECOND;
+
+ return seconds_part + nanoseconds_part;
+}
+
+/**
+ * @brief Stub for timer reset.
+ **/
+void reset_timer() {}
+
+/**
+ * @brief Initialise the timer for this platform.
+ **/
+void init_timer(platform_timer *timer)
+{
+ assert(timer);
+ memset(timer, 0, sizeof(*timer));
+
+ timer->get_time_counter = get_time_counter;
+ timer->start_profiling = get_time_counter;
+ timer->stop_profiling = get_time_counter;
+ timer->get_duration_ms = get_duration_milliseconds;
+ timer->cap.duration_ms = 1;
+ timer->get_duration_us = get_duration_microseconds;
+ timer->cap.duration_us = 1;
+ timer->reset = reset_timer;
+ timer->inited = 1;
+}
+
+#ifdef __cplusplus
+}
+#endif