diff --git a/source/hal/source/components/cmsis_device/CMakeLists.txt b/source/hal/source/components/cmsis_device/CMakeLists.txt
new file mode 100644
index 0000000..dcaeff5
--- /dev/null
+++ b/source/hal/source/components/cmsis_device/CMakeLists.txt
@@ -0,0 +1,89 @@
+#----------------------------------------------------------------------------
+#  Copyright (c) 2022 Arm Limited. All rights reserved.
+#  SPDX-License-Identifier: Apache-2.0
+#
+#  Licensed under the Apache License, Version 2.0 (the "License");
+#  you may not use this file except in compliance with the License.
+#  You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+#  Unless required by applicable law or agreed to in writing, software
+#  distributed under the License is distributed on an "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+#  See the License for the specific language governing permissions and
+#  limitations under the License.
+#----------------------------------------------------------------------------
+
+#########################################################
+# Generic CMSIS Start up library for Cortex-M targets   #
+#########################################################
+cmake_minimum_required(VERSION 3.15.6)
+
+set(CMSIS_DEVICE_TARGET cmsis_device)
+set(CPU_HEADER_TARGET cmsis_device_cpu_header)
+
+project(${CMSIS_DEVICE_TARGET}
+    DESCRIPTION     "Generic CMSIS start up file for Cortex-M targets"
+    LANGUAGES       C CXX ASM)
+
+# 1. We should be cross-compiling (non-native target)
+if (NOT ${CMAKE_CROSSCOMPILING})
+    message(FATAL_ERROR "No ${CMSIS_DEVICE_TARGET} support for this target.")
+endif()
+
+# 2. Check if CMSIS sources have been defined
+if (NOT DEFINED CMSIS_SRC_PATH)
+    message(FATAL_ERROR "CMSIS_SRC_PATH path should be defined for ${CMSIS_DEVICE_TARGET}.")
+endif()
+
+# 3.1 Create an interface library for CPU header only
+add_library(${CPU_HEADER_TARGET} INTERFACE)
+
+## Interface include directories:
+target_include_directories(${CPU_HEADER_TARGET}
+    INTERFACE
+    include
+    ${CMSIS_SRC_PATH}/CMSIS/Core/Include
+    ${CMSIS_SRC_PATH}/Device/ARM/${ARM_CPU}/Include
+    ${CMSIS_SRC_PATH}/Device/ARM/${ARM_CPU}/Include/Template)
+
+# 3.2 Create static library
+add_library(${CMSIS_DEVICE_TARGET} STATIC)
+
+## Sources - public
+target_sources(${CMSIS_DEVICE_TARGET}
+        PUBLIC
+        source/handlers.c)
+
+## Sources - private
+target_sources(${CMSIS_DEVICE_TARGET}
+    PRIVATE
+    ${CMSIS_SRC_PATH}/Device/ARM/${ARM_CPU}/Source/system_${ARM_CPU}.c
+    ${CMSIS_SRC_PATH}/Device/ARM/${ARM_CPU}/Source/startup_${ARM_CPU}.c)
+
+# Device definition needs to be set, is checked in source files to include correct header
+target_compile_definitions(${CMSIS_DEVICE_TARGET} PUBLIC ${ARM_CPU})
+
+# Tell linker that reset interrupt handler is our entry point
+target_link_options(
+    ${CMSIS_DEVICE_TARGET}
+    INTERFACE
+    --entry Reset_Handler)
+
+# Link libraries
+target_link_libraries(${CMSIS_DEVICE_TARGET}
+    PUBLIC
+    ${CPU_HEADER_TARGET})
+
+# Check if semihosting configuration is available
+if (COMMAND configure_semihosting)
+    configure_semihosting(${CMSIS_DEVICE_TARGET} OFF)
+endif()
+
+# 4 Display status:
+message(STATUS "CMAKE_CURRENT_SOURCE_DIR: " ${CMAKE_CURRENT_SOURCE_DIR})
+message(STATUS "*******************************************************")
+message(STATUS "Library                                : " ${CMSIS_DEVICE_TARGET})
+message(STATUS "CMAKE_SYSTEM_PROCESSOR                 : " ${CMAKE_SYSTEM_PROCESSOR})
+message(STATUS "*******************************************************")
diff --git a/source/hal/source/components/cmsis_device/include/RTE_Components.h b/source/hal/source/components/cmsis_device/include/RTE_Components.h
new file mode 100644
index 0000000..8988e9b
--- /dev/null
+++ b/source/hal/source/components/cmsis_device/include/RTE_Components.h
@@ -0,0 +1,24 @@
+/*
+ * Copyright (c) 2022 Arm Limited. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef RTE_COMPONENTS_H
+#define RTE_COMPONENTS_H
+
+#if defined(CPU_HEADER_FILE)
+#include CPU_HEADER_FILE /* Cortex M system header file from CMSIS. */
+#endif /* CPU_HEADER_FILE */
+
+#endif  /* RTE_COMPONENTS_H */
diff --git a/source/hal/source/components/cmsis_device/source/handlers.c b/source/hal/source/components/cmsis_device/source/handlers.c
new file mode 100644
index 0000000..a3119e6
--- /dev/null
+++ b/source/hal/source/components/cmsis_device/source/handlers.c
@@ -0,0 +1,152 @@
+/*
+ * Copyright (c) 2021 Arm Limited. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+#include "RTE_Components.h"
+
+#include <stdio.h>
+#include <inttypes.h>
+
+/**
+ * @brief   Dump core registers on stdout
+ */
+static void LogCoreCPURegisters(void)
+{
+    printf("CTRL    : 0x%08" PRIx32 "\n", __get_CONTROL());
+    printf("IPSR    : 0x%08" PRIx32 "\n", __get_IPSR());
+    printf("APSR    : 0x%08" PRIx32 "\n", __get_APSR());
+    printf("xPSR    : 0x%08" PRIx32 "\n", __get_xPSR());
+    printf("PSP     : 0x%08" PRIx32 "\n", __get_PSP());
+    printf("MSP     : 0x%08" PRIx32 "\n", __get_MSP());
+    printf("PRIMASK : 0x%08" PRIx32 "\n", __get_PRIMASK());
+    printf("BASEPRI : 0x%08" PRIx32 "\n", __get_BASEPRI());
+    printf("FAULTMSK: 0x%08" PRIx32 "\n", __get_FAULTMASK());
+}
+
+/**
+ * @brief   Default interrupt handler - an infinite loop.
+ **/
+__attribute__((noreturn)) static void DefaultHandler(void)
+{
+    LogCoreCPURegisters();
+    while (1) {
+        /* Without the following line, armclang may optimize away the
+         * infinite loop because it'd be without side effects and thus
+         * undefined behaviour. */
+        __ASM volatile("");
+    }
+}
+
+#define DEFAULT_HANDLER_CALL(type)              \
+    do {                                        \
+        printf("\n");                           \
+        printf("%s caught by function %s\n",    \
+             type, __FUNCTION__);               \
+        DefaultHandler();                       \
+    } while (0)
+
+#define DEFAULT_ERROR_HANDLER_CALL()            \
+            DEFAULT_HANDLER_CALL("Exception")
+
+#define DEFAULT_IRQ_HANDLER_CALL()              \
+            DEFAULT_HANDLER_CALL("Interrupt")
+
+/**
+ * Placeholder Exception Handlers for core interrupts.
+ *
+ * Weak definitions provided to be used if the user chooses not
+ * to override them.
+ **/
+
+/**
+ * @brief  Non maskable interrupt handler.
+ **/
+__attribute__((weak)) void NMI_Handler(void)
+{
+    DEFAULT_ERROR_HANDLER_CALL();
+}
+
+/**
+ * @brief  Hardfault interrupt handler.
+ **/
+__attribute__((weak)) void HardFault_Handler(void)
+{
+    DEFAULT_ERROR_HANDLER_CALL();
+}
+
+/**
+ * @brief  Memory management interrupt handler.
+ **/
+__attribute__((weak)) void MemManage_Handler(void)
+{
+    DEFAULT_IRQ_HANDLER_CALL();
+}
+
+/**
+ * @brief  Bus fault interrupt handler.
+ **/
+__attribute__((weak)) void BusFault_Handler(void)
+{
+    DEFAULT_ERROR_HANDLER_CALL();
+}
+
+/**
+ * @brief  Usage fault interrupt handler.
+ **/
+__attribute__((weak)) void UsageFault_Handler(void)
+{
+    DEFAULT_ERROR_HANDLER_CALL();
+}
+
+/**
+ * @brief  Secure access fault interrupt handler.
+ **/
+__attribute__((weak)) void SecureFault_Handler(void)
+{
+    DEFAULT_ERROR_HANDLER_CALL();
+}
+
+/**
+ * @brief  Supervisor call interrupt handler.
+ **/
+__attribute__((weak)) void SVC_Handler(void)
+{
+    DEFAULT_IRQ_HANDLER_CALL();
+}
+
+/**
+ * @brief  Debug monitor interrupt handler.
+ **/
+__attribute__((weak)) void DebugMon_Handler(void)
+{
+    DEFAULT_IRQ_HANDLER_CALL();
+}
+
+/**
+ * @brief  Pending SV call interrupt handler.
+ */
+__attribute__((weak)) void PendSV_Handler(void)
+{
+    DEFAULT_IRQ_HANDLER_CALL();
+}
+
+#ifdef __cplusplus
+}
+#endif