diff --git a/source/hal/source/components/npu/CMakeLists.txt b/source/hal/source/components/npu/CMakeLists.txt
new file mode 100644
index 0000000..804fb45
--- /dev/null
+++ b/source/hal/source/components/npu/CMakeLists.txt
@@ -0,0 +1,106 @@
+#----------------------------------------------------------------------------
+#  Copyright (c) 2022 Arm Limited. All rights reserved.
+#  SPDX-License-Identifier: Apache-2.0
+#
+#  Licensed under the Apache License, Version 2.0 (the "License");
+#  you may not use this file except in compliance with the License.
+#  You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+#  Unless required by applicable law or agreed to in writing, software
+#  distributed under the License is distributed on an "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+#  See the License for the specific language governing permissions and
+#  limitations under the License.
+#----------------------------------------------------------------------------
+
+#########################################################
+#         Ethos-U NPU initialization library            #
+#########################################################
+
+cmake_minimum_required(VERSION 3.15.6)
+set(ETHOS_U_NPU_INIT_COMPONENT ethos_u_npu)
+project(${ETHOS_U_NPU_INIT_COMPONENT}
+    DESCRIPTION     "Ethos-U NPU initialization library"
+    LANGUAGES       C CXX ASM)
+
+if (NOT DEFINED ETHOS_U_NPU_DRIVER_SRC_PATH)
+    message(FATAL_ERROR "ETHOS_U_NPU_DRIVER_SRC_PATH should"
+            " be defined when ETHOS_U_NPU_ENABLED=${ETHOS_U_NPU_ENABLED}")
+endif()
+
+# For the driver, we need to provide the CMSIS_PATH variable
+set(CMSIS_PATH ${CMSIS_SRC_PATH} CACHE PATH "Path to CMSIS directory")
+
+# Driver needs to know what MAC configuration to build for.
+if(ETHOS_U_NPU_CONFIG_ID MATCHES "^[A-Z]([0-9]+$)")
+    set(ETHOSU_MACS ${CMAKE_MATCH_1})
+else()
+    message(FATAL_ERROR "Couldn't work out Ethos-U number of MACS from ${ETHOS_U_NPU_CONFIG_ID}")
+endif()
+set(ETHOSU_TARGET_NPU_CONFIG
+        "ethos-${ETHOS_U_NPU_ID}-${ETHOSU_MACS}" CACHE STRING "Target Ethos-U configuration for driver.")
+
+## Memory mode target definition
+if (NOT DEFINED ETHOS_U_NPU_ID)
+    set(ETHOS_U_NPU_ID U55)
+endif()
+
+if (NOT DEFINED ETHOS_U_NPU_MEMORY_MODE)
+    set(ETHOS_U_NPU_MEMORY_MODE Shared_Sram)
+endif()
+
+if (ETHOS_U_NPU_MEMORY_MODE STREQUAL Sram_Only)
+    if (ETHOS_U_NPU_ID STREQUAL U55)
+        set(ETHOS_U_NPU_MEMORY_MODE_FLAG "-DETHOS_U_NPU_MEMORY_MODE=ETHOS_U_NPU_MEM_MODE_SRAM_ONLY")
+    else ()
+        message(FATAL_ERROR "Non compatible Ethos-U NPU memory mode and processor ${ETHOS_U_NPU_MEMORY_MODE} - ${ETHOS_U_NPU_ID}. `sram_only` can be used only for Ethos-U55.")
+    endif ()
+elseif (ETHOS_U_NPU_MEMORY_MODE STREQUAL Shared_Sram)
+    # Shared Sram can be used for Ethos-U55 and Ethos-U65
+    set(ETHOS_U_NPU_MEMORY_MODE_FLAG "-DETHOS_U_NPU_MEMORY_MODE=ETHOS_U_NPU_MEMORY_MODE_SHARED_SRAM")
+elseif (ETHOS_U_NPU_MEMORY_MODE STREQUAL Dedicated_Sram)
+    # Dedicated Sram is used only for Ethos-U65
+    if (ETHOS_U_NPU_ID STREQUAL U65)
+        list(APPEND ETHOS_U_NPU_MEMORY_MODE_FLAG "-DETHOS_U_NPU_MEMORY_MODE=ETHOS_U_NPU_MEMORY_MODE_DEDICATED_SRAM" "-DETHOS_U_NPU_CACHE_SIZE=${ETHOS_U_NPU_CACHE_SIZE}")
+    else ()
+        message(FATAL_ERROR "Non compatible Ethos-U NPU memory mode and processor ${ETHOS_U_NPU_MEMORY_MODE} - ${ETHOS_U_NPU_ID}. `dedicated_sram` can be used only for Ethos-U65.")
+    endif ()
+else ()
+    message(FATAL_ERROR "Non compatible Ethos-U NPU memory mode ${ETHOS_U_NPU_MEMORY_MODE}")
+endif ()
+
+add_subdirectory(${ETHOS_U_NPU_DRIVER_SRC_PATH} ${CMAKE_BINARY_DIR}/ethos-u-driver)
+
+# Create static library
+add_library(${ETHOS_U_NPU_INIT_COMPONENT} STATIC)
+
+## Include directories - public
+target_include_directories(${ETHOS_U_NPU_INIT_COMPONENT}
+    PUBLIC
+    include
+    ${SOURCE_GEN_DIR})
+
+## Component sources
+target_sources(${ETHOS_U_NPU_INIT_COMPONENT}
+    PRIVATE
+    ethosu_npu_init.c
+    ethosu_cpu_cache.c)
+
+## Add dependencies:
+target_link_libraries(${ETHOS_U_NPU_INIT_COMPONENT} PUBLIC
+    cmsis_device_cpu_header
+    ethosu_core_driver
+    log)
+
+target_compile_definitions(${ETHOS_U_NPU_INIT_COMPONENT}
+    PUBLIC
+    ARM_NPU
+    ${ETHOS_U_NPU_MEMORY_MODE_FLAG})
+
+# Display status
+message(STATUS "CMAKE_CURRENT_SOURCE_DIR: " ${CMAKE_CURRENT_SOURCE_DIR})
+message(STATUS "*******************************************************")
+message(STATUS "Library                                : " ${ETHOS_U_NPU_INIT_COMPONENT})
+message(STATUS "*******************************************************")
diff --git a/source/hal/source/components/npu/ethosu_cpu_cache.c b/source/hal/source/components/npu/ethosu_cpu_cache.c
new file mode 100644
index 0000000..13f6f0a
--- /dev/null
+++ b/source/hal/source/components/npu/ethosu_cpu_cache.c
@@ -0,0 +1,54 @@
+/*
+ * Copyright (c) 2022 Arm Limited. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ethosu_cpu_cache.h"
+
+#include "RTE_Components.h"         /* For CPU related defintiions */
+#include "ethosu_driver.h"          /* Arm Ethos-U driver header */
+#include "log_macros.h"             /* Logging macros */
+
+void ethosu_flush_dcache(uint32_t *p, size_t bytes)
+{
+#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+    if (SCB->CCR & SCB_CCR_DC_Msk) {
+        if (p) {
+            SCB_CleanDCache_by_Addr((void *) p, (int32_t) bytes);
+        } else {
+            SCB_CleanDCache();
+        }
+    }
+#else
+    UNUSED(p);
+    UNUSED(bytes);
+#endif /* defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) */
+}
+
+void ethosu_invalidate_dcache(uint32_t *p, size_t bytes)
+{
+#if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+    if (SCB->CCR & SCB_CCR_DC_Msk) {
+        if (p) {
+            SCB_InvalidateDCache_by_Addr((void *) p, (int32_t) bytes);
+        } else {
+            SCB_InvalidateDCache();
+        }
+    }
+#else
+    UNUSED(p);
+    UNUSED(bytes);
+#endif /* defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) */
+}
diff --git a/source/hal/source/components/npu/ethosu_npu_init.c b/source/hal/source/components/npu/ethosu_npu_init.c
new file mode 100644
index 0000000..9ccd887
--- /dev/null
+++ b/source/hal/source/components/npu/ethosu_npu_init.c
@@ -0,0 +1,122 @@
+/*
+ * Copyright (c) 2022 Arm Limited. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ethosu_npu_init.h"
+
+#include "RTE_Components.h"         /* For CPU related defintiions */
+#include "peripheral_memmap.h"      /* Peripheral memory map definitions. */
+#include "peripheral_irqs.h"        /* IRQ numbers for this platform. */
+#include "log_macros.h"             /* Logging functions */
+
+#include "ethosu_mem_config.h"      /* Arm Ethos-U memory config */
+#include "ethosu_driver.h"          /* Arm Ethos-U driver header */
+
+struct ethosu_driver ethosu_drv; /* Default Ethos-U device driver */
+
+#if defined(ETHOS_U_CACHE_BUF_SZ) && (ETHOS_U_CACHE_BUF_SZ > 0)
+static uint8_t cache_arena[ETHOS_U_CACHE_BUF_SZ] CACHE_BUF_ATTRIBUTE;
+#else  /* defined (ETHOS_U_CACHE_BUF_SZ) && (ETHOS_U_CACHE_BUF_SZ > 0) */
+static uint8_t *cache_arena = NULL;
+#endif /* defined (ETHOS_U_CACHE_BUF_SZ) && (ETHOS_U_CACHE_BUF_SZ > 0) */
+
+static uint8_t *get_cache_arena()
+{
+    return cache_arena;
+}
+
+static size_t get_cache_arena_size()
+{
+#if defined(ETHOS_U_CACHE_BUF_SZ) && (ETHOS_U_CACHE_BUF_SZ > 0)
+    return sizeof(cache_arena);
+#else  /* defined (ETHOS_U_CACHE_BUF_SZ) && (ETHOS_U_CACHE_BUF_SZ > 0) */
+    return 0;
+#endif /* defined (ETHOS_U_CACHE_BUF_SZ) && (ETHOS_U_CACHE_BUF_SZ > 0) */
+}
+
+/**
+ * @brief   Defines the Ethos-U interrupt handler: just a wrapper around the default
+ *          implementation.
+ **/
+static void arm_ethosu_npu_irq_handler(void)
+{
+    /* Call the default interrupt handler from the NPU driver */
+    ethosu_irq_handler(&ethosu_drv);
+}
+
+/**
+ * @brief  Initialises the NPU IRQ
+ **/
+static void arm_ethosu_npu_irq_init(void)
+{
+    const IRQn_Type ethosu_irqnum = (IRQn_Type)EthosU_IRQn;
+
+    /* Register the EthosU IRQ handler in our vector table.
+     * Note, this handler comes from the EthosU driver */
+    NVIC_SetVector(ethosu_irqnum, (uint32_t)arm_ethosu_npu_irq_handler);
+
+    /* Enable the IRQ */
+    NVIC_EnableIRQ(ethosu_irqnum);
+
+    debug("EthosU IRQ#: %u, Handler: 0x%p\n",
+          ethosu_irqnum, arm_ethosu_npu_irq_handler);
+}
+
+int arm_ethosu_npu_init(void)
+{
+    int err = 0;
+
+    /* Initialise the IRQ */
+    arm_ethosu_npu_irq_init();
+
+    /* Initialise Ethos-U device */
+    const void *ethosu_base_address = (void *)(SEC_ETHOS_U_NPU_BASE);
+
+    if (0 != (err = ethosu_init(
+                  &ethosu_drv,            /* Ethos-U driver device pointer */
+                  ethosu_base_address,    /* Ethos-U NPU's base address. */
+                  get_cache_arena(),      /* Pointer to fast mem area - NULL for U55. */
+                  get_cache_arena_size(), /* Fast mem region size. */
+                  1,                      /* Security enable. */
+                  1)))                    /* Privilege enable. */
+    {
+        printf_err("failed to initialise Ethos-U device\n");
+        return err;
+    }
+
+    info("Ethos-U device initialised\n");
+
+    /* Get Ethos-U version */
+    struct ethosu_driver_version driver_version;
+    struct ethosu_hw_info hw_info;
+
+    ethosu_get_driver_version(&driver_version);
+    ethosu_get_hw_info(&ethosu_drv, &hw_info);
+
+    info("Ethos-U version info:\n");
+    info("\tArch:       v%" PRIu32 ".%" PRIu32 ".%" PRIu32 "\n",
+         hw_info.version.arch_major_rev,
+         hw_info.version.arch_minor_rev,
+         hw_info.version.arch_patch_rev);
+    info("\tDriver:     v%" PRIu8 ".%" PRIu8 ".%" PRIu8 "\n",
+         driver_version.major,
+         driver_version.minor,
+         driver_version.patch);
+    info("\tMACs/cc:    %" PRIu32 "\n", (uint32_t)(1 << hw_info.cfg.macs_per_cc));
+    info("\tCmd stream: v%" PRIu32 "\n", hw_info.cfg.cmd_stream_version);
+
+    return 0;
+}
diff --git a/source/hal/source/components/npu/include/ethosu_cpu_cache.h b/source/hal/source/components/npu/include/ethosu_cpu_cache.h
new file mode 100644
index 0000000..9f21acf
--- /dev/null
+++ b/source/hal/source/components/npu/include/ethosu_cpu_cache.h
@@ -0,0 +1,39 @@
+/*
+ * Copyright (c) 2022 Arm Limited. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef ETHOSU_CPU_CACHE
+#define ETHOSU_CPU_CACHE
+
+#include <stdint.h>
+#include <stddef.h>
+
+/**
+ * @brief   Flush/clean the data cache by address and size. Passing NULL as p argument
+ *          expects the whole cache to be flushed.
+ * @param[in]   p       Pointer to the start address.
+ * @param[in]   bytes   Number of bytes to flush beginning at start address.
+ */
+void ethosu_flush_dcache(uint32_t *p, size_t bytes);
+
+/**
+ * @brief   Invalidate the data cache by address and size. Passing NULL as p argument
+ *          expects the whole cache to be invalidated.
+ * @param[in]   p       Pointer to the start address.
+ * @param[in]   bytes   Number of bytes to flush beginning at start address.
+ */
+void ethosu_invalidate_dcache(uint32_t *p, size_t bytes);
+
+#endif /* ETHOSU_CPU_CACHE */
diff --git a/source/hal/source/components/npu/include/ethosu_mem_config.h b/source/hal/source/components/npu/include/ethosu_mem_config.h
new file mode 100644
index 0000000..aa0cfda
--- /dev/null
+++ b/source/hal/source/components/npu/include/ethosu_mem_config.h
@@ -0,0 +1,58 @@
+/*
+ * Copyright (c) 2022 Arm Limited. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef ETHOS_U_NPU_MEM_CONFIG_H
+#define ETHOS_U_NPU_MEM_CONFIG_H
+
+#define ETHOS_U_NPU_MEMORY_MODE_SRAM_ONLY           0
+#define ETHOS_U_NPU_MEMORY_MODE_SHARED_SRAM         1
+#define ETHOS_U_NPU_MEMORY_MODE_DEDICATED_SRAM      2
+
+#define ETHOS_U_MEM_BYTE_ALIGNMENT                  16
+
+#ifndef ETHOS_U_NPU_MEMORY_MODE
+    #define ETHOS_U_NPU_MEMORY_MODE                 ETHOS_U_MEMORY_MODE_SHARED_SRAM
+#endif /* ETHOS_U_NPU_MEMORY_MODE */
+
+#if (ETHOS_U_NPU_MEMORY_MODE==ETHOS_U_NPU_MEMORY_MODE_DEDICATED_SRAM)
+    #ifndef ETHOS_U_NPU_CACHE_SIZE
+        #define ETHOS_U_CACHE_BUF_SZ                (393216U)  /* See vela doc for reference */
+    #else
+        #define ETHOS_U_CACHE_BUF_SZ                ETHOS_U_NPU_CACHE_SIZE
+    #endif /* ETHOS_U_NPU_CACHE_SIZE */
+#else
+    #define ETHOS_U_CACHE_BUF_SZ    (0U)
+#endif /* CACHE_BUF_SZ */
+
+/**
+ * Activation buffer aka tensor arena section name
+ * We have to place the tensor arena in different region based on the memory config.
+ **/
+#if (ETHOS_U_NPU_MEMORY_MODE==ETHOS_U_NPU_MEMORY_MODE_SHARED_SRAM)
+    #define ACTIVATION_BUF_SECTION      section(".bss.NoInit.activation_buf_sram")
+    #define ACTIVATION_BUF_SECTION_NAME ("SRAM")
+#elif (ETHOS_U_NPU_MEMORY_MODE==ETHOS_U_NPU_MEMORY_MODE_SRAM_ONLY)
+    #define ACTIVATION_BUF_SECTION      section(".bss.NoInit.activation_buf_sram")
+    #define ACTIVATION_BUF_SECTION_NAME ("SRAM")
+#elif (ETHOS_U_NPU_MEMORY_MODE==ETHOS_U_NPU_MEMORY_MODE_DEDICATED_SRAM)
+    #define ACTIVATION_BUF_SECTION      section("activation_buf_dram")
+    #define CACHE_BUF_SECTION           section(".bss.NoInit.ethos_u_cache")
+    #define ACTIVATION_BUF_SECTION_NAME ("DDR/DRAM")
+    #define CACHE_BUF_ATTRIBUTE         __attribute__((aligned(ETHOS_U_MEM_BYTE_ALIGNMENT), CACHE_BUF_SECTION))
+#endif
+
+#endif /* ETHOS_U_NPU_MEM_CONFIG_H */
diff --git a/source/hal/source/components/npu/include/ethosu_npu_init.h b/source/hal/source/components/npu/include/ethosu_npu_init.h
new file mode 100644
index 0000000..c562f6c
--- /dev/null
+++ b/source/hal/source/components/npu/include/ethosu_npu_init.h
@@ -0,0 +1,30 @@
+/*
+ * Copyright (c) 2022 Arm Limited. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef ETHOS_U_NPU_INIT_H
+#define ETHOS_U_NPU_INIT_H
+
+#if defined(ARM_NPU)
+
+/**
+ * @brief   Initialises the Arm Ethos-U NPU
+ * @return  0 if successful, error code otherwise
+ **/
+int arm_ethosu_npu_init(void);
+
+#endif /* ARM_NPU */
+
+#endif /* ETHOS_U_NPU_INIT_H */