/*
 * Copyright (c) 2021 Arm Limited. All rights reserved.
 * SPDX-License-Identifier: Apache-2.0
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 *     http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 */
// Auto-generated file
// ** DO NOT EDIT **

#ifndef PERIPHERAL_MEMMAP_H
#define PERIPHERAL_MEMMAP_H

#cmakedefine DESIGN_NAME              "@DESIGN_NAME@"

/******************************************************************************/
/*                         Peripheral memory map                              */
/******************************************************************************/

#cmakedefine CMSDK_GPIO0_BASE         (@CMSDK_GPIO0_BASE@)       /* User GPIO 0 Base Address   */
#cmakedefine CMSDK_GPIO1_BASE         (@CMSDK_GPIO1_BASE@)       /* User GPIO 1 Base Address   */
#cmakedefine CMSDK_GPIO2_BASE         (@CMSDK_GPIO2_BASE@)       /* User GPIO 2 Base Address   */
#cmakedefine CMSDK_GPIO3_BASE         (@CMSDK_GPIO3_BASE@)       /* User GPIO 3 Base Address   */

#cmakedefine FMC_CMDSK_GPIO_BASE0        (@FMC_CMDSK_GPIO_BASE0@)       /* FMC_CMDSK_GPIO_BASE 0 Base Address (4KB) */
#cmakedefine FMC_CMDSK_GPIO_BASE1        (@FMC_CMDSK_GPIO_BASE1@)       /* FMC_CMDSK_GPIO_BASE 1 Base Address (4KB)*/
#cmakedefine FMC_CMDSK_GPIO_BASE2        (@FMC_CMDSK_GPIO_BASE2@)       /* FMC_CMDSK_GPIO_BASE 2 Base Address (4KB)*/
#cmakedefine FMC_USER_AHB_BASE           (@FMC_USER_AHB_BASE@)          /* FMC_USER_AHB_BASE     Base Address (4KB)*/

#cmakedefine DMA0_BASE                (@DMA0_BASE@)       /* DMA0 (4KB) */
#cmakedefine DMA1_BASE                (@DMA1_BASE@)       /* DMA1 (4KB) */
#cmakedefine DMA2_BASE                (@DMA2_BASE@)       /* DMA2 (4KB) */
#cmakedefine DMA3_BASE                (@DMA3_BASE@)       /* DMA3 (4KB) */

#cmakedefine USER_APB0_BASE           (@USER_APB0_BASE@)       /* User APB0 */
#cmakedefine USER_APB1_BASE           (@USER_APB1_BASE@)       /* User APB1 */
#cmakedefine USER_APB2_BASE           (@USER_APB2_BASE@)       /* User APB2 */
#cmakedefine USER_APB3_BASE           (@USER_APB3_BASE@)       /* User APB3 */

#cmakedefine MPS3_I2C0_BASE           (@MPS3_I2C0_BASE@)       /* Touch Screen I2C Base Address */
#cmakedefine MPS3_I2C1_BASE           (@MPS3_I2C1_BASE@)       /* Audio Interface I2C Base Address */
#cmakedefine MPS3_SSP2_BASE           (@MPS3_SSP2_BASE@)       /* ADC SPI PL022 Base Address   */
#cmakedefine MPS3_SSP3_BASE           (@MPS3_SSP3_BASE@)       /* Shield 0 SPI PL022 Base Address   */

#cmakedefine MPS3_SSP4_BASE           (@MPS3_SSP4_BASE@)       /* Shield 1 SPI PL022 Base Address   */
#cmakedefine MPS3_I2C2_BASE           (@MPS3_I2C2_BASE@)       /* Shield 0 SBCon Base Address */
#cmakedefine MPS3_I2C3_BASE           (@MPS3_I2C3_BASE@)       /* Shield 1 SBCon Base Address */

#cmakedefine USER_APB_BASE            (@USER_APB_BASE@)       /* User APB Base Address */
#cmakedefine MPS3_I2C4_BASE           (@MPS3_I2C4_BASE@)       /* HDMI I2C SBCon Base Address */
#cmakedefine MPS3_I2C5_BASE           (@MPS3_I2C5_BASE@)       /* DDR EPROM I2C SBCon Base Address */
#cmakedefine MPS3_SCC_BASE            (@MPS3_SCC_BASE@)       /* SCC Base Address    */
#cmakedefine MPS3_AAIC_I2S_BASE       (@MPS3_AAIC_I2S_BASE@)       /* Audio Interface I2S Base Address */
#cmakedefine MPS3_FPGAIO_BASE         (@MPS3_FPGAIO_BASE@)       /* FPGA IO Base Address */
#cmakedefine PL011_UART0_BASE         (@PL011_UART0_BASE@)       /* PL011 UART0 Base Address */
#cmakedefine CMSDK_UART0_BASE         (@CMSDK_UART0_BASE@)       /* UART 0 Base Address */
#cmakedefine CMSDK_UART1_BASE         (@CMSDK_UART1_BASE@)       /* UART 1 Base Address */
#cmakedefine CMSDK_UART2_BASE         (@CMSDK_UART2_BASE@)       /* UART 2 Base Address */
#cmakedefine CMSDK_UART3_BASE         (@CMSDK_UART3_BASE@)       /* UART 3 Base Address Shield 0*/

#cmakedefine ETHOS_U_NPU_BASE           (@ETHOS_U_NPU_BASE@)    /* Ethos-U NPU base address*/
#cmakedefine ETHOS_U_NPU_TA0_BASE       (@ETHOS_U_NPU_TA0_BASE@)    /* Ethos-U NPU's timing adapter 0 base address */
#cmakedefine ETHOS_U_NPU_TA1_BASE       (@ETHOS_U_NPU_TA1_BASE@)    /* Ethos-U NPU's timing adapter 1 base address */

#cmakedefine CMSDK_UART4_BASE         (@CMSDK_UART4_BASE@)       /* UART 4 Base Address Shield 1*/
#cmakedefine CMSDK_UART5_BASE         (@CMSDK_UART5_BASE@)       /* UART 5 Base Address */
#cmakedefine HDMI_AUDIO_BASE          (@HDMI_AUDIO_BASE@)       /* HDMI AUDIO Base Address */
#cmakedefine CLCD_CONFIG_BASE         (@CLCD_CONFIG_BASE@)       /* CLCD CONFIG Base Address */
#cmakedefine RTC_BASE                 (@RTC_BASE@)       /* RTC Base address */
#cmakedefine SMSC9220_BASE            (@SMSC9220_BASE@)       /* Ethernet SMSC9220 Base Address */
#cmakedefine USB_BASE                 (@USB_BASE@)       /* USB Base Address */
#cmakedefine CMSDK_SDIO_BASE          (@CMSDK_SDIO_BASE@)       /* User SDIO Base Address   */
#cmakedefine MPS3_CLCD_BASE           (@MPS3_CLCD_BASE@)       /* HDLCD Base Address   */
#cmakedefine MPS3_eMMC_BASE           (@MPS3_eMMC_BASE@)       /* User eMMC Base Address   */
#cmakedefine USER_BASE                (@USER_BASE@)       /* User ? Base Address */

#cmakedefine QSPI_XIP_BASE            (@QSPI_XIP_BASE@)       /* QSPI XIP config Base Address */
#cmakedefine QSPI_WRITE_BASE          (@QSPI_WRITE_BASE@)       /* QSPI write config Base Address */

/******************************************************************************/
/*                      Secure Peripheral memory map                          */
/******************************************************************************/

#cmakedefine MPC_ISRAM0_BASE_S        (@MPC_ISRAM0_BASE_S@)       /* ISRAM0 Memory Protection Controller Secure base address */
#cmakedefine MPC_ISRAM1_BASE_S        (@MPC_ISRAM1_BASE_S@)       /* ISRAM1 Memory Protection Controller Secure base address */

#cmakedefine SEC_CMSDK_GPIO0_BASE     (@SEC_CMSDK_GPIO0_BASE@)       /* User GPIO 0 Base Address   */
#cmakedefine SEC_CMSDK_GPIO1_BASE     (@SEC_CMSDK_GPIO1_BASE@)       /* User GPIO 0 Base Address   */
#cmakedefine SEC_CMSDK_GPIO2_BASE     (@SEC_CMSDK_GPIO2_BASE@)       /* User GPIO 0 Base Address   */
#cmakedefine SEC_CMSDK_GPIO3_BASE     (@SEC_CMSDK_GPIO3_BASE@)       /* User GPIO 0 Base Address   */

#cmakedefine SEC_AHB_USER0_BASE       (@SEC_AHB_USER0_BASE@)       /* AHB USER 0 Base Address (4KB) */
#cmakedefine SEC_AHB_USER1_BASE       (@SEC_AHB_USER1_BASE@)       /* AHB USER 1 Base Address (4KB)*/
#cmakedefine SEC_AHB_USER2_BASE       (@SEC_AHB_USER2_BASE@)       /* AHB USER 2 Base Address (4KB)*/
#cmakedefine SEC_AHB_USER3_BASE       (@SEC_AHB_USER3_BASE@)       /* AHB USER 3 Base Address (4KB)*/

#cmakedefine SEC_DMA0_BASE            (@SEC_DMA0_BASE@)       /* DMA0 (4KB) */
#cmakedefine SEC_DMA1_BASE            (@SEC_DMA1_BASE@)       /* DMA1 (4KB) */
#cmakedefine SEC_DMA2_BASE            (@SEC_DMA2_BASE@)       /* DMA2 (4KB) */
#cmakedefine SEC_DMA3_BASE            (@SEC_DMA3_BASE@)       /* DMA3 (4KB) */

#cmakedefine SEC_USER_APB0_BASE       (@SEC_USER_APB0_BASE@)       /* User APB0 */
#cmakedefine SEC_USER_APB1_BASE       (@SEC_USER_APB1_BASE@)       /* User APB1 */
#cmakedefine SEC_USER_APB2_BASE       (@SEC_USER_APB2_BASE@)       /* User APB2 */
#cmakedefine SEC_USER_APB3_BASE       (@SEC_USER_APB3_BASE@)       /* User APB3 */

#cmakedefine SEC_MPS3_I2C0_BASE       (@SEC_MPS3_I2C0_BASE@)       /* Touch Screen I2C Base Address */
#cmakedefine SEC_MPS3_I2C1_BASE       (@SEC_MPS3_I2C1_BASE@)       /* Audio Interface I2C Base Address */
#cmakedefine SEC_MPS3_SSP2_BASE       (@SEC_MPS3_SSP2_BASE@)       /* ADC SPI PL022 Base Address   */
#cmakedefine SEC_MPS3_SSP3_BASE       (@SEC_MPS3_SSP3_BASE@)       /* Shield 0 SPI PL022 Base Address   */

#cmakedefine SEC_MPS3_SSP4_BASE       (@SEC_MPS3_SSP4_BASE@)       /* Shield 1 SPI PL022 Base Address   */
#cmakedefine SEC_MPS3_I2C2_BASE       (@SEC_MPS3_I2C2_BASE@)       /* Shield 0 SBCon Base Address */
#cmakedefine SEC_MPS3_I2C3_BASE       (@SEC_MPS3_I2C3_BASE@)       /* Shield 1 SBCon Base Address */

#cmakedefine SEC_MPS3_I2C4_BASE       (@SEC_MPS3_I2C4_BASE@)       /* HDMI I2C SBCon Base Address */
#cmakedefine SEC_MPS3_I2C5_BASE       (@SEC_MPS3_I2C5_BASE@)       /* DDR EPROM I2C SBCon Base Address */
#cmakedefine SEC_MPS3_SCC_BASE        (@SEC_MPS3_SCC_BASE@)       /* SCC Base Address    */
#cmakedefine SEC_MPS3_AAIC_I2S_BASE   (@SEC_MPS3_AAIC_I2S_BASE@)       /* Audio Interface I2S Base Address */
#cmakedefine SEC_MPS3_FPGAIO_BASE     (@SEC_MPS3_FPGAIO_BASE@)       /* FPGA IO Base Address */
#cmakedefine SEC_CMSDK_UART0_BASE     (@SEC_CMSDK_UART0_BASE@)       /* UART 0 Base Address */
#cmakedefine SEC_CMSDK_UART1_BASE     (@SEC_CMSDK_UART1_BASE@)       /* UART 1 Base Address */
#cmakedefine SEC_CMSDK_UART2_BASE     (@SEC_CMSDK_UART2_BASE@)       /* UART 2 Base Address */
#cmakedefine SEC_CMSDK_UART3_BASE     (@SEC_CMSDK_UART3_BASE@)       /* UART 3 Base Address Shield 0*/

#cmakedefine SEC_CMSDK_UART4_BASE     (@SEC_CMSDK_UART4_BASE@)       /* UART 4 Base Address Shield 1*/
#cmakedefine SEC_CMSDK_UART5_BASE     (@SEC_CMSDK_UART5_BASE@)       /* UART 5 Base Address */
#cmakedefine SEC_HDMI_AUDIO_BASE      (@SEC_HDMI_AUDIO_BASE@)       /* HDMI AUDIO Base Address */
#cmakedefine SEC_CLCD_CONFIG_BASE     (@SEC_CLCD_CONFIG_BASE@)       /* CLCD CONFIG Base Address */
#cmakedefine SEC_RTC_BASE             (@SEC_RTC_BASE@)       /* RTC Base address */
#cmakedefine SEC_SMSC9220_BASE        (@SEC_SMSC9220_BASE@)       /* Ethernet SMSC9220 Base Address */
#cmakedefine SEC_USB_BASE             (@SEC_USB_BASE@)       /* USB Base Address */

#cmakedefine SEC_ETHOS_U_NPU_BASE       (@SEC_ETHOS_U_NPU_BASE@)   /* Ethos-U NPU base address*/
#cmakedefine SEC_ETHOS_U_NPU_TA0_BASE   (@SEC_ETHOS_U_NPU_TA0_BASE@)   /* Ethos-U NPU's timing adapter 0 base address */
#cmakedefine SEC_ETHOS_U_NPU_TA1_BASE   (@SEC_ETHOS_U_NPU_TA1_BASE@)   /* Ethos-U NPU's timing adapter 1 base address */

#cmakedefine SEC_USER_BASE            (@SEC_USER_BASE@)       /* User ? Base Address */

#cmakedefine SEC_QSPI_XIP_BASE        (@SEC_QSPI_XIP_BASE@)       /* QSPI XIP config Base Address */
#cmakedefine SEC_QSPI_WRITE_BASE      (@SEC_QSPI_WRITE_BASE@)       /* QSPI write config Base Address */

/******************************************************************************/
/*                                  MPCs                                      */
/******************************************************************************/

#cmakedefine MPC_ISRAM0_BASE_S        (@MPC_ISRAM0_BASE_S@)       /* Internal SRAM 0 MPC */
#cmakedefine MPC_ISRAM1_BASE_S        (@MPC_ISRAM1_BASE_S@)       /* Internal SRAM 1 MPC */
#cmakedefine MPC_BRAM_BASE_S          (@MPC_BRAM_BASE_S@)       /* SRAM Memory Protection Controller Secure base address */
#cmakedefine MPC_QSPI_BASE_S          (@MPC_QSPI_BASE_S@)       /* QSPI Memory Protection Controller Secure base address */
#cmakedefine MPC_DDR4_BASE_S          (@MPC_DDR4_BASE_S@)       /* DDR4 Memory Protection Controller Secure base address */

#endif /* PERIPHERAL_MEMMAP_H */