MLECO-2984: Refactor components
* Use UART component from Ethos-U core-platform
* Components as cmake project
Change-Id: I053f3a59800abc20216e6a4df8555db357e3f21d
Signed-off-by: Isabella Gottardi <isabella.gottardi@arm.com>
diff --git a/source/hal/platform/mps3/source/device_mps3.h b/source/hal/platform/mps3/source/device_mps3.h
new file mode 100644
index 0000000..9447c07
--- /dev/null
+++ b/source/hal/platform/mps3/source/device_mps3.h
@@ -0,0 +1,37 @@
+/*
+ * Copyright (c) 2022 Arm Limited. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef DEVICE_MPS3_H
+#define DEVICE_MPS3_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdio.h>
+#include <stdint.h>
+
+/**
+ * @brief Gets the core clock set for MPS3.
+ * @return Clock value in Hz.
+ **/
+uint32_t GetMPS3CoreClock(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* DEVICE_MPS3_H */
diff --git a/source/hal/platform/mps3/source/font_9x15_h.h b/source/hal/platform/mps3/source/font_9x15_h.h
new file mode 100644
index 0000000..bbfb930
--- /dev/null
+++ b/source/hal/platform/mps3/source/font_9x15_h.h
@@ -0,0 +1,128 @@
+/*
+ * Copyright (c) 2021 Arm Limited. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+//Font Generated by MikroElektronika GLCD Font Creator 1.2.0.0
+//MikroElektrnika 2011
+//http://www.mikroe.com
+
+//GLCD FontName : Lucida_Console9x15
+//GLCD FontSize : 9x15
+
+#ifndef FONT_9x15_H_H
+#define FONT_9x15_H_H
+
+const unsigned short Font_9x15_h[] = {
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* Code for char num 32. */
+ 0x00,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x00,0x10,0x10,0x00,0x00,0x00, /* Code for char num 33. */
+ 0x44,0x44,0x44,0x44,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* Code for char num 34. */
+ 0x00,0x12,0x12,0x24,0x7F,0x24,0x28,0x48,0xFE,0x48,0x90,0x90,0x00,0x00,0x00, /* Code for char num 35. */
+ 0x10,0x7C,0x16,0x12,0x12,0x1C,0x38,0x70,0x50,0x50,0x52,0x3E,0x10,0x00,0x00, /* Code for char num 36. */
+ 0x00,0x8C,0x92,0x52,0x52,0x2C,0x10,0x08,0x68,0x94,0x92,0x92,0x62,0x00,0x00, /* Code for char num 37. */
+ 0x00,0x18,0x24,0x24,0x34,0x18,0x0C,0x12,0xB2,0xE2,0xC2,0xBC,0x00,0x00,0x00, /* Code for char num 38. */
+ 0x08,0x08,0x08,0x08,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* Code for char num 39. */
+ 0xC0,0x60,0x10,0x10,0x08,0x08,0x08,0x08,0x08,0x08,0x10,0x10,0x60,0xC0,0x00, /* Code for char num 40. */
+ 0x0C,0x18,0x20,0x20,0x40,0x40,0x40,0x40,0x40,0x40,0x20,0x20,0x18,0x0C,0x00, /* Code for char num 41. */
+ 0x00,0x10,0x92,0xEE,0x18,0x28,0x28,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* Code for char num 42. */
+ 0x00,0x00,0x00,0x00,0x10,0x10,0x10,0x10,0xFE,0x10,0x10,0x10,0x00,0x00,0x00, /* Code for char num 43. */
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x18,0x18,0x10,0x08,0x00, /* Code for char num 44. */
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x7C,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* Code for char num 45. */
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x18,0x18,0x00,0x00,0x00, /* Code for char num 46. */
+ 0x80,0x40,0x40,0x60,0x20,0x20,0x10,0x10,0x08,0x08,0x0C,0x04,0x04,0x02,0x00, /* Code for char num 47. */
+ 0x00,0x38,0x44,0x82,0x82,0x82,0x82,0x82,0x82,0x82,0x44,0x38,0x00,0x00,0x00, /* Code for char num 48. */
+ 0x00,0x10,0x1E,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0xFE,0x00,0x00,0x00, /* Code for char num 49. */
+ 0x00,0x3E,0x42,0x40,0x40,0x40,0x20,0x10,0x08,0x04,0x02,0x7E,0x00,0x00,0x00, /* Code for char num 50. */
+ 0x00,0x3C,0x40,0x40,0x40,0x60,0x38,0x40,0x40,0x40,0x40,0x3C,0x00,0x00,0x00, /* Code for char num 51. */
+ 0x00,0x20,0x30,0x28,0x24,0x24,0x22,0x21,0x7F,0x20,0x20,0x20,0x00,0x00,0x00, /* Code for char num 52. */
+ 0x00,0x7C,0x04,0x04,0x04,0x1C,0x20,0x40,0x40,0x40,0x20,0x3C,0x00,0x00,0x00, /* Code for char num 53. */
+ 0x00,0x78,0x04,0x04,0x02,0x3A,0x46,0x82,0x82,0x82,0x44,0x38,0x00,0x00,0x00, /* Code for char num 54. */
+ 0x00,0xFE,0x80,0x40,0x20,0x20,0x10,0x10,0x08,0x08,0x04,0x04,0x00,0x00,0x00, /* Code for char num 55. */
+ 0x00,0x3C,0x42,0x42,0x42,0x24,0x1C,0x62,0x42,0x42,0x42,0x3C,0x00,0x00,0x00, /* Code for char num 56. */
+ 0x00,0x38,0x44,0x82,0x82,0x82,0xC4,0xB8,0x80,0x40,0x40,0x3C,0x00,0x00,0x00, /* Code for char num 57. */
+ 0x00,0x00,0x00,0x00,0x18,0x18,0x00,0x00,0x00,0x00,0x18,0x18,0x00,0x00,0x00, /* Code for char num 58. */
+ 0x00,0x00,0x00,0x00,0x18,0x18,0x00,0x00,0x00,0x00,0x18,0x18,0x10,0x08,0x00, /* Code for char num 59. */
+ 0x00,0x00,0x00,0x00,0x80,0x60,0x10,0x0C,0x0C,0x10,0x60,0x80,0x00,0x00,0x00, /* Code for char num 60. */
+ 0x00,0x00,0x00,0x00,0x00,0x00,0xFE,0x00,0x00,0xFE,0x00,0x00,0x00,0x00,0x00, /* Code for char num 61. */
+ 0x00,0x00,0x00,0x00,0x02,0x0C,0x10,0x60,0x60,0x10,0x0C,0x02,0x00,0x00,0x00, /* Code for char num 62. */
+ 0x00,0x3E,0x42,0x42,0x40,0x20,0x10,0x08,0x08,0x00,0x08,0x08,0x00,0x00,0x00, /* Code for char num 63. */
+ 0x00,0x78,0x84,0xE2,0x92,0x8A,0x8A,0xCA,0xCA,0xB2,0xA6,0x3C,0x00,0x00,0x00, /* Code for char num 64. */
+ 0x00,0x00,0x10,0x38,0x28,0x28,0x44,0x44,0xFE,0x82,0x82,0x82,0x00,0x00,0x00, /* Code for char num 65. */
+ 0x00,0x00,0x3E,0x42,0x42,0x22,0x1E,0x22,0x42,0x42,0x42,0x3E,0x00,0x00,0x00, /* Code for char num 66. */
+ 0x00,0x00,0xF8,0x06,0x02,0x01,0x01,0x01,0x01,0x02,0x06,0xF8,0x00,0x00,0x00, /* Code for char num 67. */
+ 0x00,0x00,0x3E,0x42,0x82,0x82,0x82,0x82,0x82,0x82,0x42,0x3E,0x00,0x00,0x00, /* Code for char num 68. */
+ 0x00,0x00,0xFE,0x02,0x02,0x02,0x02,0x7E,0x02,0x02,0x02,0xFE,0x00,0x00,0x00, /* Code for char num 69. */
+ 0x00,0x00,0xFE,0x02,0x02,0x02,0x02,0x7E,0x02,0x02,0x02,0x02,0x00,0x00,0x00, /* Code for char num 70. */
+ 0x00,0x00,0xF8,0x06,0x02,0x01,0x01,0xE1,0x81,0x82,0x86,0xF8,0x00,0x00,0x00, /* Code for char num 71. */
+ 0x00,0x00,0x42,0x42,0x42,0x42,0x42,0x7E,0x42,0x42,0x42,0x42,0x00,0x00,0x00, /* Code for char num 72. */
+ 0x00,0x00,0xFE,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0xFE,0x00,0x00,0x00, /* Code for char num 73. */
+ 0x00,0x00,0x3C,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x1E,0x00,0x00,0x00, /* Code for char num 74. */
+ 0x00,0x00,0x42,0x22,0x12,0x0A,0x06,0x0A,0x12,0x22,0x42,0x82,0x00,0x00,0x00, /* Code for char num 75. */
+ 0x00,0x00,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0x02,0xFE,0x00,0x00,0x00, /* Code for char num 76. */
+ 0x00,0x00,0x63,0x63,0x63,0x55,0x55,0x55,0x4D,0x49,0x41,0x41,0x00,0x00,0x00, /* Code for char num 77. */
+ 0x00,0x00,0x82,0x86,0x8A,0x8A,0x92,0x92,0xA2,0xA2,0xC2,0x82,0x00,0x00,0x00, /* Code for char num 78. */
+ 0x00,0x00,0x3C,0x42,0x81,0x81,0x81,0x81,0x81,0x81,0x42,0x3C,0x00,0x00,0x00, /* Code for char num 79. */
+ 0x00,0x00,0x3E,0x42,0x42,0x42,0x62,0x1E,0x02,0x02,0x02,0x02,0x00,0x00,0x00, /* Code for char num 80. */
+ 0x00,0x00,0x3C,0x42,0x81,0x81,0x81,0x81,0x81,0x81,0x42,0x3C,0x60,0x80,0x00, /* Code for char num 81. */
+ 0x00,0x00,0x3E,0x42,0x42,0x42,0x22,0x1E,0x12,0x22,0x42,0x82,0x00,0x00,0x00, /* Code for char num 82. */
+ 0x00,0x00,0x7C,0x42,0x02,0x06,0x1C,0x20,0x40,0x40,0x42,0x3E,0x00,0x00,0x00, /* Code for char num 83. */
+ 0x00,0x00,0xFE,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x00,0x00,0x00, /* Code for char num 84. */
+ 0x00,0x00,0x82,0x82,0x82,0x82,0x82,0x82,0x82,0x82,0x44,0x3C,0x00,0x00,0x00, /* Code for char num 85. */
+ 0x00,0x00,0x82,0x82,0x82,0x82,0x44,0x44,0x28,0x28,0x38,0x10,0x00,0x00,0x00, /* Code for char num 86. */
+ 0x00,0x00,0x82,0x82,0x92,0x92,0xAA,0xAA,0xAA,0xAA,0x64,0x44,0x00,0x00,0x00, /* Code for char num 87. */
+ 0x00,0x00,0x82,0x82,0x44,0x28,0x10,0x10,0x28,0x44,0x82,0x82,0x00,0x00,0x00, /* Code for char num 88. */
+ 0x00,0x00,0x82,0x82,0x44,0x44,0x28,0x10,0x10,0x10,0x10,0x10,0x00,0x00,0x00, /* Code for char num 89. */
+ 0x00,0x00,0xFF,0x80,0x40,0x20,0x10,0x08,0x04,0x02,0x01,0xFF,0x00,0x00,0x00, /* Code for char num 90. */
+ 0xF8,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0xF8,0x00, /* Code for char num 91. */
+ 0x02,0x04,0x04,0x04,0x08,0x08,0x10,0x10,0x20,0x20,0x20,0x40,0x40,0x80,0x00, /* Code for char num 92. */
+ 0x3E,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x3E,0x00, /* Code for char num 93. */
+ 0x00,0x10,0x10,0x10,0x28,0x28,0x44,0x44,0x44,0x82,0x00,0x00,0x00,0x00,0x00, /* Code for char num 94. */
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xFE,0x00,0x00, /* Code for char num 95. */
+ 0x10,0x20,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, /* Code for char num 96. */
+ 0x00,0x00,0x00,0x00,0x3C,0x40,0x40,0x78,0x44,0x42,0x62,0xDC,0x00,0x00,0x00, /* Code for char num 97. */
+ 0x02,0x02,0x02,0x02,0x7A,0x46,0x82,0x82,0x82,0x82,0x46,0x3A,0x00,0x00,0x00, /* Code for char num 98. */
+ 0x00,0x00,0x00,0x00,0xF8,0x04,0x02,0x02,0x02,0x02,0x04,0xF8,0x00,0x00,0x00, /* Code for char num 99. */
+ 0x80,0x80,0x80,0x80,0xB8,0xC4,0x82,0x82,0x82,0x82,0xC4,0xBC,0x00,0x00,0x00, /* Code for char num 100. */
+ 0x00,0x00,0x00,0x00,0x38,0x44,0x42,0x7E,0x02,0x02,0x04,0x78,0x00,0x00,0x00, /* Code for char num 101. */
+ 0xF0,0x08,0x08,0x08,0xFE,0x08,0x08,0x08,0x08,0x08,0x08,0x08,0x00,0x00,0x00, /* Code for char num 102. */
+ 0x00,0x00,0x00,0x00,0xB8,0xC4,0x82,0x82,0x82,0x82,0xC4,0xBC,0x80,0x40,0x3C, /* Code for char num 103. */
+ 0x02,0x02,0x02,0x02,0x3A,0x46,0x42,0x42,0x42,0x42,0x42,0x42,0x00,0x00,0x00, /* Code for char num 104. */
+ 0x18,0x18,0x00,0x00,0x1E,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x00,0x00,0x00, /* Code for char num 105. */
+ 0x30,0x30,0x00,0x00,0x3C,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x20,0x1E, /* Code for char num 106. */
+ 0x02,0x02,0x02,0x02,0x42,0x22,0x12,0x0E,0x0A,0x12,0x22,0x42,0x00,0x00,0x00, /* Code for char num 107. */
+ 0x1E,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x00,0x00,0x00, /* Code for char num 108. */
+ 0x00,0x00,0x00,0x00,0xDA,0xB6,0x92,0x92,0x92,0x92,0x92,0x92,0x00,0x00,0x00, /* Code for char num 109. */
+ 0x00,0x00,0x00,0x00,0x3A,0x46,0x42,0x42,0x42,0x42,0x42,0x42,0x00,0x00,0x00, /* Code for char num 110. */
+ 0x00,0x00,0x00,0x00,0x38,0x44,0x82,0x82,0x82,0x82,0x44,0x38,0x00,0x00,0x00, /* Code for char num 111. */
+ 0x00,0x00,0x00,0x00,0x7A,0x46,0x82,0x82,0x82,0x82,0x46,0x3A,0x02,0x02,0x02, /* Code for char num 112. */
+ 0x00,0x00,0x00,0x00,0xB8,0xC4,0x82,0x82,0x82,0x82,0xC4,0xBC,0x80,0x80,0x80, /* Code for char num 113. */
+ 0x00,0x00,0x00,0x00,0xF4,0x8C,0x04,0x04,0x04,0x04,0x04,0x04,0x00,0x00,0x00, /* Code for char num 114. */
+ 0x00,0x00,0x00,0x00,0x7C,0x02,0x02,0x0C,0x30,0x40,0x42,0x3E,0x00,0x00,0x00, /* Code for char num 115. */
+ 0x00,0x00,0x08,0x08,0xFE,0x08,0x08,0x08,0x08,0x08,0x08,0xF0,0x00,0x00,0x00, /* Code for char num 116. */
+ 0x00,0x00,0x00,0x00,0x42,0x42,0x42,0x42,0x42,0x42,0x62,0x5C,0x00,0x00,0x00, /* Code for char num 117. */
+ 0x00,0x00,0x00,0x00,0x82,0x82,0x82,0x44,0x44,0x28,0x28,0x10,0x00,0x00,0x00, /* Code for char num 118. */
+ 0x00,0x00,0x00,0x00,0x82,0x92,0xAA,0xAA,0xAA,0xAA,0x44,0x44,0x00,0x00,0x00, /* Code for char num 119. */
+ 0x00,0x00,0x00,0x00,0x82,0x44,0x28,0x10,0x10,0x28,0x44,0x82,0x00,0x00,0x00, /* Code for char num 120. */
+ 0x00,0x00,0x00,0x00,0x82,0x82,0x82,0x44,0x44,0x28,0x28,0x10,0x10,0x0C,0x00, /* Code for char num 121. */
+ 0x00,0x00,0x00,0x00,0xFE,0x80,0x40,0x20,0x10,0x08,0x04,0xFE,0x00,0x00,0x00, /* Code for char num 122. */
+ 0xE0,0x10,0x10,0x10,0x10,0x10,0x10,0x0C,0x10,0x10,0x10,0x10,0x10,0xE0,0x00, /* Code for char num 123. */
+ 0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x10,0x00, /* Code for char num 124. */
+ 0x0E,0x10,0x10,0x10,0x10,0x10,0x10,0x60,0x10,0x10,0x10,0x10,0x10,0x0E,0x00, /* Code for char num 125. */
+ 0x00,0x00,0x00,0x00,0x00,0x00,0x62,0x92,0x8C,0x00,0x00,0x00,0x00,0x00,0x00, /* Code for char num 126. */
+ 0x00,0x00,0x00,0x07,0x05,0x05,0x05,0x05,0x05,0x05,0x07,0x00,0x00,0x00,0x00 /* Code for char num 127. */
+};
+
+
+#endif /* FONT_9x15_H_H */
diff --git a/source/hal/platform/mps3/source/glcd_mps3.c b/source/hal/platform/mps3/source/glcd_mps3.c
new file mode 100644
index 0000000..9a375f2
--- /dev/null
+++ b/source/hal/platform/mps3/source/glcd_mps3.c
@@ -0,0 +1,462 @@
+/*
+ * Copyright (c) 2022 Arm Limited. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "glcd_mps3.h"
+
+#include "log_macros.h"
+#include "font_9x15_h.h"
+#include "smm_mps3.h"
+
+#include "peripheral_memmap.h" /* Peripheral memory map definitions. */
+
+/*-------------- CLCD Controller Internal Register addresses ----------------*/
+#define CHAR_COM ((volatile unsigned int *)(CLCD_CONFIG_BASE + 0x000))
+#define CHAR_DAT ((volatile unsigned int *)(CLCD_CONFIG_BASE + 0x004))
+#define CHAR_RD ((volatile unsigned int *)(CLCD_CONFIG_BASE + 0x008))
+#define CHAR_RAW ((volatile unsigned int *)(CLCD_CONFIG_BASE + 0x00C))
+#define CHAR_MASK ((volatile unsigned int *)(CLCD_CONFIG_BASE + 0x010))
+#define CHAR_STAT ((volatile unsigned int *)(CLCD_CONFIG_BASE + 0x014))
+#define CHAR_MISC ((volatile unsigned int *)(CLCD_CONFIG_BASE + 0x04C))
+
+/*--------------- Graphic LCD interface hardware definitions -----------------*/
+/* Pin CS setting to 0 or 1 */
+#define LCD_CS(x) ((x) ? (*CHAR_MISC |= CLCD_CS_Msk) : (*CHAR_MISC &= ~CLCD_CS_Msk))
+#define LCD_RST(x) ((x) ? (*CHAR_MISC |= CLCD_RESET_Msk) : (*CHAR_MISC &= ~CLCD_RESET_Msk))
+#define LCD_BL(x) ((x) ? (*CHAR_MISC |= CLCD_BL_Msk) : (*CHAR_MISC &= ~CLCD_BL_Msk))
+
+#define BG_COLOR 0 /* Background colour */
+#define TXT_COLOR 1 /* Text colour */
+
+/**
+* Text and background colour
+*/
+static volatile unsigned short Color[2] = {Black, White};
+
+/**
+ * @brief Delay in while loop cycles.
+ * @param[in] cnt Number of while cycles to delay.
+ **/
+static void delay (int cnt)
+{
+ cnt <<= DELAY_2N;
+ while (cnt != 0) {
+ --cnt;
+ }
+}
+
+/**
+ * @brief Write a command the LCD controller.
+ * @param[in] cmd Command to be written.
+ */
+static __inline void wr_cmd(unsigned char cmd)
+{
+ LCD_CS(0);
+ *CHAR_COM = cmd;
+ LCD_CS(1);
+}
+
+/**
+ * @brief Start of data writing to the LCD controller.
+ */
+static __inline void wr_dat_start (void)
+{
+ LCD_CS(0);
+}
+
+/**
+ * @brief Stop of data writing to the LCD controller.
+ */
+static __inline void wr_dat_stop (void)
+{
+ LCD_CS(1);
+}
+
+/**
+ * @brief Data writing to the LCD controller.
+ * @param[in] dat Data to be written.
+ */
+static __inline void wr_dat_only(unsigned short dat)
+{
+ *CHAR_DAT = (dat >> 8); /* Write D8..D15 */
+ *CHAR_DAT = (dat & 0xFF); /* Write D0..D7 */
+}
+
+/**
+ * @brief Write a value to the to LCD register.
+ * @param[in] reg Register to be written.
+ * @param[in] val Value to write to the register.
+ */
+static __inline void wr_reg(unsigned char reg, unsigned short val)
+{
+ LCD_CS(0);
+ *CHAR_COM = reg;
+ wr_dat_only(val);
+ LCD_CS(1);
+}
+
+/**
+ * @brief Converts a gray value to RGB565 representation.
+ * @param[in] src_uchar Pointer to the source pixel.
+ * @return 16 bit RGB565 value.
+ */
+static inline uint16_t _GLCD_Gray8_to_RGB565(uint8_t *src_uchar)
+{
+ uint16_t val_r = (*src_uchar >> 3);
+ uint16_t val_g = (*src_uchar >> 2);
+ return ((val_r << 11) | (val_g << 5) | val_r);
+}
+
+/**
+ * @brief Converts an RGB888 value to RGB565 representation.
+ * @param[in] src_uchar Pointer to the source pixel for R (assumed to
+ * be RGB format).
+ * @return 16 bit RGB565 value.
+ */
+static inline uint16_t _GLCD_RGB888_to_RGB565(uint8_t *src_uchar)
+{
+ uint16_t val_r = (*src_uchar >> 3) & 0x1F;
+ uint16_t val_g = (*(src_uchar+1) >> 2) & 0x3F;
+ uint16_t val_b = (*(src_uchar+2) >> 3) & 0x1F;
+ return ((val_r << 11) | (val_g << 5) | val_b);
+}
+
+/* Helper typedef to encapsulate the colour conversion function
+ * signatures */
+typedef uint16_t (* std_clr_2_lcd_clr_fn)(uint8_t *src_uchar);
+
+void GLCD_SetWindow(unsigned int x, unsigned int y, unsigned int w, unsigned int h) {
+ unsigned int xe, ye;
+
+ xe = x+w-1;
+ ye = y+h-1;
+
+ wr_reg(0x02, x >> 8); /* Column address start MSB */
+ wr_reg(0x03, x & 0xFF); /* Column address start LSB */
+ wr_reg(0x04, xe >> 8); /* Column address end MSB */
+ wr_reg(0x05, xe & 0xFF); /* Column address end LSB */
+
+ wr_reg(0x06, y >> 8); /* Row address start MSB */
+ wr_reg(0x07, y & 0xFF); /* Row address start LSB */
+ wr_reg(0x08, ye >> 8); /* Row address end MSB */
+ wr_reg(0x09, ye & 0xFF); /* Row address end LSB */
+}
+
+void GLCD_WindowMax(void)
+{
+ GLCD_SetWindow (0, 0, GLCD_WIDTH, GLCD_HEIGHT);
+}
+
+void GLCD_SetTextColor(unsigned short color)
+{
+ Color[TXT_COLOR] = color;
+}
+
+void GLCD_SetBackColor(unsigned short color)
+{
+ Color[BG_COLOR] = color;
+}
+
+void GLCD_Clear(unsigned short color)
+{
+ unsigned int i;
+
+ GLCD_WindowMax();
+ wr_cmd(0x22);
+ wr_dat_start();
+
+ for(i = 0; i < (GLCD_WIDTH*GLCD_HEIGHT); ++i) {
+ wr_dat_only(color);
+ }
+ wr_dat_stop();
+}
+
+
+void GLCD_DrawChar(
+ unsigned int x, unsigned int y,
+ unsigned int cw, unsigned int ch,
+ unsigned char *c)
+{
+ unsigned int i, j, k, pixs;
+
+ /* Sanity check: out of bounds? */
+ if ((x + cw) > GLCD_WIDTH || (y + ch) > GLCD_HEIGHT) {
+ return;
+ }
+
+ GLCD_SetWindow(x, y, cw, ch);
+
+ wr_cmd(0x22);
+ wr_dat_start();
+
+ k = (cw + 7)/8;
+
+ if (k == 1) {
+ for (j = 0; j < ch; ++j) {
+ pixs = *(unsigned char *)c;
+ c += 1;
+
+ for (i = 0; i < cw; ++i) {
+ wr_dat_only (Color[(pixs >> i) & 1]);
+ }
+ }
+ }
+ else if (k == 2) {
+ for (j = 0; j < ch; ++j) {
+ pixs = *(unsigned short *)c;
+ c += 2;
+
+ for (i = 0; i < cw; ++i) {
+ wr_dat_only (Color[(pixs >> i) & 1]);
+ }
+ }
+ }
+ wr_dat_stop();
+}
+
+void GLCD_DisplayChar(
+ unsigned int ln, unsigned int col,
+ unsigned char fi, unsigned char c)
+{
+ c -= 32;
+ switch (fi) {
+ case 0: /* Font 9 x 15. */
+ GLCD_DrawChar(col * 9, ln * 15, 9, 15,
+ (unsigned char *)&Font_9x15_h[c * 15]);
+ break;
+ }
+}
+
+void GLCD_DisplayString(
+ unsigned int ln, unsigned int col,
+ unsigned char fi, char *s)
+{
+ while (*s) {
+ GLCD_DisplayChar(ln, col++, fi, *s++);
+ }
+}
+
+
+
+void GLCD_ClearLn(unsigned int ln, unsigned char fi)
+{
+ unsigned char i;
+ char buf[60];
+
+ GLCD_WindowMax();
+ switch (fi) {
+ case 0: /* Font 9x15*/
+ for (i = 0; i < (GLCD_WIDTH+8)/9; ++i) {
+ buf[i] = ' ';
+ }
+ buf[i+1] = 0;
+ break;
+ }
+ GLCD_DisplayString (ln, 0, fi, buf);
+}
+
+void GLCD_Bitmap(unsigned int x, unsigned int y,
+ unsigned int w, unsigned int h,
+ unsigned short *bitmap)
+{
+ unsigned int i;
+ unsigned short *bitmap_ptr = bitmap;
+
+ GLCD_SetWindow (x, y, w, h);
+
+ wr_cmd(0x22);
+ wr_dat_start();
+
+ for (i = 0; i < (w*h); ++i) {
+ wr_dat_only (bitmap_ptr[i]);
+ }
+ wr_dat_stop();
+}
+
+void GLCD_Image(const void *data, const uint32_t width,
+ const uint32_t height, const uint32_t channels,
+ const uint32_t pos_x, const uint32_t pos_y,
+ const uint32_t downsample_factor)
+{
+ uint32_t i, j = 0; /* for loops */
+ const uint32_t x_incr = channels * downsample_factor; /* stride. */
+ const uint32_t y_incr = channels * width * (downsample_factor - 1); /* skip rows. */
+ uint8_t* src_unsigned = (uint8_t *)data; /* temporary pointer. */
+ std_clr_2_lcd_clr_fn cvt_clr_fn = 0; /* colour conversion function. */
+
+ /* Based on number of channels, we decide which of the above functions to use. */
+ switch (channels) {
+ case 1:
+ cvt_clr_fn = _GLCD_Gray8_to_RGB565;
+ break;
+
+ case 3:
+ cvt_clr_fn = _GLCD_RGB888_to_RGB565;
+ break;
+
+ default:
+ printf_err("number of channels not supported by display\n");
+ return;
+ }
+
+ /* Set the window position expected. Note: this is integer div. */
+ GLCD_SetWindow(pos_x, pos_y,
+ width/downsample_factor, height/downsample_factor);
+ wr_cmd(0x22);
+ wr_dat_start();
+
+ /* Loop over the image. */
+ for (j = height; j != 0; j -= downsample_factor) {
+ for (i = width; i != 0; i -= downsample_factor) {
+ wr_dat_only(cvt_clr_fn(src_unsigned));
+ src_unsigned += x_incr;
+ }
+
+ /* Skip rows if needed. */
+ src_unsigned += y_incr;
+ }
+
+ wr_dat_stop();
+}
+
+void GLCD_Box(
+ unsigned int x, unsigned int y,
+ unsigned int w, unsigned int h,
+ unsigned short color)
+{
+ unsigned int i;
+
+ GLCD_SetWindow (x, y, w, h);
+
+ wr_cmd(0x22);
+ wr_dat_start();
+ for(i = 0; i < (w*h); ++i){
+ wr_dat_only (color);
+ }
+ wr_dat_stop();
+}
+
+
+void GLCD_Initialize (void)
+{
+ /* CLCD screen setup (Default CLCD screen interface state) ------------- */
+ LCD_CS(1); /* deassert nCS0. */
+ LCD_RST(1); /* deassert Reset. */
+ LCD_BL(0); /* switch off backlight. */
+
+ /* Reset CLCD screen --------------------------------------------------- */
+ LCD_RST(0); /* assert Reset. */
+ delay(1);
+ LCD_RST(1); /* deassert Reset. */
+ delay(10);
+
+ /* Driving ability settings ----------------------------------------------*/
+ wr_reg(0xEA, 0x00); /* Power control internal used (1). */
+ wr_reg(0xEB, 0x20); /* Power control internal used (2). */
+ wr_reg(0xEC, 0x0C); /* Source control internal used (1). */
+ wr_reg(0xED, 0xC7); /* Source control internal used (2). */
+ wr_reg(0xE8, 0x38); /* Source output period Normal mode. */
+ wr_reg(0xE9, 0x10); /* Source output period Idle mode. */
+ wr_reg(0xF1, 0x01); /* RGB 18-bit interface ;0x0110. */
+ wr_reg(0xF2, 0x10);
+
+ /* Adjust the Gamma Curve ------------------------------------------------*/
+ wr_reg(0x40, 0x01);
+ wr_reg(0x41, 0x00);
+ wr_reg(0x42, 0x00);
+ wr_reg(0x43, 0x10);
+ wr_reg(0x44, 0x0E);
+ wr_reg(0x45, 0x24);
+ wr_reg(0x46, 0x04);
+ wr_reg(0x47, 0x50);
+ wr_reg(0x48, 0x02);
+ wr_reg(0x49, 0x13);
+ wr_reg(0x4A, 0x19);
+ wr_reg(0x4B, 0x19);
+ wr_reg(0x4C, 0x16);
+
+ wr_reg(0x50, 0x1B);
+ wr_reg(0x51, 0x31);
+ wr_reg(0x52, 0x2F);
+ wr_reg(0x53, 0x3F);
+ wr_reg(0x54, 0x3F);
+ wr_reg(0x55, 0x3E);
+ wr_reg(0x56, 0x2F);
+ wr_reg(0x57, 0x7B);
+ wr_reg(0x58, 0x09);
+ wr_reg(0x59, 0x06);
+ wr_reg(0x5A, 0x06);
+ wr_reg(0x5B, 0x0C);
+ wr_reg(0x5C, 0x1D);
+ wr_reg(0x5D, 0xCC);
+
+ /* Power voltage setting -------------------------------------------------*/
+ wr_reg(0x1B, 0x1B);
+ wr_reg(0x1A, 0x01);
+ wr_reg(0x24, 0x2F);
+ wr_reg(0x25, 0x57);
+ wr_reg(0x23, 0x88);
+
+ /* Power on setting ------------------------------------------------------*/
+ wr_reg(0x18, 0x36); /* Internal oscillator frequency adj. */
+ wr_reg(0x19, 0x01); /* Enable internal oscillator. */
+ wr_reg(0x01, 0x00); /* Normal mode, no scroll. */
+ wr_reg(0x1F, 0x88); /* Power control 6 - DDVDH Off. */
+ delay(20);
+ wr_reg(0x1F, 0x82); /* Power control 6 - Step-up: 3 x VCI. */
+ delay(5);
+ wr_reg(0x1F, 0x92); /* Power control 6 - Step-up: On. */
+ delay(5);
+ wr_reg(0x1F, 0xD2); /* Power control 6 - VCOML active. */
+ delay(5);
+
+ /* Color selection -------------------------------------------------------*/
+ wr_reg(0x17, 0x55); /* RGB, System interface: 16 Bit/Pixel. */
+ wr_reg(0x00, 0x00); /* Scrolling off, no standby. */
+
+ /* Interface config ------------------------------------------------------*/
+ wr_reg(0x2F, 0x11); /* LCD Drive: 1-line inversion. */
+ wr_reg(0x31, 0x00);
+ wr_reg(0x32, 0x00); /* DPL=0, HSPL=0, VSPL=0, EPL=0. */
+
+ /* Display on setting ----------------------------------------------------*/
+ wr_reg(0x28, 0x38); /* PT(0,0) active, VGL/VGL. */
+ delay(20);
+ wr_reg(0x28, 0x3C); /* Display active, VGL/VGL. */
+
+#if (LANDSCAPE == 1)
+#if (ROTATE180 == 0)
+ wr_reg (0x16, 0xA8);
+#else /* (ROTATE180 == 0) */
+ wr_reg (0x16, 0x68);
+#endif /* (ROTATE180 == 0) */
+#else /* (LANDSCAPE == 1) */
+#if (ROTATE180 == 0)
+ wr_reg (0x16, 0x08);
+#else /* (ROTATE180 == 0) */
+ wr_reg (0x16, 0xC8);
+#endif /* (ROTATE180 == 0) */
+#endif /* (LANDSCAPE == 1) */
+
+ /* Display scrolling settings --------------------------------------------*/
+ wr_reg(0x0E, 0x00); /* TFA MSB */
+ wr_reg(0x0F, 0x00); /* TFA LSB */
+ wr_reg(0x10, 320 >> 8); /* VSA MSB */
+ wr_reg(0x11, 320 & 0xFF); /* VSA LSB */
+ wr_reg(0x12, 0x00); /* BFA MSB */
+ wr_reg(0x13, 0x00); /* BFA LSB */
+
+ LCD_BL(1); /* turn on backlight */
+}
diff --git a/source/hal/platform/mps3/source/include/device_mps3.h b/source/hal/platform/mps3/source/include/device_mps3.h
deleted file mode 100644
index 445965d..0000000
--- a/source/hal/platform/mps3/source/include/device_mps3.h
+++ /dev/null
@@ -1,112 +0,0 @@
-/*
- * Copyright (c) 2021-2022 Arm Limited. All rights reserved.
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef DEVICE_MPS3_H
-#define DEVICE_MPS3_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "smm_mps3.h" /* Memory map for MPS3. */
-
-#include <stdio.h>
-
-#define PERIF_CLK (25000000) /* Clock source for APB peripherals */
-
-typedef struct _CMSDK_UART_TypeDef_
-{
- __IO uint32_t DATA; /* Offset: 0x000 (R/W) Data Register. */
- __IO uint32_t STATE; /* Offset: 0x004 (R/W) Status Register. */
- __IO uint32_t CTRL; /* Offset: 0x008 (R/W) Control Register. */
-
- union {
- __I uint32_t INTSTATUS; /* Offset: 0x00C (R/ ) Interrupt Status Register. */
- __O uint32_t INTCLEAR; /* Offset: 0x00C ( /W) Interrupt Clear Register. */
- };
- __IO uint32_t BAUDDIV; /* Offset: 0x010 (R/W) Baudrate Divider Register. */
-
-} CMSDK_UART_TypeDef;
-
-#define CMSDK_UART0 ((CMSDK_UART_TypeDef *)CMSDK_UART0_BASE)
-
-/* CMSDK_UART DATA Register Definitions. */
-#define CMSDK_UART_DATA_Pos 0 /* CMSDK_UART_DATA_Pos: DATA Position. */
-#define CMSDK_UART_DATA_Msk (0xFFul << CMSDK_UART_DATA_Pos) /* CMSDK_UART DATA: DATA Mask. */
-
-/* CMSDK_UART STATE Register Definitions. */
-#define CMSDK_UART_STATE_RXOR_Pos 3 /* CMSDK_UART STATE: RXOR Position. */
-#define CMSDK_UART_STATE_RXOR_Msk (0x1ul << CMSDK_UART_STATE_RXOR_Pos) /* CMSDK_UART STATE: RXOR Mask. */
-
-#define CMSDK_UART_STATE_TXOR_Pos 2 /* CMSDK_UART STATE: TXOR Position. */
-#define CMSDK_UART_STATE_TXOR_Msk (0x1ul << CMSDK_UART_STATE_TXOR_Pos) /* CMSDK_UART STATE: TXOR Mask. */
-
-#define CMSDK_UART_STATE_RXBF_Pos 1 /* CMSDK_UART STATE: RXBF Position. */
-#define CMSDK_UART_STATE_RXBF_Msk (0x1ul << CMSDK_UART_STATE_RXBF_Pos) /* CMSDK_UART STATE: RXBF Mask. */
-
-#define CMSDK_UART_STATE_TXBF_Pos 0 /* CMSDK_UART STATE: TXBF Position. */
-#define CMSDK_UART_STATE_TXBF_Msk (0x1ul << CMSDK_UART_STATE_TXBF_Pos ) /* CMSDK_UART STATE: TXBF Mask. */
-
-/* CMSDK_UART CTRL Register Definitions. */
-#define CMSDK_UART_CTRL_HSTM_Pos 6 /* CMSDK_UART CTRL: HSTM Position. */
-#define CMSDK_UART_CTRL_HSTM_Msk (0x01ul << CMSDK_UART_CTRL_HSTM_Pos) /* CMSDK_UART CTRL: HSTM Mask. */
-
-#define CMSDK_UART_CTRL_RXORIRQEN_Pos 5 /* CMSDK_UART CTRL: RXORIRQEN Position. */
-#define CMSDK_UART_CTRL_RXORIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_RXORIRQEN_Pos) /* CMSDK_UART CTRL: RXORIRQEN Mask. */
-
-#define CMSDK_UART_CTRL_TXORIRQEN_Pos 4 /* CMSDK_UART CTRL: TXORIRQEN Position. */
-#define CMSDK_UART_CTRL_TXORIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_TXORIRQEN_Pos) /* CMSDK_UART CTRL: TXORIRQEN Mask. */
-
-#define CMSDK_UART_CTRL_RXIRQEN_Pos 3 /* CMSDK_UART CTRL: RXIRQEN Position. */
-#define CMSDK_UART_CTRL_RXIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_RXIRQEN_Pos) /* CMSDK_UART CTRL: RXIRQEN Mask. */
-
-#define CMSDK_UART_CTRL_TXIRQEN_Pos 2 /* CMSDK_UART CTRL: TXIRQEN Position. */
-#define CMSDK_UART_CTRL_TXIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_TXIRQEN_Pos) /* CMSDK_UART CTRL: TXIRQEN Mask. */
-
-#define CMSDK_UART_CTRL_RXEN_Pos 1 /* CMSDK_UART CTRL: RXEN Position. */
-#define CMSDK_UART_CTRL_RXEN_Msk (0x01ul << CMSDK_UART_CTRL_RXEN_Pos) /* CMSDK_UART CTRL: RXEN Mask. */
-
-#define CMSDK_UART_CTRL_TXEN_Pos 0 /* CMSDK_UART CTRL: TXEN Position. */
-#define CMSDK_UART_CTRL_TXEN_Msk (0x01ul << CMSDK_UART_CTRL_TXEN_Pos) /* CMSDK_UART CTRL: TXEN Mask. */
-
-/* CMSDK_UART INTSTATUS\INTCLEAR Register Definitions. */
-#define CMSDK_UART_INT_RXORIRQ_Pos 3 /* CMSDK_UART INT: RXORIRQ Position. */
-#define CMSDK_UART_INT_RXORIRQ_Msk (0x01ul << CMSDK_UART_INT_RXORIRQ_Pos) /* CMSDK_UART INT: RXORIRQ Mask. */
-
-#define CMSDK_UART_INT_TXORIRQ_Pos 2 /* CMSDK_UART INT: TXORIRQ Position. */
-#define CMSDK_UART_INT_TXORIRQ_Msk (0x01ul << CMSDK_UART_INT_TXORIRQ_Pos) /* CMSDK_UART INT: TXORIRQ Mask. */
-
-#define CMSDK_UART_INT_RXIRQ_Pos 1 /* CMSDK_UART INT: RXIRQ Position. */
-#define CMSDK_UART_INT_RXIRQ_Msk (0x01ul << CMSDK_UART_INT_RXIRQ_Pos) /* CMSDK_UART INT: RXIRQ Mask. */
-
-#define CMSDK_UART_INT_TXIRQ_Pos 0 /* CMSDK_UART INT: TXIRQ Position. */
-#define CMSDK_UART_INT_TXIRQ_Msk (0x01ul << CMSDK_UART_INT_TXIRQ_Pos) /* CMSDK_UART INT: TXIRQ Mask. */
-
-/* CMSDK_UART BAUDDIV Register Definitions. */
-#define CMSDK_UART_BAUDDIV_Pos 0 /* CMSDK_UART BAUDDIV: BAUDDIV Position. */
-#define CMSDK_UART_BAUDDIV_Msk (0xFFFFFul << CMSDK_UART_BAUDDIV_Pos)
-
-/**
- * @brief Gets the core clock set for MPS3.
- * @return Clock value in Hz.
- **/
-uint32_t GetMPS3CoreClock(void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* DEVICE_MPS3_H */
diff --git a/source/hal/platform/mps3/source/platform_drivers.c b/source/hal/platform/mps3/source/platform_drivers.c
index fc119ab..00afb78 100644
--- a/source/hal/platform/mps3/source/platform_drivers.c
+++ b/source/hal/platform/mps3/source/platform_drivers.c
@@ -21,14 +21,16 @@
#include "device_mps3.h" /* FPGA level definitions and functions. */
#include "uart_stdout.h" /* stdout over UART. */
+#include "smm_mps3.h" /* Memory map for MPS3. */
+
#include <string.h> /* For strncpy */
#if defined(ARM_NPU)
#include "ethosu_npu_init.h"
-#if defined(TIMING_ADAPTER_AVAILABLE)
+#if defined(ETHOS_U_NPU_TIMING_ADAPTER_ENABLED)
#include "ethosu_ta_init.h"
-#endif /* TIMING_ADAPTER_AVAILABLE */
+#endif /* ETHOS_U_NPU_TIMING_ADAPTER_ENABLED */
#endif /* ARM_NPU */
@@ -56,14 +58,14 @@
#if defined(ARM_NPU)
-#if defined(TIMING_ADAPTER_AVAILABLE)
+#if defined(ETHOS_U_NPU_TIMING_ADAPTER_ENABLED)
/* If the platform has timing adapter blocks along with Ethos-U core
* block, initialise them here. */
if (0 != (err = arm_ethosu_timing_adapter_init()))
{
return err;
}
-#endif /* TIMING_ADAPTER_AVAILABLE */
+#endif /* ETHOS_U_NPU_TIMING_ADAPTER_ENABLED */
int state;
diff --git a/source/hal/platform/mps3/source/include/smm_mps3.h b/source/hal/platform/mps3/source/smm_mps3.h
similarity index 99%
rename from source/hal/platform/mps3/source/include/smm_mps3.h
rename to source/hal/platform/mps3/source/smm_mps3.h
index bc93fdf..8d5614a 100644
--- a/source/hal/platform/mps3/source/include/smm_mps3.h
+++ b/source/hal/platform/mps3/source/smm_mps3.h
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021-2022 Arm Limited. All rights reserved.
+ * Copyright (c) 2022 Arm Limited. All rights reserved.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
diff --git a/source/hal/platform/mps3/source/timer_mps3.c b/source/hal/platform/mps3/source/timer_mps3.c
index 16ff4cd..6da026f 100644
--- a/source/hal/platform/mps3/source/timer_mps3.c
+++ b/source/hal/platform/mps3/source/timer_mps3.c
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2021-2022 Arm Limited. All rights reserved.
+ * Copyright (c) 2022 Arm Limited. All rights reserved.
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License");
@@ -18,6 +18,7 @@
#include "log_macros.h"
#include "device_mps3.h"
+#include "smm_mps3.h" /* Memory map for MPS3. */
static uint64_t cpu_cycle_count = 0; /* 64-bit cpu cycle counter */