MLECO-2976: Configurable Ethos-U cache size for Dedicated_Sram
MLECO-2949: Platform drivers should own NPU and TA init
Change-Id: I13606a0197f137816bae803eb9d7d46c358b5fb8
Signed-off-by: Isabella Gottardi <isabella.gottardi@arm.com>
diff --git a/source/hal/components/ethosu_npu_init/ethosu_npu_init.c b/source/hal/components/ethosu_npu_init/ethosu_npu_init.c
new file mode 100644
index 0000000..2fed693
--- /dev/null
+++ b/source/hal/components/ethosu_npu_init/ethosu_npu_init.c
@@ -0,0 +1,122 @@
+/*
+ * Copyright (c) 2022 Arm Limited. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ethosu_npu_init.h"
+
+#include "RTE_components.h" /* For CPU related defintiions */
+#include "peripheral_memmap.h" /* Peripheral memory map definitions. */
+#include "peripheral_irqs.h" /* IRQ numbers for this platform. */
+#include "log_macros.h" /* Logging functions */
+
+#include "ethosu_mem_config.h" /* Arm Ethos-U memory config */
+#include "ethosu_driver.h" /* Arm Ethos-U driver header */
+
+struct ethosu_driver ethosu_drv; /* Default Ethos-U device driver */
+
+#if defined(ETHOS_U_CACHE_BUF_SZ) && (ETHOS_U_CACHE_BUF_SZ > 0)
+static uint8_t cache_arena[ETHOS_U_CACHE_BUF_SZ] CACHE_BUF_ATTRIBUTE;
+#else /* defined (ETHOS_U_CACHE_BUF_SZ) && (ETHOS_U_CACHE_BUF_SZ > 0) */
+static uint8_t *cache_arena = NULL;
+#endif /* defined (ETHOS_U_CACHE_BUF_SZ) && (ETHOS_U_CACHE_BUF_SZ > 0) */
+
+uint8_t *get_cache_arena()
+{
+ return cache_arena;
+}
+
+size_t get_cache_arena_size()
+{
+#if defined(ETHOS_U_CACHE_BUF_SZ) && (ETHOS_U_CACHE_BUF_SZ > 0)
+ return sizeof(cache_arena);
+#else /* defined (ETHOS_U_CACHE_BUF_SZ) && (ETHOS_U_CACHE_BUF_SZ > 0) */
+ return 0;
+#endif /* defined (ETHOS_U_CACHE_BUF_SZ) && (ETHOS_U_CACHE_BUF_SZ > 0) */
+}
+
+/**
+ * @brief Defines the Ethos-U interrupt handler: just a wrapper around the default
+ * implementation.
+ **/
+void arm_ethosu_npu_irq_handler(void)
+{
+ /* Call the default interrupt handler from the NPU driver */
+ ethosu_irq_handler(ðosu_drv);
+}
+
+/**
+ * @brief Initialises the NPU IRQ
+ **/
+void arm_ethosu_npu_irq_init(void)
+{
+ const IRQn_Type ethosu_irqnum = (IRQn_Type)EthosU_IRQn;
+
+ /* Register the EthosU IRQ handler in our vector table.
+ * Note, this handler comes from the EthosU driver */
+ NVIC_SetVector(ethosu_irqnum, (uint32_t)arm_ethosu_npu_irq_handler);
+
+ /* Enable the IRQ */
+ NVIC_EnableIRQ(ethosu_irqnum);
+
+ debug("EthosU IRQ#: %u, Handler: 0x%p\n",
+ ethosu_irqnum, arm_ethosu_npu_irq_handler);
+}
+
+int arm_ethosu_npu_init(void)
+{
+ int err = 0;
+
+ /* Initialise the IRQ */
+ arm_ethosu_npu_irq_init();
+
+ /* Initialise Ethos-U device */
+ const void *ethosu_base_address = (void *)(SEC_ETHOS_U_NPU_BASE);
+
+ if (0 != (err = ethosu_init(
+ ðosu_drv, /* Ethos-U driver device pointer */
+ ethosu_base_address, /* Ethos-U NPU's base address. */
+ get_cache_arena(), /* Pointer to fast mem area - NULL for U55. */
+ get_cache_arena_size(), /* Fast mem region size. */
+ 1, /* Security enable. */
+ 1))) /* Privilege enable. */
+ {
+ printf_err("failed to initialise Ethos-U device\n");
+ return err;
+ }
+
+ info("Ethos-U device initialised\n");
+
+ /* Get Ethos-U version */
+ struct ethosu_driver_version driver_version;
+ struct ethosu_hw_info hw_info;
+
+ ethosu_get_driver_version(&driver_version);
+ ethosu_get_hw_info(ðosu_drv, &hw_info);
+
+ info("Ethos-U version info:\n");
+ info("\tArch: v%" PRIu32 ".%" PRIu32 ".%" PRIu32 "\n",
+ hw_info.version.arch_major_rev,
+ hw_info.version.arch_minor_rev,
+ hw_info.version.arch_patch_rev);
+ info("\tDriver: v%" PRIu8 ".%" PRIu8 ".%" PRIu8 "\n",
+ driver_version.major,
+ driver_version.minor,
+ driver_version.patch);
+ info("\tMACs/cc: %" PRIu32 "\n", (uint32_t)(1 << hw_info.cfg.macs_per_cc));
+ info("\tCmd stream: v%" PRIu32 "\n", hw_info.cfg.cmd_stream_version);
+
+ return 0;
+}
diff --git a/source/hal/components/ethosu_npu_init/include/ethosu_npu_init.h b/source/hal/components/ethosu_npu_init/include/ethosu_npu_init.h
new file mode 100644
index 0000000..c562f6c
--- /dev/null
+++ b/source/hal/components/ethosu_npu_init/include/ethosu_npu_init.h
@@ -0,0 +1,30 @@
+/*
+ * Copyright (c) 2022 Arm Limited. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef ETHOS_U_NPU_INIT_H
+#define ETHOS_U_NPU_INIT_H
+
+#if defined(ARM_NPU)
+
+/**
+ * @brief Initialises the Arm Ethos-U NPU
+ * @return 0 if successful, error code otherwise
+ **/
+int arm_ethosu_npu_init(void);
+
+#endif /* ARM_NPU */
+
+#endif /* ETHOS_U_NPU_INIT_H */
diff --git a/source/hal/components/ethosu_ta_init/ethosu_ta_init.c b/source/hal/components/ethosu_ta_init/ethosu_ta_init.c
new file mode 100644
index 0000000..26eeb5c
--- /dev/null
+++ b/source/hal/components/ethosu_ta_init/ethosu_ta_init.c
@@ -0,0 +1,86 @@
+/*
+ * Copyright (c) 2022 Arm Limited. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "ethosu_ta_init.h"
+
+#include "log_macros.h" /* Logging functions */
+
+#if defined(TIMING_ADAPTER_AVAILABLE)
+
+#include "timing_adapter.h" /* Arm Ethos-U timing adapter driver header */
+#include "timing_adapter_settings.h" /* Arm Ethos-U timing adapter settings */
+
+int arm_ethosu_timing_adapter_init(void)
+{
+#if defined(TA0_BASE)
+ struct timing_adapter ta_0;
+ struct timing_adapter_settings ta_0_settings = {
+ .maxr = TA0_MAXR,
+ .maxw = TA0_MAXW,
+ .maxrw = TA0_MAXRW,
+ .rlatency = TA0_RLATENCY,
+ .wlatency = TA0_WLATENCY,
+ .pulse_on = TA0_PULSE_ON,
+ .pulse_off = TA0_PULSE_OFF,
+ .bwcap = TA0_BWCAP,
+ .perfctrl = TA0_PERFCTRL,
+ .perfcnt = TA0_PERFCNT,
+ .mode = TA0_MODE,
+ .maxpending = 0, /* This is a read-only parameter */
+ .histbin = TA0_HISTBIN,
+ .histcnt = TA0_HISTCNT};
+
+ if (0 != ta_init(&ta_0, TA0_BASE))
+ {
+ printf_err("TA0 initialisation failed\n");
+ return 1;
+ }
+
+ ta_set_all(&ta_0, &ta_0_settings);
+#endif /* defined (TA0_BASE) */
+
+#if defined(TA1_BASE)
+ struct timing_adapter ta_1;
+ struct timing_adapter_settings ta_1_settings = {
+ .maxr = TA1_MAXR,
+ .maxw = TA1_MAXW,
+ .maxrw = TA1_MAXRW,
+ .rlatency = TA1_RLATENCY,
+ .wlatency = TA1_WLATENCY,
+ .pulse_on = TA1_PULSE_ON,
+ .pulse_off = TA1_PULSE_OFF,
+ .bwcap = TA1_BWCAP,
+ .perfctrl = TA1_PERFCTRL,
+ .perfcnt = TA1_PERFCNT,
+ .mode = TA1_MODE,
+ .maxpending = 0, /* This is a read-only parameter */
+ .histbin = TA1_HISTBIN,
+ .histcnt = TA1_HISTCNT};
+
+ if (0 != ta_init(&ta_1, TA1_BASE))
+ {
+ printf_err("TA1 initialisation failed\n");
+ return 1;
+ }
+
+ ta_set_all(&ta_1, &ta_1_settings);
+#endif /* defined (TA1_BASE) */
+
+ return 0;
+}
+
+#endif /* TIMING_ADAPTER_AVAILABLE */
diff --git a/source/hal/components/ethosu_ta_init/include/ethosu_ta_init.h b/source/hal/components/ethosu_ta_init/include/ethosu_ta_init.h
new file mode 100644
index 0000000..2ab7fb2
--- /dev/null
+++ b/source/hal/components/ethosu_ta_init/include/ethosu_ta_init.h
@@ -0,0 +1,30 @@
+/*
+ * Copyright (c) 2022 Arm Limited. All rights reserved.
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef ETHOS_U_TA_INIT_H
+#define ETHOS_U_TA_INIT_H
+
+#if defined(ARM_NPU) && defined(TIMING_ADAPTER_AVAILABLE)
+
+/**
+ * @brief Initialises the Arm Ethos-U NPU timing adapter
+ * @return 0 if successful, error code otherwise
+ **/
+int arm_ethosu_timing_adapter_init(void);
+
+#endif /* ARM_NPU && TIMING_ADAPTER_AVAILABLE */
+
+#endif /* ETHOS_U_TA_INIT_H */