diff --git a/source/application/hal/platforms/bare-metal/bsp/mem_layout/mps3-sse-300.sct b/source/application/hal/platforms/bare-metal/bsp/mem_layout/mps3-sse-300.sct
index 55ed5d7..dd53a57 100644
--- a/source/application/hal/platforms/bare-metal/bsp/mem_layout/mps3-sse-300.sct
+++ b/source/application/hal/platforms/bare-metal/bsp/mem_layout/mps3-sse-300.sct
@@ -18,7 +18,7 @@
 ; *************************************************************
 ; Please see docs/sections/appendix.md for memory mapping information.
 ;
-; Note: Ethos-U55 can access BRAM, internal SRAM and the DDR sections => activation buffers and
+; Note: Ethos-U NPU can access BRAM, internal SRAM and the DDR sections => activation buffers and
 ;       the model should only be placed in those regions.
 ;
 ;---------------------------------------------------------
@@ -63,7 +63,7 @@
     ; SSE-300's internal SRAM of 4MiB - reserved for
     ; activation buffers.
     ; This region should have 3 cycle read latency from
-    ; both Cortex-M55 and Ethos-U55
+    ; both Cortex-M55 and Ethos-U NPU
     ;-----------------------------------------------------
     isram.bin       0x31000000  UNINIT ALIGN 16 0x00400000
     {