diff --git a/source/application/hal/platforms/bare-metal/bsp/mem_layout/simple_platform.sct b/source/application/hal/platforms/bare-metal/bsp/mem_layout/simple_platform.sct
index deb4214..0c6a388 100644
--- a/source/application/hal/platforms/bare-metal/bsp/mem_layout/simple_platform.sct
+++ b/source/application/hal/platforms/bare-metal/bsp/mem_layout/simple_platform.sct
@@ -59,7 +59,7 @@
     ; SSE-300's internal SRAM of 4MiB - reserved for
     ; activation buffers.
     ; This region should have 3 cycle read latency from
-    ; both Cortex-M55 and Ethos-U55
+    ; both Cortex-M55 and Ethos-U NPU
     ;-----------------------------------------------------
     isram.bin       0x31000000  UNINIT ALIGN 16 0x00400000
     {