MLCE-864: Enabling I-Cache and D-Cache for MPS3
Both supported implementation on MPS3 (Arm Corstone-300 and
Arm Corstone-310) will now have caches enabled.
Also including a minor change left over from refactoring of
code for HAL components.
Change-Id: Ie5768cd26eef9083a817bca7c87ff691dae67fca
diff --git a/source/hal/source/components/lcd/source/lcd_img.c b/source/hal/source/components/lcd/source/lcd_img.c
index 92069c2..d438324 100644
--- a/source/hal/source/components/lcd/source/lcd_img.c
+++ b/source/hal/source/components/lcd/source/lcd_img.c
@@ -24,36 +24,9 @@
static int show_title(void)
{
- char title[128];
- int status = 0;
-
- /* LCD title string */
-#if defined(CPU_CORTEX_M55)
- const char* cpu_name = "Arm Cortex-M55";
-#elif defined (ARMv81MML_DSP_DP_MVE_FP)
- const char* cpu_name = "ARMv8.1-M CPU";
-#else /* defined(CPU_CORTEX_M55) */
- const char* cpu_name = "Arm CPU";
-#endif /* defined(CPU_CORTEX_M55) */
-
+ const char title[] = "Arm ML embedded code samples";
lcd_set_text_color(White);
-
- /* First line */
- snprintf(title, sizeof(title), "Arm ML embedded code samples");
-
- if (0 != (status = lcd_display_text(
- title, strlen(title), 10, 0, false))) {
- return status;
- }
-
- /* Second line */
-#if defined (ARM_NPU)
- snprintf(title, sizeof(title), "%s + Arm Ethos-U NPU", cpu_name);
-#else /* defined (ARM_NPU) */
- snprintf(title, sizeof(title), "%s", cpu_name);
-#endif /* defined (ARM_NPU) */
-
- return lcd_display_text(title, strlen(title), 10, 20, false);
+ return lcd_display_text(title, strlen(title), 10, 0, false);
}
int lcd_init(void)
diff --git a/source/hal/source/platform/mps3/source/platform_drivers.c b/source/hal/source/platform/mps3/source/platform_drivers.c
index 801cd0b..7c5de6d 100644
--- a/source/hal/source/platform/mps3/source/platform_drivers.c
+++ b/source/hal/source/platform/mps3/source/platform_drivers.c
@@ -65,6 +65,16 @@
return err;
}
+#if defined(__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U)
+ info("Enabling I-cache.\n");
+ SCB_EnableICache();
+#endif /* __ICACHE_PRESENT */
+
+#if defined(__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U)
+ info("Enabling D-cache.\n");
+ SCB_EnableDCache();
+#endif /* __DCACHE_PRESENT */
+
#if defined(ARM_NPU)
#if defined(ETHOS_U_NPU_TIMING_ADAPTER_ENABLED)