Blame - source/hal/platform/mps3/include/device_mps3.h - ml/ethos-u/ml-embedded-evaluation-kit

alexander

3c79893

2021-03-26 21:42:19 +0000

[diff] [blame]

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/*

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* SPDX-License-Identifier: Apache-2.0

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*

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* Licensed under the Apache License, Version 2.0 (the "License");

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* you may not use this file except in compliance with the License.

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* You may obtain a copy of the License at

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*

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* http://www.apache.org/licenses/LICENSE-2.0

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*

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* Unless required by applicable law or agreed to in writing, software

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* distributed under the License is distributed on an "AS IS" BASIS,

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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

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* See the License for the specific language governing permissions and

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* limitations under the License.

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*/

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#ifndef DEVICE_MPS3_H

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#define DEVICE_MPS3_H

#ifdef __cplusplus

extern "C" {

#endif

#include "cmsis.h" /* CMSIS device header. */

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#include "smm_mps3.h" /* Memory map for MPS3. */

#include <stdio.h>

Kshitij Sisodia

2021-10-04 14:31:25 +0100

[diff] [blame]

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#define PERIF_CLK (25000000) /* Clock source for APB peripherals */

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alexander

3c79893

2021-03-26 21:42:19 +0000

[diff] [blame]

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typedef struct _CMSDK_UART_TypeDef_

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{

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__IO uint32_t DATA; /* Offset: 0x000 (R/W) Data Register. */

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__IO uint32_t STATE; /* Offset: 0x004 (R/W) Status Register. */

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__IO uint32_t CTRL; /* Offset: 0x008 (R/W) Control Register. */

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union {

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__I uint32_t INTSTATUS; /* Offset: 0x00C (R/ ) Interrupt Status Register. */

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__O uint32_t INTCLEAR; /* Offset: 0x00C ( /W) Interrupt Clear Register. */

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};

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__IO uint32_t BAUDDIV; /* Offset: 0x010 (R/W) Baudrate Divider Register. */

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} CMSDK_UART_TypeDef;

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#define CMSDK_UART0 ((CMSDK_UART_TypeDef *)CMSDK_UART0_BASE)

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/* CMSDK_UART DATA Register Definitions. */

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#define CMSDK_UART_DATA_Pos 0 /* CMSDK_UART_DATA_Pos: DATA Position. */

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#define CMSDK_UART_DATA_Msk (0xFFul << CMSDK_UART_DATA_Pos) /* CMSDK_UART DATA: DATA Mask. */

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/* CMSDK_UART STATE Register Definitions. */

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#define CMSDK_UART_STATE_RXOR_Pos 3 /* CMSDK_UART STATE: RXOR Position. */

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#define CMSDK_UART_STATE_RXOR_Msk (0x1ul << CMSDK_UART_STATE_RXOR_Pos) /* CMSDK_UART STATE: RXOR Mask. */

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#define CMSDK_UART_STATE_TXOR_Pos 2 /* CMSDK_UART STATE: TXOR Position. */

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#define CMSDK_UART_STATE_TXOR_Msk (0x1ul << CMSDK_UART_STATE_TXOR_Pos) /* CMSDK_UART STATE: TXOR Mask. */

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#define CMSDK_UART_STATE_RXBF_Pos 1 /* CMSDK_UART STATE: RXBF Position. */

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#define CMSDK_UART_STATE_RXBF_Msk (0x1ul << CMSDK_UART_STATE_RXBF_Pos) /* CMSDK_UART STATE: RXBF Mask. */

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#define CMSDK_UART_STATE_TXBF_Pos 0 /* CMSDK_UART STATE: TXBF Position. */

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#define CMSDK_UART_STATE_TXBF_Msk (0x1ul << CMSDK_UART_STATE_TXBF_Pos ) /* CMSDK_UART STATE: TXBF Mask. */

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/* CMSDK_UART CTRL Register Definitions. */

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#define CMSDK_UART_CTRL_HSTM_Pos 6 /* CMSDK_UART CTRL: HSTM Position. */

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#define CMSDK_UART_CTRL_HSTM_Msk (0x01ul << CMSDK_UART_CTRL_HSTM_Pos) /* CMSDK_UART CTRL: HSTM Mask. */

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#define CMSDK_UART_CTRL_RXORIRQEN_Pos 5 /* CMSDK_UART CTRL: RXORIRQEN Position. */

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#define CMSDK_UART_CTRL_RXORIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_RXORIRQEN_Pos) /* CMSDK_UART CTRL: RXORIRQEN Mask. */

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#define CMSDK_UART_CTRL_TXORIRQEN_Pos 4 /* CMSDK_UART CTRL: TXORIRQEN Position. */

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#define CMSDK_UART_CTRL_TXORIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_TXORIRQEN_Pos) /* CMSDK_UART CTRL: TXORIRQEN Mask. */

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#define CMSDK_UART_CTRL_RXIRQEN_Pos 3 /* CMSDK_UART CTRL: RXIRQEN Position. */

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#define CMSDK_UART_CTRL_RXIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_RXIRQEN_Pos) /* CMSDK_UART CTRL: RXIRQEN Mask. */

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#define CMSDK_UART_CTRL_TXIRQEN_Pos 2 /* CMSDK_UART CTRL: TXIRQEN Position. */

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#define CMSDK_UART_CTRL_TXIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_TXIRQEN_Pos) /* CMSDK_UART CTRL: TXIRQEN Mask. */

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#define CMSDK_UART_CTRL_RXEN_Pos 1 /* CMSDK_UART CTRL: RXEN Position. */

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#define CMSDK_UART_CTRL_RXEN_Msk (0x01ul << CMSDK_UART_CTRL_RXEN_Pos) /* CMSDK_UART CTRL: RXEN Mask. */

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#define CMSDK_UART_CTRL_TXEN_Pos 0 /* CMSDK_UART CTRL: TXEN Position. */

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#define CMSDK_UART_CTRL_TXEN_Msk (0x01ul << CMSDK_UART_CTRL_TXEN_Pos) /* CMSDK_UART CTRL: TXEN Mask. */

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/* CMSDK_UART INTSTATUS\INTCLEAR Register Definitions. */

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#define CMSDK_UART_INT_RXORIRQ_Pos 3 /* CMSDK_UART INT: RXORIRQ Position. */

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#define CMSDK_UART_INT_RXORIRQ_Msk (0x01ul << CMSDK_UART_INT_RXORIRQ_Pos) /* CMSDK_UART INT: RXORIRQ Mask. */

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#define CMSDK_UART_INT_TXORIRQ_Pos 2 /* CMSDK_UART INT: TXORIRQ Position. */

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#define CMSDK_UART_INT_TXORIRQ_Msk (0x01ul << CMSDK_UART_INT_TXORIRQ_Pos) /* CMSDK_UART INT: TXORIRQ Mask. */

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#define CMSDK_UART_INT_RXIRQ_Pos 1 /* CMSDK_UART INT: RXIRQ Position. */

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#define CMSDK_UART_INT_RXIRQ_Msk (0x01ul << CMSDK_UART_INT_RXIRQ_Pos) /* CMSDK_UART INT: RXIRQ Mask. */

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#define CMSDK_UART_INT_TXIRQ_Pos 0 /* CMSDK_UART INT: TXIRQ Position. */

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#define CMSDK_UART_INT_TXIRQ_Msk (0x01ul << CMSDK_UART_INT_TXIRQ_Pos) /* CMSDK_UART INT: TXIRQ Mask. */

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/* CMSDK_UART BAUDDIV Register Definitions. */

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#define CMSDK_UART_BAUDDIV_Pos 0 /* CMSDK_UART BAUDDIV: BAUDDIV Position. */

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#define CMSDK_UART_BAUDDIV_Msk (0xFFFFFul << CMSDK_UART_BAUDDIV_Pos)

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/**

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* @brief Gets the core clock set for MPS3.

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* @return Clock value in Hz.

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**/

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uint32_t GetMPS3CoreClock(void);

#ifdef __cplusplus

}

#endif

#endif /* DEVICE_MPS3_H */