blob: c11706df558a0a30314cc5d98cbb6ec2c34f4386 [file] [log] [blame]
alexander3c798932021-03-26 21:42:19 +00001#----------------------------------------------------------------------------
2# Copyright (c) 2021 Arm Limited. All rights reserved.
3# SPDX-License-Identifier: Apache-2.0
4#
5# Licensed under the Apache License, Version 2.0 (the "License");
6# you may not use this file except in compliance with the License.
7# You may obtain a copy of the License at
8#
9# http://www.apache.org/licenses/LICENSE-2.0
10#
11# Unless required by applicable law or agreed to in writing, software
12# distributed under the License is distributed on an "AS IS" BASIS,
13# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14# See the License for the specific language governing permissions and
15# limitations under the License.
16#----------------------------------------------------------------------------
17
18# CMake configuration file for peripheral memory map for simple platform. This is a stripped down
19# version of Arm Corstone-300 platform with minimal peripherals to be able to use Ethos-U55. However,
20# for ease of integration with Arm FastModel Tools, it uses PL011 as the UART component instead of
21# the CMSDK UART block used by the MPS3 FPGA and FVP implementations.
22
23###################################################################################################
24# Application specific config #
25###################################################################################################
26
27# This parameter is based on the linker/scatter script for internal FVP. Do not change this
28# parameter in isolation.
29set(ACTIVATION_BUF_SRAM_SZ "0x00200000" CACHE STRING "Maximum SRAM size for activation buffers")
30set(DESIGN_NAME "Simple platform" CACHE STRING "Design name")
31
32###################################################################################################
33# Base addresses #
34###################################################################################################
35set(PL011_UART0_BASE "0x49303000" CACHE STRING "PL011 UART 0 Base Address")
36
37if (ETHOS_U55_ENABLED)
38 set(ETHOS_U55_BASE "0x48102000" CACHE STRING "Ethos-U55 base address")
39 set(ETHOS_U55_TA0_BASE "0x48103000" CACHE STRING "Ethos-U55's timing adapter 0 base address")
40 set(ETHOS_U55_TA1_BASE "0x48103200" CACHE STRING "Ethos-U55's timing adapter 1 base address")
41 set(SEC_ETHOS_U55_BASE "0x58102000" CACHE STRING "Ethos-U55 base address")
42 set(SEC_ETHOS_U55_TA0_BASE "0x58103000" CACHE STRING "Ethos-U55's timing adapter 0 base address")
43 set(SEC_ETHOS_U55_TA1_BASE "0x58103200" CACHE STRING "Ethos-U55's timing adapter 1 base address")
44endif ()
45
46###################################################################################################
47# IRQ numbers #
48###################################################################################################
49if (ETHOS_U55_ENABLED)
50 set(EthosU_IRQn "56" CACHE STRING "Ethos-U55 Interrupt")
51endif ()