blob: a631aaa81fa3858a1b5e623b64de0bbd0b3c4428 [file] [log] [blame]
Kshitij Sisodia8c61c0a2022-05-17 11:16:22 +01001/*
2 * Copyright (c) 2021 Arm Limited. All rights reserved.
3 * SPDX-License-Identifier: Apache-2.0
4 *
5 * Licensed under the Apache License, Version 2.0 (the "License");
6 * you may not use this file except in compliance with the License.
7 * You may obtain a copy of the License at
8 *
9 * http://www.apache.org/licenses/LICENSE-2.0
10 *
11 * Unless required by applicable law or agreed to in writing, software
12 * distributed under the License is distributed on an "AS IS" BASIS,
13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14 * See the License for the specific language governing permissions and
15 * limitations under the License.
16 */
17
18__STACK_SIZE = 0x00008000;
19__HEAP_SIZE = 0x000C0000;
20
21/* System memory brief */
22MEMORY
23{
24 ITCM (rx) : ORIGIN = 0x10000000, LENGTH = 0x00008000
25 DTCM (rwx) : ORIGIN = 0x30000000, LENGTH = 0x00008000
26 BRAM (rwx) : ORIGIN = 0x11000000, LENGTH = 0x00200000
27 SRAM (rwx) : ORIGIN = 0x31000000, LENGTH = 0x00400000
28 DDR (rwx) : ORIGIN = 0x70000000, LENGTH = 0x02000000
29
30 /* Dynamic load regions declared for use by FVP only
31 * These regions are mentioned in the CMake subsystem profile.
32 * Do not change the addresses here in isolation. */
33 DDR_dynamic_model (rx) : ORIGIN = 0x90000000, LENGTH = 0x02000000
34 DDR_dynamic_ifm (rx) : ORIGIN = 0x92000000, LENGTH = 0x01000000
35 DDR_dynamic_ofm (rx) : ORIGIN = 0x93000000, LENGTH = 0x01000000
36}
37
38/* Linker script to place sections and symbol values. Should be used together
39 * with other linker script that defines memory regions ITCM and RAM.
40 * It references following symbols, which must be defined in code:
41 * Reset_Handler : Entry of reset handler
42 *
43 * It defines following symbols, which code can use without definition:
44 * __exidx_start
45 * __exidx_end
46 * __copy_table_start__
47 * __copy_table_end__
48 * __zero_table_start__
49 * __zero_table_end__
50 * __etext
51 * __data_start__
52 * __preinit_array_start
53 * __preinit_array_end
54 * __init_array_start
55 * __init_array_end
56 * __fini_array_start
57 * __fini_array_end
58 * __data_end__
59 * __bss_start__
60 * __bss_end__
61 * __end__
62 * end
63 * __HeapLimit
64 * __StackLimit
65 * __StackTop
66 * __stack
67 */
68ENTRY(Reset_Handler)
69
70SECTIONS
71{
72 .text.at_bram :
73 {
74 KEEP(*(.vectors))
75
76 KEEP(*(.init))
77 KEEP(*(.fini))
78
79 /* .ctors */
80 *crtbegin.o(.ctors)
81 *crtbegin?.o(.ctors)
82 *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
83 *(SORT(.ctors.*))
84 *(.ctors)
85
86 /* .dtors */
87 *crtbegin.o(.dtors)
88 *crtbegin?.o(.dtors)
89 *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
90 *(SORT(.dtors.*))
91 *(.dtors)
92
93 KEEP(*(.eh_frame*))
94
95 *(vtable)
96 *(.data)
97 *(.data.*)
98 . = ALIGN(4);
99 PROVIDE_HIDDEN (__preinit_array_start = .);
100 KEEP(*(.preinit_array))
101 PROVIDE_HIDDEN (__preinit_array_end = .);
102 . = ALIGN(4);
103 PROVIDE_HIDDEN (__init_array_start = .);
104 KEEP(*(SORT(.init_array.*)))
105 KEEP(*(.init_array))
106 PROVIDE_HIDDEN (__init_array_end = .);
107 . = ALIGN(4);
108 PROVIDE_HIDDEN (__fini_array_start = .);
109 KEEP(*(SORT(.fini_array.*)))
110 KEEP(*(.fini_array))
111 PROVIDE_HIDDEN (__fini_array_end = .);
112 KEEP(*(.jcr*))
113 . = ALIGN(4);
114
115 *(.ARM.extab* .gnu.linkonce.armextab.*)
116 . = ALIGN(4);
117
118 *(.rodata*)
119 . = ALIGN(4);
120 * (npu_driver_version)
121 . = ALIGN(4);
122 * (npu_driver_arch_version)
123 . = ALIGN(4);
124
125 __copy_table_start__ = .;
126 . = ALIGN(4);
127 __copy_table_end__ = .;
128 } > BRAM
129
130 __exidx_start = .;
131 .ARM.exidx.at_bram :
132 {
133 *(.ARM.exidx* .gnu.linkonce.armexidx.*)
134 } > BRAM
135 __exidx_end = .;
136
137 .sram :
138 {
139 . = ALIGN(16);
140 /* Cache area (if used) */
141 *(.bss.NoInit.ethos_u_cache)
142 . = ALIGN (16);
143 /* activation buffers a.k.a tensor arena when memory mode sram only or shared sram */
144 *(.bss.NoInit.activation_buf_sram)
145 . = ALIGN(16);
146 } > SRAM AT > SRAM
147
148 .bss :
149 {
150 . = ALIGN(4);
151 __bss_start__ = .;
152 *(.bss)
153 *(.bss.*)
154 *(COMMON)
155 . = ALIGN(4);
156 __bss_end__ = .;
157 } > BRAM
158
159 .zero.table.at_bram :
160 {
161 . = ALIGN(4);
162 __zero_table_start__ = .;
163
164 LONG (__bss_start__)
165 LONG ((__bss_end__ - __bss_start__)/4) /* Size is in 32-bit words */
166
167 __zero_table_end__ = .;
168 } > BRAM
169
170 .heap (COPY) :
171 {
172 . = ALIGN(8);
173 __end__ = .;
174 PROVIDE(end = .);
175 . = . + __HEAP_SIZE;
176 . = ALIGN(8);
177 __HeapLimit = .;
178 } > BRAM
179
180 __bram_total = ALIGN(4);
181
182 ASSERT( __bram_total < (ORIGIN(BRAM) + LENGTH(BRAM)), "BRAM overflow")
183
184 .stack (ORIGIN(DTCM) + LENGTH(DTCM) - __STACK_SIZE) (COPY) :
185 {
186 . = ALIGN(8);
187 __StackLimit = .;
188 . = . + __STACK_SIZE;
189 . = ALIGN(8);
190 __StackTop = .;
191 } > DTCM
192 PROVIDE(__stack = __StackTop);
193 ASSERT(__STACK_SIZE <= LENGTH(DTCM), "DTCM overflow")
194
195 .ddr.at_ddr :
196 {
197 /* __attribute__((aligned(16))) is not handled by the CMSIS startup code.
198 * Force the alignment here as a workaround */
199 . = ALIGN(16);
200 /* nn model's baked in input matrices */
201 *(ifm)
202 . = ALIGN(16);
203 /* nn model's default space */
204 *(nn_model)
205 . = ALIGN (16);
206 /* labels */
207 *(labels)
208 . = ALIGN (16);
209 /* activation buffers a.k.a tensor arena when memory mode dedicated sram */
210 *(activation_buf_dram)
211 . = ALIGN (16);
212 } > DDR AT > DDR
213
214}