Kshitij Sisodia | 8c61c0a | 2022-05-17 11:16:22 +0100 | [diff] [blame] | 1 | /* |
Richard Burton | 973158f | 2023-11-06 14:40:28 +0000 | [diff] [blame^] | 2 | * SPDX-FileCopyrightText: Copyright 2021, 2023 Arm Limited and/or its affiliates <open-source-office@arm.com> |
Kshitij Sisodia | 8c61c0a | 2022-05-17 11:16:22 +0100 | [diff] [blame] | 3 | * SPDX-License-Identifier: Apache-2.0 |
| 4 | * |
| 5 | * Licensed under the Apache License, Version 2.0 (the "License"); |
| 6 | * you may not use this file except in compliance with the License. |
| 7 | * You may obtain a copy of the License at |
| 8 | * |
| 9 | * http://www.apache.org/licenses/LICENSE-2.0 |
| 10 | * |
| 11 | * Unless required by applicable law or agreed to in writing, software |
| 12 | * distributed under the License is distributed on an "AS IS" BASIS, |
| 13 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 14 | * See the License for the specific language governing permissions and |
| 15 | * limitations under the License. |
| 16 | */ |
| 17 | |
| 18 | __STACK_SIZE = 0x00008000; |
| 19 | __HEAP_SIZE = 0x000C0000; |
| 20 | |
| 21 | /* System memory brief */ |
| 22 | MEMORY |
| 23 | { |
| 24 | ITCM (rx) : ORIGIN = 0x10000000, LENGTH = 0x00008000 |
| 25 | DTCM (rwx) : ORIGIN = 0x30000000, LENGTH = 0x00008000 |
| 26 | BRAM (rwx) : ORIGIN = 0x11000000, LENGTH = 0x00200000 |
| 27 | SRAM (rwx) : ORIGIN = 0x31000000, LENGTH = 0x00400000 |
| 28 | DDR (rwx) : ORIGIN = 0x70000000, LENGTH = 0x02000000 |
| 29 | |
| 30 | /* Dynamic load regions declared for use by FVP only |
| 31 | * These regions are mentioned in the CMake subsystem profile. |
| 32 | * Do not change the addresses here in isolation. */ |
| 33 | DDR_dynamic_model (rx) : ORIGIN = 0x90000000, LENGTH = 0x02000000 |
| 34 | DDR_dynamic_ifm (rx) : ORIGIN = 0x92000000, LENGTH = 0x01000000 |
| 35 | DDR_dynamic_ofm (rx) : ORIGIN = 0x93000000, LENGTH = 0x01000000 |
| 36 | } |
| 37 | |
| 38 | /* Linker script to place sections and symbol values. Should be used together |
| 39 | * with other linker script that defines memory regions ITCM and RAM. |
| 40 | * It references following symbols, which must be defined in code: |
| 41 | * Reset_Handler : Entry of reset handler |
| 42 | * |
| 43 | * It defines following symbols, which code can use without definition: |
| 44 | * __exidx_start |
| 45 | * __exidx_end |
| 46 | * __copy_table_start__ |
| 47 | * __copy_table_end__ |
| 48 | * __zero_table_start__ |
| 49 | * __zero_table_end__ |
| 50 | * __etext |
| 51 | * __data_start__ |
| 52 | * __preinit_array_start |
| 53 | * __preinit_array_end |
| 54 | * __init_array_start |
| 55 | * __init_array_end |
| 56 | * __fini_array_start |
| 57 | * __fini_array_end |
| 58 | * __data_end__ |
| 59 | * __bss_start__ |
| 60 | * __bss_end__ |
| 61 | * __end__ |
| 62 | * end |
| 63 | * __HeapLimit |
| 64 | * __StackLimit |
| 65 | * __StackTop |
| 66 | * __stack |
| 67 | */ |
| 68 | ENTRY(Reset_Handler) |
| 69 | |
| 70 | SECTIONS |
| 71 | { |
| 72 | .text.at_bram : |
| 73 | { |
| 74 | KEEP(*(.vectors)) |
Maksims Svecovs | bddefa3 | 2022-11-08 13:08:04 +0000 | [diff] [blame] | 75 | *(.text*) |
Kshitij Sisodia | 8c61c0a | 2022-05-17 11:16:22 +0100 | [diff] [blame] | 76 | |
| 77 | KEEP(*(.init)) |
| 78 | KEEP(*(.fini)) |
| 79 | |
| 80 | /* .ctors */ |
| 81 | *crtbegin.o(.ctors) |
| 82 | *crtbegin?.o(.ctors) |
| 83 | *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) |
| 84 | *(SORT(.ctors.*)) |
| 85 | *(.ctors) |
| 86 | |
| 87 | /* .dtors */ |
| 88 | *crtbegin.o(.dtors) |
| 89 | *crtbegin?.o(.dtors) |
| 90 | *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) |
| 91 | *(SORT(.dtors.*)) |
| 92 | *(.dtors) |
| 93 | |
| 94 | KEEP(*(.eh_frame*)) |
Maksims Svecovs | bddefa3 | 2022-11-08 13:08:04 +0000 | [diff] [blame] | 95 | |
Kshitij Sisodia | 8c61c0a | 2022-05-17 11:16:22 +0100 | [diff] [blame] | 96 | *(vtable) |
| 97 | *(.data) |
| 98 | *(.data.*) |
| 99 | . = ALIGN(4); |
| 100 | PROVIDE_HIDDEN (__preinit_array_start = .); |
| 101 | KEEP(*(.preinit_array)) |
| 102 | PROVIDE_HIDDEN (__preinit_array_end = .); |
| 103 | . = ALIGN(4); |
| 104 | PROVIDE_HIDDEN (__init_array_start = .); |
| 105 | KEEP(*(SORT(.init_array.*))) |
| 106 | KEEP(*(.init_array)) |
| 107 | PROVIDE_HIDDEN (__init_array_end = .); |
| 108 | . = ALIGN(4); |
| 109 | PROVIDE_HIDDEN (__fini_array_start = .); |
| 110 | KEEP(*(SORT(.fini_array.*))) |
| 111 | KEEP(*(.fini_array)) |
| 112 | PROVIDE_HIDDEN (__fini_array_end = .); |
| 113 | KEEP(*(.jcr*)) |
| 114 | . = ALIGN(4); |
| 115 | |
| 116 | *(.ARM.extab* .gnu.linkonce.armextab.*) |
| 117 | . = ALIGN(4); |
| 118 | |
| 119 | *(.rodata*) |
| 120 | . = ALIGN(4); |
| 121 | * (npu_driver_version) |
| 122 | . = ALIGN(4); |
| 123 | * (npu_driver_arch_version) |
| 124 | . = ALIGN(4); |
| 125 | |
| 126 | __copy_table_start__ = .; |
| 127 | . = ALIGN(4); |
| 128 | __copy_table_end__ = .; |
| 129 | } > BRAM |
| 130 | |
| 131 | __exidx_start = .; |
| 132 | .ARM.exidx.at_bram : |
| 133 | { |
| 134 | *(.ARM.exidx* .gnu.linkonce.armexidx.*) |
| 135 | } > BRAM |
| 136 | __exidx_end = .; |
| 137 | |
| 138 | .sram : |
| 139 | { |
| 140 | . = ALIGN(16); |
| 141 | /* Cache area (if used) */ |
| 142 | *(.bss.NoInit.ethos_u_cache) |
| 143 | . = ALIGN (16); |
| 144 | /* activation buffers a.k.a tensor arena when memory mode sram only or shared sram */ |
| 145 | *(.bss.NoInit.activation_buf_sram) |
| 146 | . = ALIGN(16); |
| 147 | } > SRAM AT > SRAM |
| 148 | |
| 149 | .bss : |
| 150 | { |
| 151 | . = ALIGN(4); |
| 152 | __bss_start__ = .; |
| 153 | *(.bss) |
| 154 | *(.bss.*) |
| 155 | *(COMMON) |
| 156 | . = ALIGN(4); |
| 157 | __bss_end__ = .; |
| 158 | } > BRAM |
| 159 | |
| 160 | .zero.table.at_bram : |
| 161 | { |
| 162 | . = ALIGN(4); |
| 163 | __zero_table_start__ = .; |
| 164 | |
| 165 | LONG (__bss_start__) |
| 166 | LONG ((__bss_end__ - __bss_start__)/4) /* Size is in 32-bit words */ |
| 167 | |
| 168 | __zero_table_end__ = .; |
| 169 | } > BRAM |
Maksims Svecovs | bddefa3 | 2022-11-08 13:08:04 +0000 | [diff] [blame] | 170 | |
Kshitij Sisodia | 8c61c0a | 2022-05-17 11:16:22 +0100 | [diff] [blame] | 171 | .heap (COPY) : |
| 172 | { |
| 173 | . = ALIGN(8); |
| 174 | __end__ = .; |
| 175 | PROVIDE(end = .); |
| 176 | . = . + __HEAP_SIZE; |
| 177 | . = ALIGN(8); |
| 178 | __HeapLimit = .; |
| 179 | } > BRAM |
| 180 | |
| 181 | __bram_total = ALIGN(4); |
| 182 | |
| 183 | ASSERT( __bram_total < (ORIGIN(BRAM) + LENGTH(BRAM)), "BRAM overflow") |
| 184 | |
| 185 | .stack (ORIGIN(DTCM) + LENGTH(DTCM) - __STACK_SIZE) (COPY) : |
| 186 | { |
| 187 | . = ALIGN(8); |
| 188 | __StackLimit = .; |
| 189 | . = . + __STACK_SIZE; |
| 190 | . = ALIGN(8); |
| 191 | __StackTop = .; |
| 192 | } > DTCM |
| 193 | PROVIDE(__stack = __StackTop); |
| 194 | ASSERT(__STACK_SIZE <= LENGTH(DTCM), "DTCM overflow") |
| 195 | |
| 196 | .ddr.at_ddr : |
| 197 | { |
| 198 | /* __attribute__((aligned(16))) is not handled by the CMSIS startup code. |
| 199 | * Force the alignment here as a workaround */ |
| 200 | . = ALIGN(16); |
| 201 | /* nn model's baked in input matrices */ |
| 202 | *(ifm) |
| 203 | . = ALIGN(16); |
| 204 | /* nn model's default space */ |
| 205 | *(nn_model) |
| 206 | . = ALIGN (16); |
| 207 | /* labels */ |
| 208 | *(labels) |
| 209 | . = ALIGN (16); |
Richard Burton | 973158f | 2023-11-06 14:40:28 +0000 | [diff] [blame^] | 210 | *Labels*.obj (*.rodata*) |
| 211 | . = ALIGN (16); |
Kshitij Sisodia | 8c61c0a | 2022-05-17 11:16:22 +0100 | [diff] [blame] | 212 | /* activation buffers a.k.a tensor arena when memory mode dedicated sram */ |
| 213 | *(activation_buf_dram) |
| 214 | . = ALIGN (16); |
| 215 | } > DDR AT > DDR |
| 216 | |
| 217 | } |