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Kshitij Sisodia987efae2023-02-14 16:28:40 +00001; SPDX-FileCopyrightText: Copyright 2021, 2023 Arm Limited and/or its affiliates <open-source-office@arm.com>
Kshitij Sisodia8c61c0a2022-05-17 11:16:22 +01002; SPDX-License-Identifier: Apache-2.0
3;
4; Licensed under the Apache License, Version 2.0 (the "License");
5; you may not use this file except in compliance with the License.
6; You may obtain a copy of the License at
7;
8; http://www.apache.org/licenses/LICENSE-2.0
9;
10; Unless required by applicable law or agreed to in writing, software
11; distributed under the License is distributed on an "AS IS" BASIS,
12; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
13; See the License for the specific language governing permissions and
14; limitations under the License.
15
16; *************************************************************
17; *** Scatter-Loading Description File ***
18; *************************************************************
19; Please see docs/sections/appendix.md for memory mapping
20; information.
21;
22; Note: Ethos-U NPU can access BRAM, internal SRAM and the DDR
23; sections => activation buffers and the model should
24; only be placed in those regions.
25;
26
27;---------------------------------------------------------
28; First load region (SRAM/BRAM) 2MiB region
29;---------------------------------------------------------
30LOAD_REGION_0 0x11000000 0x00200000
31{
32 ;-----------------------------------------------------
Kshitij Sisodia987efae2023-02-14 16:28:40 +000033 ; First 640K of SRAM/BRAM. Our vector table also
Kshitij Sisodia8c61c0a2022-05-17 11:16:22 +010034 ; resides here as the default INITSVTOR is 0x11000000.
35 ; We currently do not use the ITCM for any code, but
36 ; could potentially put some critical code in there
37 ; if we need to.
38 ;-----------------------------------------------------
Kshitij Sisodia987efae2023-02-14 16:28:40 +000039 bram.bin 0x11000000 0x000A0000
Kshitij Sisodia8c61c0a2022-05-17 11:16:22 +010040 {
41 *.o (RESET, +First)
42 * (InRoot$$Sections)
43
44 ; Essentially only RO (code + data)
45 .ANY (+RO)
46 }
47
48 ;-----------------------------------------------------
Kshitij Sisodia987efae2023-02-14 16:28:40 +000049 ; Next 384K of SRAM/BRAM region for RO, RW and ZI
Kshitij Sisodia8c61c0a2022-05-17 11:16:22 +010050 ; data, 8 byte aligned.
51 ;-----------------------------------------------------
Kshitij Sisodia987efae2023-02-14 16:28:40 +000052 data.bin 0x110A0000 ALIGN 8 0x00060000
Kshitij Sisodia8c61c0a2022-05-17 11:16:22 +010053 {
54 ; Any RO-DATA
55 .ANY (+RO-DATA)
56
57 ; Any R/W and/or zero initialised data
58 .ANY(+RW +ZI)
59 }
60
61 ;-----------------------------------------------------
62 ; 768 KiB of remaining part of the 1MiB BRAM used as
63 ; heap space.
64 ;-----------------------------------------------------
65 ARM_LIB_HEAP 0x11100000 EMPTY ALIGN 8 0x000C0000
66 {}
67
68 ;-----------------------------------------------------
69 ; 32 kiB of stack space occupying the DTCM region.
70 ;-----------------------------------------------------
71 ARM_LIB_STACK 0x30000000 EMPTY ALIGN 8 0x00008000
72 {}
73
74 ;-----------------------------------------------------
75 ; FPGA internal SRAM of 2MiB - reserved for activation
76 ; buffers. The total memory is 4 MiB (we are choosing
77 ; to not use the other bank). This region should have
78 ; 3 cycle read latency from both CPU and Ethos-U NPU.
79 ;-----------------------------------------------------
80 isram.bin 0x31000000 UNINIT ALIGN 16 0x00200000
81 {
82 ; Cache area (if used)
83 *.o (.bss.NoInit.ethos_u_cache)
84
85 ; activation buffers a.k.a tensor arena when
86 ; memory mode sram only or shared sram
87 *.o (.bss.NoInit.activation_buf_sram)
88 }
89}
90
91;---------------------------------------------------------
92; Second load region (DDR)
93;---------------------------------------------------------
94LOAD_REGION_1 0x70000000 0x02000000
95{
96 ;-----------------------------------------------------
97 ; 32 MiB of DDR space for neural network model,
98 ; input vectors and labels. If the activation buffer
99 ; size required by the network is bigger than the
100 ; SRAM size available, it is accommodated here.
101 ;-----------------------------------------------------
102 ddr.bin 0x70000000 ALIGN 16 0x02000000
103 {
104 ; nn model's baked in input matrices
105 *.o (ifm)
106
107 ; nn model's default space
108 *.o (nn_model)
109
110 ; labels
111 *.o (labels)
Richard Burton973158f2023-11-06 14:40:28 +0000112 Labels.o (+RO-DATA)
Kshitij Sisodia8c61c0a2022-05-17 11:16:22 +0100113
114 ; activation buffers a.k.a tensor arena when memory mode dedicated sram
115 *.o (activation_buf_dram)
116 }
117
118 ;-----------------------------------------------------
119 ; The following regions are for use by the FVP to
120 ; allow loading or dumping of dynamic data into or
121 ; from the memory. These regions are mentioned in
122 ; the CMake subsystem profile. Do not change the
123 ; addresses and sizes below in isolation.
124 ;-----------------------------------------------------
125 ; 32 MiB of model space for run-time load of model
126 ;-----------------------------------------------------
127 runtime_model 0x90000000 EMPTY ALIGN 16 0x02000000
128 {}
129
130 ;-----------------------------------------------------
131 ; 16 MiB of IFM space for run-time loading (FVP only)
132 ;-----------------------------------------------------
133 runtime_ifm 0x92000000 EMPTY ALIGN 16 0x01000000
134 {}
135
136 ;-----------------------------------------------------
137 ; 16 MiB of OFM space for run-time loading (FVP only)
138 ;-----------------------------------------------------
139 runtime_ofm 0x93000000 EMPTY ALIGN 16 0x01000000
140 {}
141}