| Kshitij Sisodia | 8c61c0a | 2022-05-17 11:16:22 +0100 | [diff] [blame] | 1 | /* |
| Richard Burton | f32a86a | 2022-11-15 11:46:11 +0000 | [diff] [blame] | 2 | * SPDX-FileCopyrightText: Copyright 2022 Arm Limited and/or its affiliates <open-source-office@arm.com> |
| Kshitij Sisodia | 8c61c0a | 2022-05-17 11:16:22 +0100 | [diff] [blame] | 3 | * SPDX-License-Identifier: Apache-2.0 |
| 4 | * |
| 5 | * Licensed under the Apache License, Version 2.0 (the "License"); |
| 6 | * you may not use this file except in compliance with the License. |
| 7 | * You may obtain a copy of the License at |
| 8 | * |
| 9 | * http://www.apache.org/licenses/LICENSE-2.0 |
| 10 | * |
| 11 | * Unless required by applicable law or agreed to in writing, software |
| 12 | * distributed under the License is distributed on an "AS IS" BASIS, |
| 13 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 14 | * See the License for the specific language governing permissions and |
| 15 | * limitations under the License. |
| 16 | */ |
| 17 | |
| 18 | #ifndef MEM_REGION_DEFS_H |
| 19 | #define MEM_REGION_DEFS_H |
| 20 | |
| 21 | #define ITCM_SIZE (0x00080000) /* ITCM size */ |
| 22 | #define DTCM_BLK_SIZE (0x00020000) /* DTCM size, 4 banks of this size available */ |
| 23 | #define BRAM_SIZE (0x00200000) /* BRAM size */ |
| 24 | #define ISRAM0_SIZE (0x00200000) /* ISRAM0 size */ |
| 25 | #define ISRAM1_SIZE (0x00200000) /* ISRAM1 size */ |
| 26 | #define QSPI_SRAM_SIZE (0x00800000) /* QSPI Flash size */ |
| 27 | #define DDR4_BLK_SIZE (0x10000000) /* DDR4 block size */ |
| 28 | |
| 29 | #define ITCM_BASE_NS (0x00000000) /* Instruction TCM Non-Secure base address */ |
| 30 | #define BRAM_BASE_NS (0x01000000) /* CODE SRAM Non-Secure base address */ |
| 31 | #define DTCM0_BASE_NS (0x20000000) /* Data TCM block 0 Non-Secure base address */ |
| 32 | #define DTCM1_BASE_NS (0x20020000) /* Data TCM block 1 Non-Secure base address */ |
| 33 | #define DTCM2_BASE_NS (0x20040000) /* Data TCM block 2 Non-Secure base address */ |
| 34 | #define DTCM3_BASE_NS (0x20060000) /* Data TCM block 3 Non-Secure base address */ |
| 35 | #define ISRAM0_BASE_NS (0x21000000) /* Internal SRAM Area Non-Secure base address */ |
| 36 | #define ISRAM1_BASE_NS (0x21100000) /* Internal SRAM Area Non-Secure base address */ |
| 37 | #define QSPI_SRAM_BASE_NS (0x28000000) /* QSPI SRAM Non-Secure base address */ |
| 38 | #define DDR4_BLK0_BASE_NS (0x60000000) /* DDR4 block 0 Non-Secure base address */ |
| 39 | #define DDR4_BLK1_BASE_NS (0x80000000) /* DDR4 block 1 Non-Secure base address */ |
| 40 | #define DDR4_BLK2_BASE_NS (0xA0000000) /* DDR4 block 2 Non-Secure base address */ |
| 41 | #define DDR4_BLK3_BASE_NS (0xC0000000) /* DDR4 block 3 Non-Secure base address */ |
| 42 | |
| 43 | #define ITCM_BASE_S (0x10000000) /* Instruction TCM Secure base address */ |
| 44 | #define BRAM_BASE_S (0x11000000) /* CODE SRAM Secure base address */ |
| 45 | #define DTCM0_BASE_S (0x30000000) /* Data TCM block 0 Secure base address */ |
| 46 | #define DTCM1_BASE_S (0x30020000) /* Data TCM block 1 Secure base address */ |
| 47 | #define DTCM2_BASE_S (0x30040000) /* Data TCM block 2 Secure base address */ |
| 48 | #define DTCM3_BASE_S (0x30060000) /* Data TCM block 3 Secure base address */ |
| 49 | #define ISRAM0_BASE_S (0x31000000) /* Internal SRAM Area Secure base address */ |
| 50 | #define ISRAM1_BASE_S (0x31100000) /* Internal SRAM Area Secure base address */ |
| 51 | #define DDR4_BLK0_BASE_S (0x70000000) /* DDR4 block 0 Secure base address */ |
| 52 | #define DDR4_BLK1_BASE_S (0x90000000) /* DDR4 block 1 Secure base address */ |
| 53 | #define DDR4_BLK2_BASE_S (0xB0000000) /* DDR4 block 2 Secure base address */ |
| 54 | #define DDR4_BLK3_BASE_S (0xD0000000) /* DDR4 block 3 Secure base address */ |
| 55 | |
| 56 | #endif /* MEM_REGION_DEFS_H */ |