| Kshitij Sisodia | 8c61c0a | 2022-05-17 11:16:22 +0100 | [diff] [blame] | 1 | /* |
| Richard Burton | f32a86a | 2022-11-15 11:46:11 +0000 | [diff] [blame] | 2 | * SPDX-FileCopyrightText: Copyright 2022 Arm Limited and/or its affiliates <open-source-office@arm.com> |
| Kshitij Sisodia | 8c61c0a | 2022-05-17 11:16:22 +0100 | [diff] [blame] | 3 | * SPDX-License-Identifier: Apache-2.0 |
| 4 | * |
| 5 | * Licensed under the Apache License, Version 2.0 (the "License"); |
| 6 | * you may not use this file except in compliance with the License. |
| 7 | * You may obtain a copy of the License at |
| 8 | * |
| 9 | * http://www.apache.org/licenses/LICENSE-2.0 |
| 10 | * |
| 11 | * Unless required by applicable law or agreed to in writing, software |
| 12 | * distributed under the License is distributed on an "AS IS" BASIS, |
| 13 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 14 | * See the License for the specific language governing permissions and |
| 15 | * limitations under the License. |
| 16 | */ |
| 17 | |
| 18 | #ifndef PERIPHERAL_IRQS_H |
| 19 | #define PERIPHERAL_IRQS_H |
| 20 | |
| 21 | /******************************************************************************/ |
| 22 | /* Peripheral interrupt numbers */ |
| 23 | /******************************************************************************/ |
| 24 | |
| 25 | /* ------------------- Cortex-M Processor Exceptions Numbers -------------- */ |
| 26 | /* -14 to -1 should be defined by the system header */ |
| 27 | /* ---------------------- Core Specific Interrupt Numbers ------------------*/ |
| 28 | #define NONSEC_WATCHDOG_RESET_IRQn ( 0) /* Non-Secure Watchdog Reset Interrupt */ |
| 29 | #define NONSEC_WATCHDOG_IRQn ( 1) /* Non-Secure Watchdog Interrupt */ |
| 30 | #define S32K_TIMER_IRQn ( 2) /* S32K Timer Interrupt */ |
| 31 | #define TIMER0_IRQn ( 3) /* TIMER 0 Interrupt */ |
| 32 | #define TIMER1_IRQn ( 4) /* TIMER 1 Interrupt */ |
| 33 | #define TIMER2_IRQn ( 5) /* TIMER 2 Interrupt */ |
| 34 | #define MPC_IRQn ( 9) /* MPC Combined () Interrupt */ |
| 35 | #define PPC_IRQn (10) /* PPC Combined () Interrupt */ |
| 36 | #define MSC_IRQn (11) /* MSC Combined () Interrput */ |
| 37 | #define BRIDGE_ERROR_IRQn (12) /* Bridge Error Combined () Interrupt */ |
| 38 | #define MGMT_PPU_IRQn (14) /* MGMT_PPU */ |
| 39 | #define EthosU_IRQn (16) /* Ethos-Uxx Interrupt */ |
| 40 | #define CPU0_PPU_IRQn (16) /* CPU0_PPU */ |
| 41 | #define DEBUG_PPU_IRQn (26) /* DEBUG_PPU */ |
| 42 | #define TIMER3_AON_IRQn (27) /* TIMER3_AON */ |
| 43 | #define CPU0CTIIQ0_IRQn (28) /* CPU0CTIIQ0 */ |
| 44 | #define CPU0CTIIQ01_IRQn (29) /* CPU0CTIIQ01 */ |
| 45 | |
| 46 | #define SYS_TSTAMP_COUNTER_IRQn (32) /* System timestamp counter interrupt */ |
| 47 | |
| 48 | /* ---------------------- CMSDK Specific Interrupt Numbers ----------------- */ |
| 49 | #define UARTRX0_IRQn (33) /* UART 0 RX Interrupt */ |
| 50 | #define UARTTX0_IRQn (34) /* UART 0 TX Interrupt */ |
| 51 | #define UARTRX1_IRQn (35) /* UART 1 RX Interrupt */ |
| 52 | #define UARTTX1_IRQn (36) /* UART 1 TX Interrupt */ |
| 53 | #define UARTRX2_IRQn (37) /* UART 2 RX Interrupt */ |
| 54 | #define UARTTX2_IRQn (38) /* UART 2 TX Interrupt */ |
| 55 | #define UARTRX3_IRQn (39) /* UART 3 RX Interrupt */ |
| 56 | #define UARTTX3_IRQn (40) /* UART 3 TX Interrupt */ |
| 57 | #define UARTRX4_IRQn (41) /* UART 4 RX Interrupt */ |
| 58 | #define UARTTX4_IRQn (42) /* UART 4 TX Interrupt */ |
| 59 | #define UART0_IRQn (43) /* UART 0 combined Interrupt */ |
| 60 | #define UART1_IRQn (44) /* UART 1 combined Interrupt */ |
| 61 | #define UART2_IRQn (45) /* UART 2 combined Interrupt */ |
| 62 | #define UART3_IRQn (46) /* UART 3 combined Interrupt */ |
| 63 | #define UART4_IRQn (47) /* UART 4 combined Interrupt */ |
| 64 | #define UARTOVF_IRQn (48) /* UART 0,1,2,3 and 4 Overflow Interrupt */ |
| 65 | #define ETHERNET_IRQn (49) /* Ethernet Interrupt */ |
| 66 | #define I2S_IRQn (50) /* I2S Interrupt */ |
| 67 | #define TSC_IRQn (51) /* Touch Screen Interrupt */ |
| 68 | #define SPI2_IRQn (53) /* SPI 2 Interrupt */ |
| 69 | #define SPI3_IRQn (54) /* SPI 3 Interrupt */ |
| 70 | #define SPI4_IRQn (55) /* SPI 4 Interrupt */ |
| 71 | |
| 72 | #define GPIO0_IRQn (69) /* GPIO 0 Combined Interrupt */ |
| 73 | #define GPIO1_IRQn (70) /* GPIO 1 Combined Interrupt */ |
| 74 | #define GPIO2_IRQn (71) /* GPIO 2 Combined Interrupt */ |
| 75 | #define GPIO3_IRQn (72) /* GPIO 3 Combined Interrupt */ |
| 76 | |
| 77 | #define GPIO0_0_IRQn (73) /* All P0 I/O pins used as irq source */ |
| 78 | #define GPIO0_1_IRQn (74) /* There are 16 pins in total */ |
| 79 | #define GPIO0_2_IRQn (75) |
| 80 | #define GPIO0_3_IRQn (76) |
| 81 | #define GPIO0_4_IRQn (77) |
| 82 | #define GPIO0_5_IRQn (78) |
| 83 | #define GPIO0_6_IRQn (79) |
| 84 | #define GPIO0_7_IRQn (80) |
| 85 | #define GPIO0_8_IRQn (81) |
| 86 | #define GPIO0_9_IRQn (82) |
| 87 | #define GPIO0_10_IRQn (83) |
| 88 | #define GPIO0_11_IRQn (84) |
| 89 | #define GPIO0_12_IRQn (85) |
| 90 | #define GPIO0_13_IRQn (86) |
| 91 | #define GPIO0_14_IRQn (87) |
| 92 | #define GPIO0_15_IRQn (88) |
| 93 | #define GPIO1_0_IRQn (89) /* All P1 I/O pins used as irq source */ |
| 94 | #define GPIO1_1_IRQn (90) /* There are 16 pins in total */ |
| 95 | #define GPIO1_2_IRQn (91) |
| 96 | #define GPIO1_3_IRQn (92) |
| 97 | #define GPIO1_4_IRQn (93) |
| 98 | #define GPIO1_5_IRQn (94) |
| 99 | #define GPIO1_6_IRQn (95) |
| 100 | #define GPIO1_7_IRQn (96) |
| 101 | #define GPIO1_8_IRQn (97) |
| 102 | #define GPIO1_9_IRQn (98) |
| 103 | #define GPIO1_10_IRQn (99) |
| 104 | #define GPIO1_11_IRQn (100) |
| 105 | #define GPIO1_12_IRQn (101) |
| 106 | #define GPIO1_13_IRQn (102) |
| 107 | #define GPIO1_14_IRQn (103) |
| 108 | #define GPIO1_15_IRQn (104) |
| 109 | #define GPIO2_0_IRQn (105) /* All P2 I/O pins used as irq source */ |
| 110 | #define GPIO2_1_IRQn (106) /* There are 15 pins in total */ |
| 111 | #define GPIO2_2_IRQn (107) |
| 112 | #define GPIO2_3_IRQn (108) |
| 113 | #define GPIO2_4_IRQn (109) |
| 114 | #define GPIO2_5_IRQn (110) |
| 115 | #define GPIO2_6_IRQn (111) |
| 116 | #define GPIO2_7_IRQn (112) |
| 117 | #define GPIO2_8_IRQn (113) |
| 118 | #define GPIO2_9_IRQn (114) |
| 119 | #define GPIO2_10_IRQn (115) |
| 120 | #define GPIO2_11_IRQn (116) |
| 121 | #define GPIO2_12_IRQn (117) |
| 122 | #define GPIO2_13_IRQn (118) |
| 123 | #define GPIO2_14_IRQn (119) |
| 124 | #define GPIO2_15_IRQn (120) |
| 125 | #define GPIO3_0_IRQn (121) /* All P3 I/O pins used as irq source */ |
| 126 | #define GPIO3_1_IRQn (122) /* There are 4 pins in total */ |
| 127 | #define GPIO3_2_IRQn (123) |
| 128 | #define GPIO3_3_IRQn (124) |
| 129 | #define UARTRX5_IRQn (125) /* UART 5 RX Interrupt */ |
| 130 | #define UARTTX5_IRQn (126) /* UART 5 TX Interrupt */ |
| 131 | #define UART5_IRQn (127) /* UART 5 combined Interrupt */ |
| 132 | /* #undef HDCLCD_IRQn */ |
| 133 | |
| 134 | #endif /* PERIPHERAL_IRQS_H */ |