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review.mlplatform.org / ml / ethos-u / ml-embedded-evaluation-kit / a1256e3881d1ec3e77b341dbb0c5c5dbf7ab3247 / . / source / hal / platform / mps3 / source / include / device_mps3.h
blob: 445965d50df851c106794f5ca0cedff876b54cff [file] [log] [blame]
alexander3c798932021-03-26 21:42:19 +0000[diff] [blame]1/*
Kshitij Sisodiaa1256e32022-02-23 14:40:45 +0000[diff] [blame^]2 * Copyright (c) 2021-2022 Arm Limited. All rights reserved.
alexander3c798932021-03-26 21:42:19 +0000[diff] [blame]3 * SPDX-License-Identifier: Apache-2.0
4 *
5 * Licensed under the Apache License, Version 2.0 (the "License");
6 * you may not use this file except in compliance with the License.
7 * You may obtain a copy of the License at
8 *
9 * http://www.apache.org/licenses/LICENSE-2.0
10 *
11 * Unless required by applicable law or agreed to in writing, software
12 * distributed under the License is distributed on an "AS IS" BASIS,
13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14 * See the License for the specific language governing permissions and
15 * limitations under the License.
16 */
17#ifndef DEVICE_MPS3_H
18#define DEVICE_MPS3_H
19
20#ifdef __cplusplus
21extern "C" {
22#endif
23
alexander3c798932021-03-26 21:42:19 +0000[diff] [blame]24#include "smm_mps3.h" /* Memory map for MPS3. */
25
26#include <stdio.h>
27
Kshitij Sisodia105ed712021-10-04 14:31:25 +0100[diff] [blame]28#define PERIF_CLK (25000000) /* Clock source for APB peripherals */
29
alexander3c798932021-03-26 21:42:19 +0000[diff] [blame]30typedef struct _CMSDK_UART_TypeDef_
31{
32 __IO uint32_t DATA; /* Offset: 0x000 (R/W) Data Register. */
33 __IO uint32_t STATE; /* Offset: 0x004 (R/W) Status Register. */
34 __IO uint32_t CTRL; /* Offset: 0x008 (R/W) Control Register. */
35
36 union {
37 __I uint32_t INTSTATUS; /* Offset: 0x00C (R/ ) Interrupt Status Register. */
38 __O uint32_t INTCLEAR; /* Offset: 0x00C ( /W) Interrupt Clear Register. */
39 };
40 __IO uint32_t BAUDDIV; /* Offset: 0x010 (R/W) Baudrate Divider Register. */
41
42} CMSDK_UART_TypeDef;
43
44#define CMSDK_UART0 ((CMSDK_UART_TypeDef *)CMSDK_UART0_BASE)
45
46/* CMSDK_UART DATA Register Definitions. */
47#define CMSDK_UART_DATA_Pos 0 /* CMSDK_UART_DATA_Pos: DATA Position. */
48#define CMSDK_UART_DATA_Msk (0xFFul << CMSDK_UART_DATA_Pos) /* CMSDK_UART DATA: DATA Mask. */
49
50/* CMSDK_UART STATE Register Definitions. */
51#define CMSDK_UART_STATE_RXOR_Pos 3 /* CMSDK_UART STATE: RXOR Position. */
52#define CMSDK_UART_STATE_RXOR_Msk (0x1ul << CMSDK_UART_STATE_RXOR_Pos) /* CMSDK_UART STATE: RXOR Mask. */
53
54#define CMSDK_UART_STATE_TXOR_Pos 2 /* CMSDK_UART STATE: TXOR Position. */
55#define CMSDK_UART_STATE_TXOR_Msk (0x1ul << CMSDK_UART_STATE_TXOR_Pos) /* CMSDK_UART STATE: TXOR Mask. */
56
57#define CMSDK_UART_STATE_RXBF_Pos 1 /* CMSDK_UART STATE: RXBF Position. */
58#define CMSDK_UART_STATE_RXBF_Msk (0x1ul << CMSDK_UART_STATE_RXBF_Pos) /* CMSDK_UART STATE: RXBF Mask. */
59
60#define CMSDK_UART_STATE_TXBF_Pos 0 /* CMSDK_UART STATE: TXBF Position. */
61#define CMSDK_UART_STATE_TXBF_Msk (0x1ul << CMSDK_UART_STATE_TXBF_Pos ) /* CMSDK_UART STATE: TXBF Mask. */
62
63/* CMSDK_UART CTRL Register Definitions. */
64#define CMSDK_UART_CTRL_HSTM_Pos 6 /* CMSDK_UART CTRL: HSTM Position. */
65#define CMSDK_UART_CTRL_HSTM_Msk (0x01ul << CMSDK_UART_CTRL_HSTM_Pos) /* CMSDK_UART CTRL: HSTM Mask. */
66
67#define CMSDK_UART_CTRL_RXORIRQEN_Pos 5 /* CMSDK_UART CTRL: RXORIRQEN Position. */
68#define CMSDK_UART_CTRL_RXORIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_RXORIRQEN_Pos) /* CMSDK_UART CTRL: RXORIRQEN Mask. */
69
70#define CMSDK_UART_CTRL_TXORIRQEN_Pos 4 /* CMSDK_UART CTRL: TXORIRQEN Position. */
71#define CMSDK_UART_CTRL_TXORIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_TXORIRQEN_Pos) /* CMSDK_UART CTRL: TXORIRQEN Mask. */
72
73#define CMSDK_UART_CTRL_RXIRQEN_Pos 3 /* CMSDK_UART CTRL: RXIRQEN Position. */
74#define CMSDK_UART_CTRL_RXIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_RXIRQEN_Pos) /* CMSDK_UART CTRL: RXIRQEN Mask. */
75
76#define CMSDK_UART_CTRL_TXIRQEN_Pos 2 /* CMSDK_UART CTRL: TXIRQEN Position. */
77#define CMSDK_UART_CTRL_TXIRQEN_Msk (0x01ul << CMSDK_UART_CTRL_TXIRQEN_Pos) /* CMSDK_UART CTRL: TXIRQEN Mask. */
78
79#define CMSDK_UART_CTRL_RXEN_Pos 1 /* CMSDK_UART CTRL: RXEN Position. */
80#define CMSDK_UART_CTRL_RXEN_Msk (0x01ul << CMSDK_UART_CTRL_RXEN_Pos) /* CMSDK_UART CTRL: RXEN Mask. */
81
82#define CMSDK_UART_CTRL_TXEN_Pos 0 /* CMSDK_UART CTRL: TXEN Position. */
83#define CMSDK_UART_CTRL_TXEN_Msk (0x01ul << CMSDK_UART_CTRL_TXEN_Pos) /* CMSDK_UART CTRL: TXEN Mask. */
84
85/* CMSDK_UART INTSTATUS\INTCLEAR Register Definitions. */
86#define CMSDK_UART_INT_RXORIRQ_Pos 3 /* CMSDK_UART INT: RXORIRQ Position. */
87#define CMSDK_UART_INT_RXORIRQ_Msk (0x01ul << CMSDK_UART_INT_RXORIRQ_Pos) /* CMSDK_UART INT: RXORIRQ Mask. */
88
89#define CMSDK_UART_INT_TXORIRQ_Pos 2 /* CMSDK_UART INT: TXORIRQ Position. */
90#define CMSDK_UART_INT_TXORIRQ_Msk (0x01ul << CMSDK_UART_INT_TXORIRQ_Pos) /* CMSDK_UART INT: TXORIRQ Mask. */
91
92#define CMSDK_UART_INT_RXIRQ_Pos 1 /* CMSDK_UART INT: RXIRQ Position. */
93#define CMSDK_UART_INT_RXIRQ_Msk (0x01ul << CMSDK_UART_INT_RXIRQ_Pos) /* CMSDK_UART INT: RXIRQ Mask. */
94
95#define CMSDK_UART_INT_TXIRQ_Pos 0 /* CMSDK_UART INT: TXIRQ Position. */
96#define CMSDK_UART_INT_TXIRQ_Msk (0x01ul << CMSDK_UART_INT_TXIRQ_Pos) /* CMSDK_UART INT: TXIRQ Mask. */
97
98/* CMSDK_UART BAUDDIV Register Definitions. */
99#define CMSDK_UART_BAUDDIV_Pos 0 /* CMSDK_UART BAUDDIV: BAUDDIV Position. */
100#define CMSDK_UART_BAUDDIV_Msk (0xFFFFFul << CMSDK_UART_BAUDDIV_Pos)
101
102/**
103 * @brief Gets the core clock set for MPS3.
104 * @return Clock value in Hz.
105 **/
106uint32_t GetMPS3CoreClock(void);
107
108#ifdef __cplusplus
109}
110#endif
111
112#endif /* DEVICE_MPS3_H */