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alexander3c798932021-03-26 21:42:19 +00001/*
Kshitij Sisodiaa1256e32022-02-23 14:40:45 +00002 * Copyright (c) 2022 Arm Limited. All rights reserved.
alexander3c798932021-03-26 21:42:19 +00003 * SPDX-License-Identifier: Apache-2.0
4 *
5 * Licensed under the Apache License, Version 2.0 (the "License");
6 * you may not use this file except in compliance with the License.
7 * You may obtain a copy of the License at
8 *
9 * http://www.apache.org/licenses/LICENSE-2.0
10 *
11 * Unless required by applicable law or agreed to in writing, software
12 * distributed under the License is distributed on an "AS IS" BASIS,
13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14 * See the License for the specific language governing permissions and
15 * limitations under the License.
16 */
alexander3c798932021-03-26 21:42:19 +000017
Kshitij Sisodiaa1256e32022-02-23 14:40:45 +000018#include "platform_drivers.h"
alexander3c798932021-03-26 21:42:19 +000019
Kshitij Sisodiaa1256e32022-02-23 14:40:45 +000020#include "uart_stdout.h" /* stdout over UART. */
21#include "log_macros.h" /* Logging functions */
22#include "device_mps3.h" /* FPGA level definitions and functions. */
23
24#include <string.h> /* For strncpy */
25
26/**
27 * @brief Checks if the platform is valid by checking
28 * the CPU ID for the FPGA implementation against
29 * the register from the CPU core.
30 * @return 0 if successful, 1 otherwise
31 */
32static int verify_platform(void);
33
34int platform_init(void)
35{
36 int err = 0;
37
38 SystemCoreClockUpdate(); /* From start up code */
39
40 /* UART init - will enable valid use of printf (stdout
41 * re-directed at this UART (UART0) */
42 UartStdOutInit();
43
44 if (0 != (err = verify_platform())) {
45 return err;
46 }
47
48 /** TODO: Add ARM NPU and TA init here */
49 return 0;
50}
51
52void platform_release(void)
53{
54 __disable_irq();
55}
56
57void platform_name(char* name, size_t size)
58{
59 strncpy(name, DESIGN_NAME, size);
60}
61
Kshitij Sisodiaf9c19ea2021-05-07 16:08:14 +010062#define CREATE_MASK(msb, lsb) (int)(((1U << ((msb) - (lsb) + 1)) - 1) << (lsb))
63#define MASK_BITS(arg, msb, lsb) (int)((arg) & CREATE_MASK(msb, lsb))
64#define EXTRACT_BITS(arg, msb, lsb) (int)(MASK_BITS(arg, msb, lsb) >> (lsb))
alexander3c798932021-03-26 21:42:19 +000065
Kshitij Sisodiaa1256e32022-02-23 14:40:45 +000066static int verify_platform(void)
alexander3c798932021-03-26 21:42:19 +000067{
alexander3c798932021-03-26 21:42:19 +000068 uint32_t id = 0;
69 uint32_t fpgaid = 0;
70 uint32_t apnote = 0;
71 uint32_t rev = 0;
72 uint32_t aid = 0;
73 uint32_t fpga_clk = 0;
Kshitij Sisodiaf9c19ea2021-05-07 16:08:14 +010074 const uint32_t ascii_A = (uint32_t)('A');
alexander3c798932021-03-26 21:42:19 +000075
76 /* Initialise the LEDs as the switches are */
77 MPS3_FPGAIO->LED = MPS3_FPGAIO->SWITCHES & 0xFF;
alexander3c798932021-03-26 21:42:19 +000078
Kshitij Sisodiaa1256e32022-02-23 14:40:45 +000079 info("Processor internal clock: %" PRIu32 "Hz\n", GetMPS3CoreClock());
alexander3c798932021-03-26 21:42:19 +000080
alexander3c798932021-03-26 21:42:19 +000081 /* Get revision information from various registers */
82 rev = MPS3_SCC->CFG_REG4;
83 fpgaid = MPS3_SCC->SCC_ID;
84 aid = MPS3_SCC->SCC_AID;
85 apnote = EXTRACT_BITS(fpgaid, 15, 4);
86 fpga_clk = GetMPS3CoreClock();
87
Kshitij Sisodiaf9c19ea2021-05-07 16:08:14 +010088 info("V2M-MPS3 revision %c\n\n", (char)(rev + ascii_A));
89 info("Application Note AN%" PRIx32 ", Revision %c\n", apnote,
90 (char)(EXTRACT_BITS(aid, 23, 20) + ascii_A));
alexander3c798932021-03-26 21:42:19 +000091 info("MPS3 build %d\n", EXTRACT_BITS(aid, 31, 24));
Kshitij Sisodiaf9c19ea2021-05-07 16:08:14 +010092 info("MPS3 core clock has been set to: %" PRIu32 "Hz\n", fpga_clk);
alexander3c798932021-03-26 21:42:19 +000093
94 /* Display CPU ID */
95 id = SCB->CPUID;
Kshitij Sisodiaf9c19ea2021-05-07 16:08:14 +010096 info("CPU ID: 0x%08" PRIx32 "\n", id);
alexander3c798932021-03-26 21:42:19 +000097
98 if(EXTRACT_BITS(id, 15, 8) == 0xD2) {
99 if (EXTRACT_BITS(id, 7, 4) == 2) {
100 info ("CPU: Cortex-M55 r%dp%d\n\n",
101 EXTRACT_BITS(id, 23, 20),EXTRACT_BITS(id, 3, 0));
102#if defined (CPU_CORTEX_M55)
103 /* CPU ID should be "0x_41_0f_d2_20" for Cortex-M55 */
104 return 0;
105#endif /* CPU_CORTEX_M55 */
106 } else if (EXTRACT_BITS(id, 7, 4) == 1) {
107 info ("CPU: Cortex-M33 r%dp%d\n\n",
108 EXTRACT_BITS(id, 23, 20),EXTRACT_BITS(id, 3, 0));
109#if defined (CPU_CORTEX_M33)
110 return 0;
111#endif /* CPU_CORTEX_M33 */
112 } else if (EXTRACT_BITS(id, 7, 4) == 0) {
113 info ("CPU: Cortex-M23 r%dp%d\n\n",
114 EXTRACT_BITS(id, 23, 20),EXTRACT_BITS(id, 3, 0));
115 } else {
116 info ("CPU: Cortex-M processor family");
117 }
118 } else if (EXTRACT_BITS(id, 15, 8) == 0xC6) {
119 info ("CPU: Cortex-M%d+ r%dp%d\n\n",
120 EXTRACT_BITS(id, 7, 4), EXTRACT_BITS(id, 23, 20),
121 EXTRACT_BITS(id, 3, 0));
122 } else {
123 info ("CPU: Cortex-M%d r%dp%d\n\n",
124 EXTRACT_BITS(id, 7, 4), EXTRACT_BITS(id, 23, 20),
125 EXTRACT_BITS(id, 3, 0));
126 }
alexander3c798932021-03-26 21:42:19 +0000127
128 /* If the CPU is anything other than M33 or M55, we return 1 */
129 printf_err("CPU mismatch!\n");
130 return 1;
131}