Kshitij Sisodia | f9c19ea | 2021-05-07 16:08:14 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2021 Arm Limited. All rights reserved. |
| 3 | * SPDX-License-Identifier: Apache-2.0 |
| 4 | * |
| 5 | * Licensed under the Apache License, Version 2.0 (the "License"); |
| 6 | * you may not use this file except in compliance with the License. |
| 7 | * You may obtain a copy of the License at |
| 8 | * |
| 9 | * http://www.apache.org/licenses/LICENSE-2.0 |
| 10 | * |
| 11 | * Unless required by applicable law or agreed to in writing, software |
| 12 | * distributed under the License is distributed on an "AS IS" BASIS, |
| 13 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 14 | * See the License for the specific language governing permissions and |
| 15 | * limitations under the License. |
| 16 | */ |
| 17 | |
Kshitij Sisodia | 7e56d8f | 2022-04-11 10:34:29 +0100 | [diff] [blame] | 18 | __STACK_SIZE = 0x00008000; |
Kshitij Sisodia | 661959c | 2021-11-24 10:39:52 +0000 | [diff] [blame] | 19 | __HEAP_SIZE = 0x000C0000; |
Kshitij Sisodia | f9c19ea | 2021-05-07 16:08:14 +0100 | [diff] [blame] | 20 | |
| 21 | /* System memory brief */ |
| 22 | MEMORY |
| 23 | { |
| 24 | ITCM (rx) : ORIGIN = 0x00000000, LENGTH = 0x00080000 |
| 25 | DTCM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00080000 |
Kshitij Sisodia | 661959c | 2021-11-24 10:39:52 +0000 | [diff] [blame] | 26 | BRAM (rwx) : ORIGIN = 0x11000000, LENGTH = 0x00100000 |
| 27 | SRAM (rwx) : ORIGIN = 0x31000000, LENGTH = 0x00200000 |
Kshitij Sisodia | f9c19ea | 2021-05-07 16:08:14 +0100 | [diff] [blame] | 28 | DDR (rwx) : ORIGIN = 0x70000000, LENGTH = 0x02000000 |
| 29 | } |
| 30 | |
| 31 | /* Linker script to place sections and symbol values. Should be used together |
| 32 | * with other linker script that defines memory regions ITCM and RAM. |
| 33 | * It references following symbols, which must be defined in code: |
| 34 | * Reset_Handler : Entry of reset handler |
| 35 | * |
| 36 | * It defines following symbols, which code can use without definition: |
| 37 | * __exidx_start |
| 38 | * __exidx_end |
| 39 | * __copy_table_start__ |
| 40 | * __copy_table_end__ |
| 41 | * __zero_table_start__ |
| 42 | * __zero_table_end__ |
| 43 | * __etext |
| 44 | * __data_start__ |
| 45 | * __preinit_array_start |
| 46 | * __preinit_array_end |
| 47 | * __init_array_start |
| 48 | * __init_array_end |
| 49 | * __fini_array_start |
| 50 | * __fini_array_end |
| 51 | * __data_end__ |
| 52 | * __bss_start__ |
| 53 | * __bss_end__ |
| 54 | * __end__ |
| 55 | * end |
| 56 | * __HeapLimit |
| 57 | * __StackLimit |
| 58 | * __StackTop |
| 59 | * __stack |
| 60 | */ |
| 61 | ENTRY(Reset_Handler) |
| 62 | |
| 63 | SECTIONS |
| 64 | { |
| 65 | .text.at_itcm : |
| 66 | { |
| 67 | KEEP(*(.vectors)) |
Éanna Ó Catháin | 8f95887 | 2021-09-15 09:32:30 +0100 | [diff] [blame] | 68 | |
| 69 | /** |
| 70 | * All code goes here, with one exception of |
| 71 | * all_ops_resolver object file. This code |
| 72 | * instead placed on BRAM. See comment in the |
| 73 | * BRAM section for details. |
| 74 | **/ |
| 75 | *(EXCLUDE_FILE(*all_ops_resolver.o *hal.c.obj) .text*) |
Kshitij Sisodia | f9c19ea | 2021-05-07 16:08:14 +0100 | [diff] [blame] | 76 | |
| 77 | KEEP(*(.init)) |
| 78 | KEEP(*(.fini)) |
| 79 | |
| 80 | /* .ctors */ |
| 81 | *crtbegin.o(.ctors) |
| 82 | *crtbegin?.o(.ctors) |
| 83 | *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) |
| 84 | *(SORT(.ctors.*)) |
| 85 | *(.ctors) |
| 86 | |
| 87 | /* .dtors */ |
| 88 | *crtbegin.o(.dtors) |
| 89 | *crtbegin?.o(.dtors) |
| 90 | *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) |
| 91 | *(SORT(.dtors.*)) |
| 92 | *(.dtors) |
| 93 | |
| 94 | KEEP(*(.eh_frame*)) |
| 95 | } > ITCM |
| 96 | |
Kshitij Sisodia | f9c19ea | 2021-05-07 16:08:14 +0100 | [diff] [blame] | 97 | __exidx_start = .; |
| 98 | .ARM.exidx.at_itcm : |
| 99 | { |
| 100 | *(.ARM.exidx* .gnu.linkonce.armexidx.*) |
| 101 | } > ITCM |
| 102 | __exidx_end = .; |
| 103 | |
| 104 | .zero.table.at_itcm : |
| 105 | { |
| 106 | . = ALIGN(4); |
| 107 | __zero_table_start__ = .; |
| 108 | |
| 109 | LONG (__bss_start__) |
| 110 | LONG ((__bss_end__ - __bss_start__)/4) /* Size is in 32-bit words */ |
| 111 | |
| 112 | __zero_table_end__ = .; |
| 113 | } > ITCM |
| 114 | |
| 115 | .copy.table.at_itcm : |
| 116 | { |
| 117 | . = ALIGN(4); |
| 118 | __copy_table_start__ = .; |
| 119 | |
| 120 | /* Section to be copied - part 1: any data to be placed in BRAM */ |
| 121 | LONG (__etext) |
| 122 | LONG (__data_start__) |
| 123 | LONG ((__data_end__ - __data_start__)/4) /* Size is in 32-bit words */ |
| 124 | |
| 125 | /* Section to be copied - part 2: RO data for for DTCM */ |
| 126 | LONG (__etext2) |
| 127 | LONG (__ro_data_start__) |
| 128 | LONG ((__ro_data_end__ - __ro_data_start__)/4) /* Size is in 32-bit words */ |
| 129 | |
| 130 | __copy_table_end__ = .; |
| 131 | } > ITCM |
| 132 | |
| 133 | __itcm_total = ALIGN(4); |
| 134 | |
| 135 | ASSERT( __itcm_total < (ORIGIN(ITCM) + LENGTH(ITCM)), "ITCM overflow") |
| 136 | |
| 137 | .sram : |
| 138 | { |
| 139 | . = ALIGN(16); |
Isabella Gottardi | 118f73e | 2021-09-16 17:54:35 +0100 | [diff] [blame] | 140 | /* Cache area (if used) */ |
| 141 | *(.bss.NoInit.ethos_u_cache) |
| 142 | . = ALIGN (16); |
| 143 | /* activation buffers a.k.a tensor arena when memory mode sram only or shared sram */ |
| 144 | *(.bss.NoInit.activation_buf_sram) |
Kshitij Sisodia | f9c19ea | 2021-05-07 16:08:14 +0100 | [diff] [blame] | 145 | . = ALIGN(16); |
| 146 | } > SRAM AT > SRAM |
| 147 | |
| 148 | .bss : |
| 149 | { |
| 150 | . = ALIGN(4); |
| 151 | __bss_start__ = .; |
| 152 | *(.bss) |
| 153 | *(.bss.*) |
| 154 | *(COMMON) |
| 155 | . = ALIGN(4); |
| 156 | __bss_end__ = .; |
| 157 | } > DTCM AT > DTCM |
| 158 | |
| 159 | .stack (ORIGIN(DTCM) + LENGTH(DTCM) - __STACK_SIZE) (COPY) : |
| 160 | { |
| 161 | . = ALIGN(8); |
| 162 | __StackLimit = .; |
| 163 | . = . + __STACK_SIZE; |
| 164 | . = ALIGN(8); |
| 165 | __StackTop = .; |
| 166 | } > DTCM |
| 167 | PROVIDE(__stack = __StackTop); |
| 168 | ASSERT( |
| 169 | (__STACK_SIZE + __bss_end__ - __bss_start__) <= LENGTH(DTCM), |
| 170 | "DTCM overflow") |
| 171 | |
| 172 | .ddr.at_ddr : |
| 173 | { |
| 174 | /* __attribute__((aligned(16))) is not handled by the CMSIS startup code. |
| 175 | * Force the alignment here as a workaround */ |
| 176 | . = ALIGN(16); |
Isabella Gottardi | 118f73e | 2021-09-16 17:54:35 +0100 | [diff] [blame] | 177 | /* nn model's baked in input matrices */ |
Kshitij Sisodia | f9c19ea | 2021-05-07 16:08:14 +0100 | [diff] [blame] | 178 | *(ifm) |
| 179 | . = ALIGN(16); |
Isabella Gottardi | 118f73e | 2021-09-16 17:54:35 +0100 | [diff] [blame] | 180 | /* nn model's default space */ |
Kshitij Sisodia | f9c19ea | 2021-05-07 16:08:14 +0100 | [diff] [blame] | 181 | *(nn_model) |
| 182 | . = ALIGN (16); |
Isabella Gottardi | 118f73e | 2021-09-16 17:54:35 +0100 | [diff] [blame] | 183 | /* labels */ |
Kshitij Sisodia | f9c19ea | 2021-05-07 16:08:14 +0100 | [diff] [blame] | 184 | *(labels) |
| 185 | . = ALIGN (16); |
Isabella Gottardi | 118f73e | 2021-09-16 17:54:35 +0100 | [diff] [blame] | 186 | /* activation buffers a.k.a tensor arena when memory mode dedicated sram */ |
| 187 | *(activation_buf_dram) |
Kshitij Sisodia | f9c19ea | 2021-05-07 16:08:14 +0100 | [diff] [blame] | 188 | . = ALIGN (16); |
| 189 | } > DDR AT > DDR |
| 190 | |
| 191 | /** |
| 192 | * Location counter can end up 2byte aligned with narrow Thumb code but |
| 193 | * __etext is assumed by startup code to be the LMA of a section in DTCM |
| 194 | * which must be 4byte aligned |
| 195 | */ |
| 196 | __etext = ALIGN (4); |
| 197 | |
| 198 | .bram.at_ddr : AT (__etext) |
| 199 | { |
| 200 | __data_start__ = .; |
| 201 | *(vtable) |
| 202 | *(.data) |
| 203 | *(.data.*) |
| 204 | . = ALIGN(4); |
| 205 | PROVIDE_HIDDEN (__preinit_array_start = .); |
| 206 | KEEP(*(.preinit_array)) |
| 207 | PROVIDE_HIDDEN (__preinit_array_end = .); |
| 208 | . = ALIGN(4); |
| 209 | PROVIDE_HIDDEN (__init_array_start = .); |
| 210 | KEEP(*(SORT(.init_array.*))) |
| 211 | KEEP(*(.init_array)) |
| 212 | PROVIDE_HIDDEN (__init_array_end = .); |
| 213 | . = ALIGN(4); |
| 214 | PROVIDE_HIDDEN (__fini_array_start = .); |
| 215 | KEEP(*(SORT(.fini_array.*))) |
| 216 | KEEP(*(.fini_array)) |
| 217 | PROVIDE_HIDDEN (__fini_array_end = .); |
| 218 | KEEP(*(.jcr*)) |
| 219 | . = ALIGN(4); |
| 220 | |
Éanna Ó Catháin | 8f95887 | 2021-09-15 09:32:30 +0100 | [diff] [blame] | 221 | *(.ARM.extab* .gnu.linkonce.armextab.*) |
| 222 | . = ALIGN(4); |
| 223 | |
| 224 | /** |
| 225 | * Place the all ops resolver code data here. This accounts |
| 226 | * for ~4k worth of saving on the ITCM load region. It is |
| 227 | * only designed to be included (by default) for the inference |
| 228 | * runner use case. |
| 229 | **/ |
| 230 | *all_ops_resolver.o (*.text*) |
| 231 | . = ALIGN(4); |
| 232 | *hal.c.obj (*.text*) |
| 233 | . = ALIGN(4); |
| 234 | |
Kshitij Sisodia | f9c19ea | 2021-05-07 16:08:14 +0100 | [diff] [blame] | 235 | __data_end__ = .; |
| 236 | } > BRAM |
| 237 | |
| 238 | __etext2 = __etext + (__data_end__ - __data_start__); |
| 239 | |
| 240 | .data.at_ddr : AT (__etext2) |
| 241 | { |
| 242 | . = ALIGN(4); |
| 243 | __ro_data_start__ = .; |
| 244 | |
| 245 | *(.rodata*) |
| 246 | . = ALIGN(4); |
| 247 | * (npu_driver_version) |
| 248 | . = ALIGN(4); |
| 249 | * (npu_driver_arch_version) |
| 250 | . = ALIGN(4); |
| 251 | |
| 252 | __ro_data_end__ = .; |
| 253 | } > BRAM |
| 254 | |
| 255 | .heap (COPY) : |
| 256 | { |
| 257 | . = ALIGN(8); |
| 258 | __end__ = .; |
| 259 | PROVIDE(end = .); |
| 260 | . = . + __HEAP_SIZE; |
| 261 | . = ALIGN(8); |
| 262 | __HeapLimit = .; |
| 263 | } > BRAM |
| 264 | |
| 265 | ASSERT ( |
| 266 | (__ro_data_end__ - __ro_data_start__) |
| 267 | + (__data_end__ - __data_start__) |
| 268 | + __HEAP_SIZE <= LENGTH(BRAM), |
| 269 | "BRAM overflow") |
| 270 | } |