alexander | 3c79893 | 2021-03-26 21:42:19 +0000 | [diff] [blame] | 1 | ; Copyright (c) 2021 Arm Limited. All rights reserved. |
| 2 | ; SPDX-License-Identifier: Apache-2.0 |
| 3 | ; |
| 4 | ; Licensed under the Apache License, Version 2.0 (the "License"); |
| 5 | ; you may not use this file except in compliance with the License. |
| 6 | ; You may obtain a copy of the License at |
| 7 | ; |
| 8 | ; http://www.apache.org/licenses/LICENSE-2.0 |
| 9 | ; |
| 10 | ; Unless required by applicable law or agreed to in writing, software |
| 11 | ; distributed under the License is distributed on an "AS IS" BASIS, |
| 12 | ; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 13 | ; See the License for the specific language governing permissions and |
| 14 | ; limitations under the License. |
| 15 | |
| 16 | ; ************************************************************* |
| 17 | ; *** Scatter-Loading Description File *** |
| 18 | ; ************************************************************* |
Kshitij Sisodia | 7e56d8f | 2022-04-11 10:34:29 +0100 | [diff] [blame] | 19 | ; Please see docs/sections/appendix.md for memory mapping |
| 20 | ; information. |
alexander | 3c79893 | 2021-03-26 21:42:19 +0000 | [diff] [blame] | 21 | ; |
Kshitij Sisodia | 7e56d8f | 2022-04-11 10:34:29 +0100 | [diff] [blame] | 22 | ; Note: Ethos-U NPU can access BRAM, internal SRAM and the DDR |
| 23 | ; sections => activation buffers and the model should |
| 24 | ; only be placed in those regions. |
alexander | 3c79893 | 2021-03-26 21:42:19 +0000 | [diff] [blame] | 25 | ; |
| 26 | ;--------------------------------------------------------- |
| 27 | ; First load region (ITCM) |
| 28 | ;--------------------------------------------------------- |
| 29 | LOAD_REGION_0 0x00000000 0x00080000 |
| 30 | { |
| 31 | ;----------------------------------------------------- |
| 32 | ; First part of code mem - 512kiB |
| 33 | ;----------------------------------------------------- |
| 34 | itcm.bin 0x00000000 0x00080000 |
| 35 | { |
| 36 | *.o (RESET, +First) |
| 37 | * (InRoot$$Sections) |
| 38 | |
| 39 | ; Essentially only RO-CODE, RO-DATA is in a |
| 40 | ; different region. |
| 41 | .ANY (+RO) |
| 42 | } |
| 43 | |
| 44 | ;----------------------------------------------------- |
Kshitij Sisodia | 7e56d8f | 2022-04-11 10:34:29 +0100 | [diff] [blame] | 45 | ; 384kiB of 512kiB DTCM is used for any other RW or ZI |
alexander | 3c79893 | 2021-03-26 21:42:19 +0000 | [diff] [blame] | 46 | ; data. Note: this region is internal to the Cortex-M |
| 47 | ; CPU. |
| 48 | ;----------------------------------------------------- |
Kshitij Sisodia | 7e56d8f | 2022-04-11 10:34:29 +0100 | [diff] [blame] | 49 | dtcm.bin 0x20000000 0x00060000 |
alexander | 3c79893 | 2021-03-26 21:42:19 +0000 | [diff] [blame] | 50 | { |
| 51 | ; Any R/W and/or zero initialised data |
| 52 | .ANY(+RW +ZI) |
| 53 | } |
| 54 | |
| 55 | ;----------------------------------------------------- |
Kshitij Sisodia | 7e56d8f | 2022-04-11 10:34:29 +0100 | [diff] [blame] | 56 | ; 32 kiB of stack space within the DTCM region. See |
alexander | 3c79893 | 2021-03-26 21:42:19 +0000 | [diff] [blame] | 57 | ; `dtcm.bin` for the first section. Note: by virtue of |
| 58 | ; being part of DTCM, this region is only accessible |
Kshitij Sisodia | 7e56d8f | 2022-04-11 10:34:29 +0100 | [diff] [blame] | 59 | ; from Cortex-M55. We use the last DTCM bank |
alexander | 3c79893 | 2021-03-26 21:42:19 +0000 | [diff] [blame] | 60 | ;----------------------------------------------------- |
Kshitij Sisodia | 7e56d8f | 2022-04-11 10:34:29 +0100 | [diff] [blame] | 61 | ARM_LIB_STACK 0x20060000 EMPTY ALIGN 8 0x00008000 |
alexander | 3c79893 | 2021-03-26 21:42:19 +0000 | [diff] [blame] | 62 | {} |
| 63 | |
| 64 | ;----------------------------------------------------- |
Kshitij Sisodia | 661959c | 2021-11-24 10:39:52 +0000 | [diff] [blame] | 65 | ; FPGA internal SRAM of 2MiB - reserved for activation |
| 66 | ; buffers. |
alexander | 3c79893 | 2021-03-26 21:42:19 +0000 | [diff] [blame] | 67 | ; This region should have 3 cycle read latency from |
Isabella Gottardi | f590773 | 2021-08-06 15:39:41 +0100 | [diff] [blame] | 68 | ; both Cortex-M55 and Ethos-U NPU |
alexander | 3c79893 | 2021-03-26 21:42:19 +0000 | [diff] [blame] | 69 | ;----------------------------------------------------- |
Kshitij Sisodia | 661959c | 2021-11-24 10:39:52 +0000 | [diff] [blame] | 70 | isram.bin 0x31000000 UNINIT ALIGN 16 0x00200000 |
alexander | 3c79893 | 2021-03-26 21:42:19 +0000 | [diff] [blame] | 71 | { |
Isabella Gottardi | 118f73e | 2021-09-16 17:54:35 +0100 | [diff] [blame] | 72 | ; Cache area (if used) |
| 73 | *.o (.bss.NoInit.ethos_u_cache) |
| 74 | |
Kshitij Sisodia | 661959c | 2021-11-24 10:39:52 +0000 | [diff] [blame] | 75 | ; activation buffers a.k.a tensor arena when |
| 76 | ; memory mode sram only or shared sram |
Isabella Gottardi | 118f73e | 2021-09-16 17:54:35 +0100 | [diff] [blame] | 77 | *.o (.bss.NoInit.activation_buf_sram) |
alexander | 3c79893 | 2021-03-26 21:42:19 +0000 | [diff] [blame] | 78 | } |
| 79 | } |
| 80 | |
| 81 | ;--------------------------------------------------------- |
| 82 | ; Second load region (DDR) |
| 83 | ;--------------------------------------------------------- |
| 84 | LOAD_REGION_1 0x70000000 0x02000000 |
| 85 | { |
| 86 | ;----------------------------------------------------- |
Kshitij Sisodia | f9c19ea | 2021-05-07 16:08:14 +0100 | [diff] [blame] | 87 | ; 32 MiB of DDR space for neural network model, |
alexander | 3c79893 | 2021-03-26 21:42:19 +0000 | [diff] [blame] | 88 | ; input vectors and labels. If the activation buffer |
| 89 | ; size required by the network is bigger than the |
| 90 | ; SRAM size available, it is accommodated here. |
| 91 | ;----------------------------------------------------- |
Kshitij Sisodia | f9c19ea | 2021-05-07 16:08:14 +0100 | [diff] [blame] | 92 | ddr.bin 0x70000000 ALIGN 16 0x02000000 |
alexander | 3c79893 | 2021-03-26 21:42:19 +0000 | [diff] [blame] | 93 | { |
| 94 | ; nn model's baked in input matrices |
| 95 | *.o (ifm) |
| 96 | |
Isabella Gottardi | 118f73e | 2021-09-16 17:54:35 +0100 | [diff] [blame] | 97 | ; nn model's default space |
alexander | 3c79893 | 2021-03-26 21:42:19 +0000 | [diff] [blame] | 98 | *.o (nn_model) |
| 99 | |
| 100 | ; labels |
| 101 | *.o (labels) |
| 102 | |
Isabella Gottardi | 118f73e | 2021-09-16 17:54:35 +0100 | [diff] [blame] | 103 | ; activation buffers a.k.a tensor arena when memory mode dedicated sram |
| 104 | *.o (activation_buf_dram) |
alexander | 3c79893 | 2021-03-26 21:42:19 +0000 | [diff] [blame] | 105 | } |
| 106 | |
| 107 | ;----------------------------------------------------- |
| 108 | ; First 256kiB of BRAM (FPGA SRAM) used for RO data. |
Kshitij Sisodia | 661959c | 2021-11-24 10:39:52 +0000 | [diff] [blame] | 109 | ; Note: Total BRAM size available is 1MiB. |
alexander | 3c79893 | 2021-03-26 21:42:19 +0000 | [diff] [blame] | 110 | ;----------------------------------------------------- |
| 111 | bram.bin 0x11000000 ALIGN 8 0x00040000 |
| 112 | { |
| 113 | ; RO data (incl. unwinding tables for debugging) |
| 114 | .ANY (+RO-DATA) |
| 115 | } |
| 116 | |
| 117 | ;----------------------------------------------------- |
Kshitij Sisodia | 661959c | 2021-11-24 10:39:52 +0000 | [diff] [blame] | 118 | ; 768 KiB of remaining part of the 1MiB BRAM used as |
| 119 | ; heap space. |
alexander | 3c79893 | 2021-03-26 21:42:19 +0000 | [diff] [blame] | 120 | ;----------------------------------------------------- |
Kshitij Sisodia | 661959c | 2021-11-24 10:39:52 +0000 | [diff] [blame] | 121 | ARM_LIB_HEAP 0x11040000 EMPTY ALIGN 8 0x000C0000 |
alexander | 3c79893 | 2021-03-26 21:42:19 +0000 | [diff] [blame] | 122 | {} |
Kshitij Sisodia | aa5e1f6 | 2021-09-24 14:42:08 +0100 | [diff] [blame] | 123 | |
| 124 | ;----------------------------------------------------- |
| 125 | ; The following regions are for use by the FVP to |
| 126 | ; allow loading or dumping of dynamic data into or |
| 127 | ; from the memory. These regions are mentioned in |
| 128 | ; the CMake subsystem profile. Do not change the |
| 129 | ; addresses and sizes below in isolation. |
| 130 | ;----------------------------------------------------- |
| 131 | ; 32 MiB of model space for run-time load of model |
| 132 | ;----------------------------------------------------- |
| 133 | runtime_model 0x90000000 EMPTY ALIGN 16 0x02000000 |
| 134 | {} |
| 135 | |
| 136 | ;----------------------------------------------------- |
| 137 | ; 16 MiB of IFM space for run-time loading (FVP only) |
| 138 | ;----------------------------------------------------- |
| 139 | runtime_ifm 0x92000000 EMPTY ALIGN 16 0x01000000 |
| 140 | {} |
| 141 | |
| 142 | ;----------------------------------------------------- |
| 143 | ; 16 MiB of OFM space for run-time loading (FVP only) |
| 144 | ;----------------------------------------------------- |
| 145 | runtime_ofm 0x93000000 EMPTY ALIGN 16 0x01000000 |
| 146 | {} |
alexander | 3c79893 | 2021-03-26 21:42:19 +0000 | [diff] [blame] | 147 | } |