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review.mlplatform.org / ml / ethos-u / ml-embedded-evaluation-kit / c22e80e25521bdd291fdef9ba20194ce9d2a8544 / . / source / hal / source / platform / mps3 / source / smm_mps3.h
blob: 8d5614a8092443578eafedbec93ab9036c623a39 [file] [log] [blame]
alexander3c798932021-03-26 21:42:19 +0000[diff] [blame]1/*
Kshitij Sisodiad5679cc2022-03-03 16:30:07 +0000[diff] [blame]2 * Copyright (c) 2022 Arm Limited. All rights reserved.
alexander3c798932021-03-26 21:42:19 +0000[diff] [blame]3 * SPDX-License-Identifier: Apache-2.0
4 *
5 * Licensed under the Apache License, Version 2.0 (the "License");
6 * you may not use this file except in compliance with the License.
7 * You may obtain a copy of the License at
8 *
9 * http://www.apache.org/licenses/LICENSE-2.0
10 *
11 * Unless required by applicable law or agreed to in writing, software
12 * distributed under the License is distributed on an "AS IS" BASIS,
13 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14 * See the License for the specific language governing permissions and
15 * limitations under the License.
16 */
17#ifndef SMM_MPS3_H
18#define SMM_MPS3_H
19
alexander3c798932021-03-26 21:42:19 +0000[diff] [blame]20#include "peripheral_memmap.h" /* Peripheral memory map definitions. */
21
Kshitij Sisodia6a2ac462022-03-01 17:36:06 +0000[diff] [blame]22#include "RTE_Components.h"
Kshitij Sisodiaa1256e32022-02-23 14:40:45 +0000[diff] [blame]23
alexander3c798932021-03-26 21:42:19 +0000[diff] [blame]24#if defined ( __CC_ARM )
25#pragma anon_unions
26#endif
27
28/******************************************************************************/
29/* FPGA System Register declaration */
30/******************************************************************************/
31
32typedef struct
33{
34 __IO uint32_t LED; /* Offset: 0x000 (R/W) LED connections
35 * [31:2] : Reserved
36 * [1:0] : LEDs
37 */
38 uint32_t RESERVED1[1];
39 __IO uint32_t BUTTON; /* Offset: 0x008 (R/W) Buttons
40 * [31:2] : Reserved
41 * [1:0] : Buttons
42 */
43 uint32_t RESERVED2[1];
44 __IO uint32_t CLK1HZ; /* Offset: 0x010 (R/W) 1Hz up counter */
45 __IO uint32_t CLK100HZ; /* Offset: 0x014 (R/W) 100Hz up counter */
46 __IO uint32_t COUNTER; /* Offset: 0x018 (R/W) Cycle Up Counter
47 * Increments when 32-bit prescale counter reach zero
48 */
49 __IO uint32_t PRESCALE; /* Offset: 0x01C (R/W) Prescaler
50 * Bit[31:0] : reload value for prescale counter
51 */
52 __IO uint32_t PSCNTR; /* Offset: 0x020 (R/W) 32-bit Prescale counter
53 * current value of the pre-scaler counter
54 * The Cycle Up Counter increment when the prescale down counter reach 0
55 * The pre-scaler counter is reloaded with PRESCALE after reaching 0.
56 */
57 uint32_t RESERVED3[1];
58 __IO uint32_t SWITCHES; /* Offset: 0x028 (R/W) Switches
59 * [31:8] : Reserved
60 * [7:0] : Switches
61 */
62 uint32_t RESERVED4[8];
63 __IO uint32_t MISC; /* Offset: 0x04C (R/W) Misc control
64 * [31:10] : Reserved
65 * [9] :
66 * [8] :
67 * [7] : ADC_SPI_nCS
68 * [6] : CLCD_BL_CTRL
69 * [5] : CLCD_RD
70 * [4] : CLCD_RS
71 * [3] : CLCD_RESET
72 * [2] : SHIELD_1_SPI_nCS
73 * [1] : SHIELD_0_SPI_nCS
74 * [0] : CLCD_CS
75 */
76} MPS3_FPGAIO_TypeDef;
77
78/* MISC register bit definitions. */
79
80#define CLCD_CS_Pos 0
81#define CLCD_CS_Msk (1UL<<CLCD_CS_Pos)
82#define SHIELD_0_nCS_Pos 1
83#define SHIELD_0_nCS_Msk (1UL<<SHIELD_0_nCS_Pos)
84#define SHIELD_1_nCS_Pos 2
85#define SHIELD_1_nCS_Msk (1UL<<SHIELD_1_nCS_Pos)
86#define CLCD_RESET_Pos 3
87#define CLCD_RESET_Msk (1UL<<CLCD_RESET_Pos)
88#define CLCD_RS_Pos 4
89#define CLCD_RS_Msk (1UL<<CLCD_RS_Pos)
90#define CLCD_RD_Pos 5
91#define CLCD_RD_Msk (1UL<<CLCD_RD_Pos)
92#define CLCD_BL_Pos 6
93#define CLCD_BL_Msk (1UL<<CLCD_BL_Pos)
94#define ADC_nCS_Pos 7
95#define ADC_nCS_Msk (1UL<<ADC_nCS_Pos)
96
97/******************************************************************************/
98/* SCC Register declaration */
99/******************************************************************************/
100
101typedef struct
102{
103 __IO uint32_t CFG_REG0; /* Offset: 0x000 (R/W) Remaps block RAM to ZBT
104 * [31:1] : Reserved
105 * [0] 1 : REMAP BlockRam to ZBT
106 */
107 __IO uint32_t LEDS; /* Offset: 0x004 (R/W) Controls the MCC user LEDs
108 * [31:8] : Reserved
109 * [7:0] : MCC LEDs
110 */
111 uint32_t RESERVED0[1];
112 __I uint32_t SWITCHES; /* Offset: 0x00C (R/ ) Denotes the state of the MCC user switches
113 * [31:8] : Reserved
114 * [7:0] : These bits indicate state of the MCC switches
115 */
116 __I uint32_t CFG_REG4; /* Offset: 0x010 (R/ ) Denotes the board revision
117 * [31:4] : Reserved
118 * [3:0] : Used by the MCC to pass PCB revision. 0 = A 1 = B
119 */
120 __I uint32_t CFG_ACLK; /* Offset: 0x014 (R/ ) System Clock
121 */
122 uint32_t RESERVED1[34];
123 __IO uint32_t SYS_CFGDATA_RTN; /* Offset: 0x0A0 (R/W) User data register
124 * [31:0] : Data
125 */
126 __IO uint32_t SYS_CFGDATA_OUT; /* Offset: 0x0A4 (R/W) User data register
127 * [31:0] : Data
128 */
129 __IO uint32_t SYS_CFGCTRL; /* Offset: 0x0A8 (R/W) Control register
130 * [31] : Start (generates interrupt on write to this bit)
131 * [30] : R/W access
132 * [29:26] : Reserved
133 * [25:20] : Function value
134 * [19:12] : Reserved
135 * [11:0] : Device (value of 0/1/2 for supported clocks)
136 */
137 __IO uint32_t SYS_CFGSTAT; /* Offset: 0x0AC (R/W) Contains status information
138 * [31:2] : Reserved
139 * [1] : Error
140 * [0] : Complete
141 */
142 __IO uint32_t RESERVED2[20];
143 __IO uint32_t SCC_DLL; /* Offset: 0x100 (R/W) DLL Lock Register
144 * [31:24] : DLL LOCK MASK[7:0] - Indicate if the DLL locked is masked
145 * [23:16] : DLL LOCK MASK[7:0] - Indicate if the DLLs are locked or unlocked
146 * [15:1] : Reserved
147 * [0] : This bit indicates if all enabled DLLs are locked
148 */
149 uint32_t RESERVED3[957];
150 __I uint32_t SCC_AID; /* Offset: 0xFF8 (R/ ) SCC AID Register
151 * [31:24] : FPGA build number
152 * [23:20] : V2M-MPS3 target board revision (A = 0, B = 1)
153 * [19:11] : Reserved
154 * [10] : if “1” SCC_SW register has been implemented
155 * [9] : if “1” SCC_LED register has been implemented
156 * [8] : if “1” DLL lock register has been implemented
157 * [7:0] : number of SCC configuration register
158 */
159 __I uint32_t SCC_ID; /* Offset: 0xFFC (R/ ) Contains information about the FPGA image
160 * [31:24] : Implementer ID: 0x41 = ARM
161 * [23:20] : Application note IP variant number
162 * [19:16] : IP Architecture: 0x4 =AHB
163 * [15:4] : Primary part number: 386 = AN386
164 * [3:0] : Application note IP revision number
165 */
166} MPS3_SCC_TypeDef;
167
168
169/******************************************************************************/
170/* SSP Peripheral declaration */
171/******************************************************************************/
172
173typedef struct
174{
175 __IO uint32_t CR0; /* Offset: 0x000 (R/W) Control register 0
176 * [31:16] : Reserved
177 * [15:8] : Serial clock rate
178 * [7] : SSPCLKOUT phase, applicable to Motorola SPI frame format only
179 * [6] : SSPCLKOUT polarity, applicable to Motorola SPI frame format only
180 * [5:4] : Frame format
181 * [3:0] : Data Size Select
182 */
183 __IO uint32_t CR1; /* Offset: 0x004 (R/W) Control register 1
184 * [31:4] : Reserved
185 * [3] : Slave-mode output disable
186 * [2] : Master or slave mode select
187 * [1] : Synchronous serial port enable
188 * [0] : Loop back mode
189 */
190 __IO uint32_t DR; /* Offset: 0x008 (R/W) Data register
191 * [31:16] : Reserved
192 * [15:0] : Transmit/Receive FIFO
193 */
194 __I uint32_t SR; /* Offset: 0x00C (R/ ) Status register
195 * [31:5] : Reserved
196 * [4] : PrimeCell SSP busy flag
197 * [3] : Receive FIFO full
198 * [2] : Receive FIFO not empty
199 * [1] : Transmit FIFO not full
200 * [0] : Transmit FIFO empty
201 */
202 __IO uint32_t CPSR; /* Offset: 0x010 (R/W) Clock prescale register
203 * [31:8] : Reserved
204 * [8:0] : Clock prescale divisor
205 */
206 __IO uint32_t IMSC; /* Offset: 0x014 (R/W) Interrupt mask set or clear register
207 * [31:4] : Reserved
208 * [3] : Transmit FIFO interrupt mask
209 * [2] : Receive FIFO interrupt mask
210 * [1] : Receive timeout interrupt mask
211 * [0] : Receive overrun interrupt mask
212 */
213 __I uint32_t RIS; /* Offset: 0x018 (R/ ) Raw interrupt status register
214 * [31:4] : Reserved
215 * [3] : raw interrupt state, prior to masking, of the SSPTXINTR interrupt
216 * [2] : raw interrupt state, prior to masking, of the SSPRXINTR interrupt
217 * [1] : raw interrupt state, prior to masking, of the SSPRTINTR interrupt
218 * [0] : raw interrupt state, prior to masking, of the SSPRORINTR interrupt
219 */
220 __I uint32_t MIS; /* Offset: 0x01C (R/ ) Masked interrupt status register
221 * [31:4] : Reserved
222 * [3] : transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt
223 * [2] : receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt
224 * [1] : receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt
225 * [0] : receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt
226 */
227 __O uint32_t ICR; /* Offset: 0x020 ( /W) Interrupt clear register
228 * [31:2] : Reserved
229 * [1] : Clears the SSPRTINTR interrupt
230 * [0] : Clears the SSPRORINTR interrupt
231 */
232 __IO uint32_t DMACR; /* Offset: 0x024 (R/W) DMA control register
233 * [31:2] : Reserved
234 * [1] : Transmit DMA Enable
235 * [0] : Receive DMA Enable
236 */
237} MPS3_SSP_TypeDef;
238
239
240/* SSP_CR0 Control register 0. */
241#define SSP_CR0_DSS_Pos 0 /* Data Size Select. */
242#define SSP_CR0_DSS_Msk (0xF<<SSP_CR0_DSS_Pos)
243#define SSP_CR0_FRF_Pos 4 /* Frame Format Select. */
244#define SSP_CR0_FRF_Msk (3UL<<SSP_CR0_FRM_Pos)
245#define SSP_CR0_SPO_Pos 6 /* SSPCLKOUT polarity. */
246#define SSP_CR0_SPO_Msk (1UL<<SSP_CR0_SPO_Pos)
247#define SSP_CR0_SPH_Pos 7 /* SSPCLKOUT phase. */
248#define SSP_CR0_SPH_Msk (1UL<<SSP_CR0_SPH_Pos)
249#define SSP_CR0_SCR_Pos 8 /* Serial Clock Rate (divide). */
250#define SSP_CR0_SCR_Msk (0xFF<<SSP_CR0_SCR_Pos)
251
252#define SSP_CR0_SCR_DFLT 0x0300 /* Serial Clock Rate (divide), default set at 3. */
253#define SSP_CR0_FRF_MOT 0x0000 /* Frame format. */
254#define SSP_CR0_DSS_8 0x0007 /* Data packet size, 8bits. */
255#define SSP_CR0_DSS_16 0x000F /* Data packet size, 16bits. */
256
257/* SSP_CR1 Control register 1. */
258#define SSP_CR1_LBM_Pos 0 /* Loop Back Mode. */
259#define SSP_CR1_LBM_Msk (1UL<<SSP_CR1_LBM_Pos)
260#define SSP_CR1_SSE_Pos 1 /* Serial port enable. */
261#define SSP_CR1_SSE_Msk (1UL<<SSP_CR1_SSE_Pos)
262#define SSP_CR1_MS_Pos 2 /* Master or Slave mode. */
263#define SSP_CR1_MS_Msk (1UL<<SSP_CR1_MS_Pos)
264#define SSP_CR1_SOD_Pos 3 /* Slave Output mode Disable. */
265#define SSP_CR1_SOD_Msk (1UL<<SSP_CR1_SOD_Pos)
266
267/* SSP_SR Status register. */
268#define SSP_SR_TFE_Pos 0 /* Transmit FIFO empty. */
269#define SSP_SR_TFE_Msk (1UL<<SSP_SR_TFE_Pos)
270#define SSP_SR_TNF_Pos 1 /* Transmit FIFO not full. */
271#define SSP_SR_TNF_Msk (1UL<<SSP_SR_TNF_Pos)
272#define SSP_SR_RNE_Pos 2 /* Receive FIFO not empty. */
273#define SSP_SR_RNE_Msk (1UL<<SSP_SR_RNE_Pos)
274#define SSP_SR_RFF_Pos 3 /* Receive FIFO full. */
275#define SSP_SR_RFF_Msk (1UL<<SSP_SR_RFF_Pos)
276#define SSP_SR_BSY_Pos 4 /* Busy. */
277#define SSP_SR_BSY_Msk (1UL<<SSP_SR_BSY_Pos)
278
279/* SSP_CPSR Clock prescale register. */
280#define SSP_CPSR_CPD_Pos 0 /* Clock prescale divisor. */
281#define SSP_CPSR_CPD_Msk (0xFF<<SSP_CPSR_CDP_Pos)
282
283#define SSP_CPSR_DFLT 0x0008 /* Clock prescale (use with SCR), default set at 8. */
284
285/* SSPIMSC Interrupt mask set and clear register. */
286#define SSP_IMSC_RORIM_Pos 0 /* Receive overrun not Masked. */
287#define SSP_IMSC_RORIM_Msk (1UL<<SSP_IMSC_RORIM_Pos)
288#define SSP_IMSC_RTIM_Pos 1 /* Receive timeout not Masked. */
289#define SSP_IMSC_RTIM_Msk (1UL<<SSP_IMSC_RTIM_Pos)
290#define SSP_IMSC_RXIM_Pos 2 /* Receive FIFO not Masked. */
291#define SSP_IMSC_RXIM_Msk (1UL<<SSP_IMSC_RXIM_Pos)
292#define SSP_IMSC_TXIM_Pos 3 /* Transmit FIFO not Masked. */
293#define SSP_IMSC_TXIM_Msk (1UL<<SSP_IMSC_TXIM_Pos)
294
295/* SSPRIS Raw interrupt status register. */
296#define SSP_RIS_RORRIS_Pos 0 /* Raw Overrun interrupt flag. */
297#define SSP_RIS_RORRIS_Msk (1UL<<SSP_RIS_RORRIS_Pos)
298#define SSP_RIS_RTRIS_Pos 1 /* Raw Timemout interrupt flag. */
299#define SSP_RIS_RTRIS_Msk (1UL<<SSP_RIS_RTRIS_Pos)
300#define SSP_RIS_RXRIS_Pos 2 /* Raw Receive interrupt flag. */
301#define SSP_RIS_RXRIS_Msk (1UL<<SSP_RIS_RXRIS_Pos)
302#define SSP_RIS_TXRIS_Pos 3 /* Raw Transmit interrupt flag. */
303#define SSP_RIS_TXRIS_Msk (1UL<<SSP_RIS_TXRIS_Pos)
304
305/* SSPMIS Masked interrupt status register. */
306#define SSP_MIS_RORMIS_Pos 0 /* Masked Overrun interrupt flag. */
307#define SSP_MIS_RORMIS_Msk (1UL<<SSP_MIS_RORMIS_Pos)
308#define SSP_MIS_RTMIS_Pos 1 /* Masked Timemout interrupt flag. */
309#define SSP_MIS_RTMIS_Msk (1UL<<SSP_MIS_RTMIS_Pos)
310#define SSP_MIS_RXMIS_Pos 2 /* Masked Receive interrupt flag. */
311#define SSP_MIS_RXMIS_Msk (1UL<<SSP_MIS_RXMIS_Pos)
312#define SSP_MIS_TXMIS_Pos 3 /* Masked Transmit interrupt flag. */
313#define SSP_MIS_TXMIS_Msk (1UL<<SSP_MIS_TXMIS_Pos)
314
315/* SSPICR Interrupt clear register. */
316#define SSP_ICR_RORIC_Pos 0 /* Clears Overrun interrupt flag. */
317#define SSP_ICR_RORIC_Msk (1UL<<SSP_ICR_RORIC_Pos)
318#define SSP_ICR_RTIC_Pos 1 /* Clears Timemout interrupt flag. */
319#define SSP_ICR_RTIC_Msk (1UL<<SSP_ICR_RTIC_Pos)
320
321/* SSPDMACR DMA control register. */
322#define SSP_DMACR_RXDMAE_Pos 0 /* Enable Receive FIFO DMA. */
323#define SSP_DMACR_RXDMAE_Msk (1UL<<SSP_DMACR_RXDMAE_Pos)
324#define SSP_DMACR_TXDMAE_Pos 1 /* Enable Transmit FIFO DMA. */
325#define SSP_DMACR_TXDMAE_Msk (1UL<<SSP_DMACR_TXDMAE_Pos)
326
327/******************************************************************************/
328/* Audio and Touch Screen (I2C) Peripheral declaration */
329/******************************************************************************/
330
331typedef struct
332{
333 union {
334 __O uint32_t CONTROLS; /* Offset: 0x000 CONTROL Set Register ( /W). */
335 __I uint32_t CONTROL; /* Offset: 0x000 CONTROL Status Register (R/ ). */
336 };
337 __O uint32_t CONTROLC; /* Offset: 0x004 CONTROL Clear Register ( /W). */
338} MPS3_I2C_TypeDef;
339
340#define SDA 1 << 1
341#define SCL 1 << 0
342
343
344/******************************************************************************/
345/* Audio I2S Peripheral declaration */
346/******************************************************************************/
347
348typedef struct
349{
350 /*!< Offset: 0x000 CONTROL Register (R/W) */
351 __IO uint32_t CONTROL; /* <h> CONTROL </h>
352 * <o.0> TX Enable
353 * <0=> TX disabled
354 * <1=> TX enabled
355 * <o.1> TX IRQ Enable
356 * <0=> TX IRQ disabled
357 * <1=> TX IRQ enabled
358 * <o.2> RX Enable
359 * <0=> RX disabled
360 * <1=> RX enabled
361 * <o.3> RX IRQ Enable
362 * <0=> RX IRQ disabled
363 * <1=> RX IRQ enabled
364 * <o.10..8> TX Buffer Water Level
365 * <0=> / IRQ triggers when any space available
366 * <1=> / IRQ triggers when more than 1 space available
367 * <2=> / IRQ triggers when more than 2 space available
368 * <3=> / IRQ triggers when more than 3 space available
369 * <4=> Undefined!
370 * <5=> Undefined!
371 * <6=> Undefined!
372 * <7=> Undefined!
373 * <o.14..12> RX Buffer Water Level
374 * <0=> Undefined!
375 * <1=> / IRQ triggers when less than 1 space available
376 * <2=> / IRQ triggers when less than 2 space available
377 * <3=> / IRQ triggers when less than 3 space available
378 * <4=> / IRQ triggers when less than 4 space available
379 * <5=> Undefined!
380 * <6=> Undefined!
381 * <7=> Undefined!
382 * <o.16> FIFO reset
383 * <0=> Normal operation
384 * <1=> FIFO reset
385 * <o.17> Audio Codec reset
386 * <0=> Normal operation
387 * <1=> Assert audio Codec reset
388 */
389 /*!< Offset: 0x004 STATUS Register (R/ ) */
390 __I uint32_t STATUS; /* <h> STATUS </h>
391 * <o.0> TX Buffer alert
392 * <0=> TX buffer don't need service yet
393 * <1=> TX buffer need service
394 * <o.1> RX Buffer alert
395 * <0=> RX buffer don't need service yet
396 * <1=> RX buffer need service
397 * <o.2> TX Buffer Empty
398 * <0=> TX buffer have data
399 * <1=> TX buffer empty
400 * <o.3> TX Buffer Full
401 * <0=> TX buffer not full
402 * <1=> TX buffer full
403 * <o.4> RX Buffer Empty
404 * <0=> RX buffer have data
405 * <1=> RX buffer empty
406 * <o.5> RX Buffer Full
407 * <0=> RX buffer not full
408 * <1=> RX buffer full
409 */
410 union {
411 /*!< Offset: 0x008 Error Status Register (R/ ) */
412 __I uint32_t ERROR; /* <h> ERROR </h>
413 * <o.0> TX error
414 * <0=> Okay
415 * <1=> TX overrun/underrun
416 * <o.1> RX error
417 * <0=> Okay
418 * <1=> RX overrun/underrun
419 */
420 /*!< Offset: 0x008 Error Clear Register ( /W) */
421 __O uint32_t ERRORCLR; /* <h> ERRORCLR </h>
422 * <o.0> TX error
423 * <0=> Okay
424 * <1=> Clear TX error
425 * <o.1> RX error
426 * <0=> Okay
427 * <1=> Clear RX error
428 */
429 };
430 /*!< Offset: 0x00C Divide ratio Register (R/W) */
431 __IO uint32_t DIVIDE; /* <h> Divide ratio for Left/Right clock </h>
432 * <o.9..0> TX error (default 0x80)
433 */
434 /*!< Offset: 0x010 Transmit Buffer ( /W) */
435 __O uint32_t TXBUF; /* <h> Transmit buffer </h>
436 * <o.15..0> Right channel
437 * <o.31..16> Left channel
438 */
439
440 /*!< Offset: 0x014 Receive Buffer (R/ ) */
441 __I uint32_t RXBUF; /* <h> Receive buffer </h>
442 * <o.15..0> Right channel
443 * <o.31..16> Left channel
444 */
445 uint32_t RESERVED1[186];
446 __IO uint32_t ITCR; /* <h> Integration Test Control Register </h>
447 * <o.0> ITEN
448 * <0=> Normal operation
449 * <1=> Integration Test mode enable
450 */
451 __O uint32_t ITIP1; /* <h> Integration Test Input Register 1</h>
452 * <o.0> SDIN
453 */
454 __O uint32_t ITOP1; /* <h> Integration Test Output Register 1</h>
455 * <o.0> SDOUT
456 * <o.1> SCLK
457 * <o.2> LRCK
458 * <o.3> IRQOUT
459 */
460} MPS3_I2S_TypeDef;
461
462#define I2S_CONTROL_TXEN_Pos 0
463#define I2S_CONTROL_TXEN_Msk (1UL<<I2S_CONTROL_TXEN_Pos)
464
465#define I2S_CONTROL_TXIRQEN_Pos 1
466#define I2S_CONTROL_TXIRQEN_Msk (1UL<<I2S_CONTROL_TXIRQEN_Pos)
467
468#define I2S_CONTROL_RXEN_Pos 2
469#define I2S_CONTROL_RXEN_Msk (1UL<<I2S_CONTROL_RXEN_Pos)
470
471#define I2S_CONTROL_RXIRQEN_Pos 3
472#define I2S_CONTROL_RXIRQEN_Msk (1UL<<I2S_CONTROL_RXIRQEN_Pos)
473
474#define I2S_CONTROL_TXWLVL_Pos 8
475#define I2S_CONTROL_TXWLVL_Msk (7UL<<I2S_CONTROL_TXWLVL_Pos)
476
477#define I2S_CONTROL_RXWLVL_Pos 12
478#define I2S_CONTROL_RXWLVL_Msk (7UL<<I2S_CONTROL_RXWLVL_Pos)
479/* FIFO reset. */
480#define I2S_CONTROL_FIFORST_Pos 16
481#define I2S_CONTROL_FIFORST_Msk (1UL<<I2S_CONTROL_FIFORST_Pos)
482/* Codec reset. */
483#define I2S_CONTROL_CODECRST_Pos 17
484#define I2S_CONTROL_CODECRST_Msk (1UL<<I2S_CONTROL_CODECRST_Pos)
485
486#define I2S_STATUS_TXIRQ_Pos 0
487#define I2S_STATUS_TXIRQ_Msk (1UL<<I2S_STATUS_TXIRQ_Pos)
488
489#define I2S_STATUS_RXIRQ_Pos 1
490#define I2S_STATUS_RXIRQ_Msk (1UL<<I2S_STATUS_RXIRQ_Pos)
491
492#define I2S_STATUS_TXEmpty_Pos 2
493#define I2S_STATUS_TXEmpty_Msk (1UL<<I2S_STATUS_TXEmpty_Pos)
494
495#define I2S_STATUS_TXFull_Pos 3
496#define I2S_STATUS_TXFull_Msk (1UL<<I2S_STATUS_TXFull_Pos)
497
498#define I2S_STATUS_RXEmpty_Pos 4
499#define I2S_STATUS_RXEmpty_Msk (1UL<<I2S_STATUS_RXEmpty_Pos)
500
501#define I2S_STATUS_RXFull_Pos 5
502#define I2S_STATUS_RXFull_Msk (1UL<<I2S_STATUS_RXFull_Pos)
503
504#define I2S_ERROR_TXERR_Pos 0
505#define I2S_ERROR_TXERR_Msk (1UL<<I2S_ERROR_TXERR_Pos)
506
507#define I2S_ERROR_RXERR_Pos 1
508#define I2S_ERROR_RXERR_Msk (1UL<<I2S_ERROR_RXERR_Pos)
509
510/******************************************************************************/
511/* SMSC9220 Register Definitions */
512/******************************************************************************/
513
514typedef struct /* SMSC LAN9220 */
515{
516__I uint32_t RX_DATA_PORT; /* Receive FIFO Ports (offset 0x0). */
517 uint32_t RESERVED1[0x7];
518__O uint32_t TX_DATA_PORT; /* Transmit FIFO Ports (offset 0x20). */
519 uint32_t RESERVED2[0x7];
520
521__I uint32_t RX_STAT_PORT; /* Receive FIFO status port (offset 0x40). */
522__I uint32_t RX_STAT_PEEK; /* Receive FIFO status peek (offset 0x44). */
523__I uint32_t TX_STAT_PORT; /* Transmit FIFO status port (offset 0x48). */
524__I uint32_t TX_STAT_PEEK; /* Transmit FIFO status peek (offset 0x4C). */
525
526__I uint32_t ID_REV; /* Chip ID and Revision (offset 0x50). */
527__IO uint32_t IRQ_CFG; /* Main Interrupt Configuration (offset 0x54). */
528__IO uint32_t INT_STS; /* Interrupt Status (offset 0x58). */
529__IO uint32_t INT_EN; /* Interrupt Enable Register (offset 0x5C). */
530 uint32_t RESERVED3; /* Reserved for future use (offset 0x60). */
531__I uint32_t BYTE_TEST; /* Read-only byte order testing register 87654321h (offset 0x64). */
532__IO uint32_t FIFO_INT; /* FIFO Level Interrupts (offset 0x68). */
533__IO uint32_t RX_CFG; /* Receive Configuration (offset 0x6C). */
534__IO uint32_t TX_CFG; /* Transmit Configuration (offset 0x70). */
535__IO uint32_t HW_CFG; /* Hardware Configuration (offset 0x74). */
536__IO uint32_t RX_DP_CTL; /* RX Datapath Control (offset 0x78). */
537__I uint32_t RX_FIFO_INF; /* Receive FIFO Information (offset 0x7C). */
538__I uint32_t TX_FIFO_INF; /* Transmit FIFO Information (offset 0x80). */
539__IO uint32_t PMT_CTRL; /* Power Management Control (offset 0x84). */
540__IO uint32_t GPIO_CFG; /* General Purpose IO Configuration (offset 0x88). */
541__IO uint32_t GPT_CFG; /* General Purpose Timer Configuration (offset 0x8C). */
542__I uint32_t GPT_CNT; /* General Purpose Timer Count (offset 0x90). */
543 uint32_t RESERVED4; /* Reserved for future use (offset 0x94). */
544__IO uint32_t ENDIAN; /* WORD SWAP Register (offset 0x98). */
545__I uint32_t FREE_RUN; /* Free Run Counter (offset 0x9C). */
546__I uint32_t RX_DROP; /* RX Dropped Frames Counter (offset 0xA0). */
547__IO uint32_t MAC_CSR_CMD; /* MAC CSR Synchronizer Command (offset 0xA4). */
548__IO uint32_t MAC_CSR_DATA; /* MAC CSR Synchronizer Data (offset 0xA8). */
549__IO uint32_t AFC_CFG; /* Automatic Flow Control Configuration (offset 0xAC). */
550__IO uint32_t E2P_CMD; /* EEPROM Command (offset 0xB0). */
551__IO uint32_t E2P_DATA; /* EEPROM Data (offset 0xB4). */
552
553} SMSC9220_TypeDef;
554
555/* SMSC9220 MAC Registers Indices. */
556#define SMSC9220_MAC_CR 0x1
557#define SMSC9220_MAC_ADDRH 0x2
558#define SMSC9220_MAC_ADDRL 0x3
559#define SMSC9220_MAC_HASHH 0x4
560#define SMSC9220_MAC_HASHL 0x5
561#define SMSC9220_MAC_MII_ACC 0x6
562#define SMSC9220_MAC_MII_DATA 0x7
563#define SMSC9220_MAC_FLOW 0x8
564#define SMSC9220_MAC_VLAN1 0x9
565#define SMSC9220_MAC_VLAN2 0xA
566#define SMSC9220_MAC_WUFF 0xB
567#define SMSC9220_MAC_WUCSR 0xC
568
569/* SMSC9220 PHY Registers Indices. */
570#define SMSC9220_PHY_BCONTROL 0x0
571#define SMSC9220_PHY_BSTATUS 0x1
572#define SMSC9220_PHY_ID1 0x2
573#define SMSC9220_PHY_ID2 0x3
574#define SMSC9220_PHY_ANEG_ADV 0x4
575#define SMSC9220_PHY_ANEG_LPA 0x5
576#define SMSC9220_PHY_ANEG_EXP 0x6
577#define SMSC9220_PHY_MCONTROL 0x17
578#define SMSC9220_PHY_MSTATUS 0x18
579#define SMSC9220_PHY_CSINDICATE 0x27
580#define SMSC9220_PHY_INTSRC 0x29
581#define SMSC9220_PHY_INTMASK 0x30
582#define SMSC9220_PHY_CS 0x31
583
584/******************************************************************************/
585/* Peripheral declaration */
586/******************************************************************************/
587
588#define MPS3_TS_I2C ((MPS3_I2C_TypeDef *) MPS3_I2C0_BASE )
589#define MPS3_AAIC_I2C ((MPS3_I2C_TypeDef *) MPS3_I2C1_BASE )
590#define MPS3_CAM_I2C2 ((MPS3_I2C_TypeDef *) MPS3_I2C2_BASE )
591#define MPS3_CAM_I2C3 ((MPS3_I2C_TypeDef *) MPS3_I2C3_BASE )
592#define MPS3_AAIC_I2S ((MPS3_I2S_TypeDef *) MPS3_AAIC_I2S_BASE )
593#define MPS3_FPGAIO ((MPS3_FPGAIO_TypeDef *) MPS3_FPGAIO_BASE )
594#define MPS3_SCC ((MPS3_SCC_TypeDef *) MPS3_SCC_BASE )
595#define MPS3_SSP0 ((MPS3_SSP_TypeDef *) MPS3_SSP0_BASE )
596#define MPS3_SSP1 ((MPS3_SSP_TypeDef *) MPS3_SSP1_BASE )
597#define MPS3_SSP2 ((MPS3_SSP_TypeDef *) MPS3_SSP2_BASE )
598#define MPS3_SSP3 ((MPS3_SSP_TypeDef *) MPS3_SSP3_BASE )
599#define MPS3_SSP4 ((MPS3_SSP_TypeDef *) MPS3_SSP4_BASE )
600#define SMSC9220 ((SMSC9220_TypeDef *) SMSC9220_BASE)
601
602/******************************************************************************/
603/* Secure Peripheral declaration */
604/******************************************************************************/
605
606#define SEC_TS_I2C ((MPS3_I2C_TypeDef *) SEC_MPS3_I2C0_BASE )
607#define SEC_AAIC_I2C ((MPS3_I2C_TypeDef *) SEC_MPS3_I2C1_BASE )
608#define SEC_AAIC_I2S ((MPS3_I2S_TypeDef *) SEC_MPS3_AAIC_I2S_BASE )
609#define SEC_FPGAIO ((MPS3_FPGAIO_TypeDef *) SEC_MPS3_FPGAIO_BASE )
610#define SEC_SCC ((MPS3_SCC_TypeDef *) SEC_MPS3_SCC_BASE )
611#define SEC_SSP0 ((MPS3_SSP_TypeDef *) SEC_SSP0_BASE )
612#define SEC_SSP1 ((MPS3_SSP_TypeDef *) SEC_SSP1_BASE )
613#define SEC_SSP2 ((MPS3_SSP_TypeDef *) SEC_MPS3_SSP2_BASE )
614#define SEC_SMSC9220 ((SMSC9220_TypeDef *) SEC_SMSC9220_BASE)
615
616#endif /* SMM_MPS3_H */