Blame - source/hal/platform/mps3/cmake/subsystem-profiles/sse-300.cmake - ml/ethos-u/ml-embedded-evaluation-kit

2021-03-26 21:42:19 +0000

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#----------------------------------------------------------------------------

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# SPDX-License-Identifier: Apache-2.0

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#

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# Licensed under the Apache License, Version 2.0 (the "License");

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# you may not use this file except in compliance with the License.

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# You may obtain a copy of the License at

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#

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# http://www.apache.org/licenses/LICENSE-2.0

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#

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# Unless required by applicable law or agreed to in writing, software

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# distributed under the License is distributed on an "AS IS" BASIS,

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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.

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# See the License for the specific language governing permissions and

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# limitations under the License.

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#----------------------------------------------------------------------------

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# CMake configuration file for peripheral memory map for MPS3 as per SSE-300 design

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###################################################################################################

alexander

2021-03-26 21:42:19 +0000

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# Mem sizes #

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###################################################################################################

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set(ITCM_SIZE "0x00080000" CACHE STRING "ITCM size: 512 kiB")

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set(DTCM_BLK_SIZE "0x00020000" CACHE STRING "DTCM size: 128 kiB, 4 banks")

Kshitij Sisodia

2021-11-24 10:39:52 +0000

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set(BRAM_SIZE "0x00100000" CACHE STRING "BRAM size: 1 MiB")

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set(ISRAM0_SIZE "0x00100000" CACHE STRING "ISRAM0 size: 1 MiB")

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set(ISRAM1_SIZE "0x00100000" CACHE STRING "ISRAM1 size: 1 MiB")

alexander

2021-03-26 21:42:19 +0000

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set(QSPI_SRAM_SIZE "0x00800000" CACHE STRING "QSPI Flash size: 8 MiB")

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set(DDR4_BLK_SIZE "0x10000000" CACHE STRING "DDR4 block size: 256 MiB")

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###################################################################################################

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# Base addresses for memory regions #

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###################################################################################################

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set(ITCM_BASE_NS "0x00000000" CACHE STRING "Instruction TCM Non-Secure base address")

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set(BRAM_BASE_NS "0x01000000" CACHE STRING "CODE SRAM Non-Secure base address")

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set(DTCM0_BASE_NS "0x20000000" CACHE STRING "Data TCM block 0 Non-Secure base address")

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set(DTCM1_BASE_NS "0x20020000" CACHE STRING "Data TCM block 1 Non-Secure base address")

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set(DTCM2_BASE_NS "0x20040000" CACHE STRING "Data TCM block 2 Non-Secure base address")

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set(DTCM3_BASE_NS "0x20060000" CACHE STRING "Data TCM block 3 Non-Secure base address")

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set(ISRAM0_BASE_NS "0x21000000" CACHE STRING "Internal SRAM Area Non-Secure base address")

Kshitij Sisodia

2021-11-24 10:39:52 +0000

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set(ISRAM1_BASE_NS "0x21100000" CACHE STRING "Internal SRAM Area Non-Secure base address")

alexander

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set(QSPI_SRAM_BASE_NS "0x28000000" CACHE STRING "QSPI SRAM Non-Secure base address")

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set(DDR4_BLK0_BASE_NS "0x60000000" CACHE STRING "DDR4 block 0 Non-Secure base address")

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set(DDR4_BLK1_BASE_NS "0x80000000" CACHE STRING "DDR4 block 1 Non-Secure base address")

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set(DDR4_BLK2_BASE_NS "0xA0000000" CACHE STRING "DDR4 block 2 Non-Secure base address")

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set(DDR4_BLK3_BASE_NS "0xC0000000" CACHE STRING "DDR4 block 3 Non-Secure base address")

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set(ITCM_BASE_S "0x10000000" CACHE STRING "Instruction TCM Secure base address")

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set(BRAM_BASE_S "0x11000000" CACHE STRING "CODE SRAM Secure base address")

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set(DTCM0_BASE_S "0x30000000" CACHE STRING "Data TCM block 0 Secure base address")

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set(DTCM1_BASE_S "0x30020000" CACHE STRING "Data TCM block 1 Secure base address")

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set(DTCM2_BASE_S "0x30040000" CACHE STRING "Data TCM block 2 Secure base address")

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set(DTCM3_BASE_S "0x30060000" CACHE STRING "Data TCM block 3 Secure base address")

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set(ISRAM0_BASE_S "0x31000000" CACHE STRING "Internal SRAM Area Secure base address")

Kshitij Sisodia

2021-11-24 10:39:52 +0000

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set(ISRAM1_BASE_S "0x31100000" CACHE STRING "Internal SRAM Area Secure base address")

Liam Barry

2022-02-02 17:03:06 +0000

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set(QSPI_SRAM_BASE_S "0x38000000" CACHE STRING "QSPI SRAM Non-Secure base address")

alexander

2021-03-26 21:42:19 +0000

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set(DDR4_BLK0_BASE_S "0x70000000" CACHE STRING "DDR4 block 0 Secure base address")

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set(DDR4_BLK1_BASE_S "0x90000000" CACHE STRING "DDR4 block 1 Secure base address")

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set(DDR4_BLK2_BASE_S "0xB0000000" CACHE STRING "DDR4 block 2 Secure base address")

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set(DDR4_BLK3_BASE_S "0xD0000000" CACHE STRING "DDR4 block 3 Secure base address")

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Kshitij Sisodia

aa5e1f6

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###################################################################################################

Kshitij Sisodia

f4962c8

2021-10-04 12:20:33 +0100

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# Application specific config #

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###################################################################################################

Kshitij Sisodia

2021-11-24 10:39:52 +0000

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set(APP_NOTE "AN552")

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set(DESIGN_NAME "Arm Corstone-300 - ${APP_NOTE}" CACHE STRING "Design name")

Kshitij Sisodia

f4962c8

2021-10-04 12:20:33 +0100

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Kshitij Sisodia

2021-11-24 10:39:52 +0000

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# The following parameter is based on the linker/scatter script for SSE-300.

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# Do not change this parameter in isolation.

Kshitij Sisodia

f4962c8

2021-10-04 12:20:33 +0100

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# SRAM size reserved for activation buffers

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math(EXPR ACTIVATION_BUF_SRAM_SZ "${ISRAM0_SIZE} + ${ISRAM1_SIZE}" OUTPUT_FORMAT HEXADECIMAL)

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###################################################################################################

Kshitij Sisodia

aa5e1f6

2021-09-24 14:42:08 +0100

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# Base addresses for dynamic loads (to be used for FVP form only) #

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###################################################################################################

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# This parameter is also mentioned in the linker/scatter script for SSE-300. Do not change these

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# parameters in isolation.

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set(DYNAMIC_MODEL_BASE "${DDR4_BLK1_BASE_S}" CACHE STRING

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"Region to be used for dynamic load of model into memory")

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set(DYNAMIC_MODEL_SIZE "0x02000000" CACHE STRING "Size of the space reserved for the model")

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math(EXPR DYNAMIC_IFM_BASE "${DYNAMIC_MODEL_BASE} + ${DYNAMIC_MODEL_SIZE}" OUTPUT_FORMAT HEXADECIMAL)

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set(DYNAMIC_IFM_SIZE "0x01000000" CACHE STRING "Size of the space reserved for the IFM")

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math(EXPR DYNAMIC_OFM_BASE "${DYNAMIC_IFM_BASE} + ${DYNAMIC_IFM_SIZE}" OUTPUT_FORMAT HEXADECIMAL)

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set(DYNAMIC_OFM_SIZE "0x01000000" CACHE STRING "Size of the space reserved for the OFM")

alexander

2021-03-26 21:42:19 +0000

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###################################################################################################

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# Base addresses for peripherals - non secure #

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###################################################################################################

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set(CMSDK_GPIO0_BASE "0x41100000" CACHE STRING "User GPIO 0 Base Address (4KB)")

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set(CMSDK_GPIO1_BASE "0x41101000" CACHE STRING "User GPIO 1 Base Address (4KB)")

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set(CMSDK_GPIO2_BASE "0x41102000" CACHE STRING "User GPIO 2 Base Address (4KB)")

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set(CMSDK_GPIO3_BASE "0x41103000" CACHE STRING "User GPIO 3 Base Address (4KB)")

Liam Barry

2022-02-02 17:03:06 +0000

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set(FMC_CMDSK_GPIO_BASE0 "0x41104000" CACHE STRING "FMC CMDSK GPIO 0 Base Address (4KB)")

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set(FMC_CMDSK_GPIO_BASE1 "0x41105000" CACHE STRING "FMC CMDSK GPIO 1 Base Address (4KB)")

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set(FMC_CMDSK_GPIO_BASE2 "0x41106000" CACHE STRING "FMC CMDSK GPIO 2 Base Address (4KB)")

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set(FMC_USER_AHB_BASE "0x41107000" CACHE STRING "FMC USER AHB Base Address (4KB)")

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set(DMA0_BASE "0x41200000" CACHE STRING "DMA0 ExternalManager0 (4KB)")

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set(DMA1_BASE "0x41201000" CACHE STRING "DMA1 ExternalManager1 (4KB)")

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set(DMA2_BASE "0x41202000" CACHE STRING "DMA2 ExternalManager2 (4KB)")

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set(DMA3_BASE "0x41203000" CACHE STRING "DMA3 ExternalManager3 (4KB)")

alexander

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set(SMSC9220_BASE "0x41400000" CACHE STRING "Ethernet SMSC9220 Base Address (1MB)")

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set(USB_BASE "0x41500000" CACHE STRING "USB Base Address (1MB)")

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set(USER_APB0_BASE "0x41700000" CACHE STRING "User APB0")

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set(USER_APB1_BASE "0x41701000" CACHE STRING "User APB1")

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set(USER_APB2_BASE "0x41702000" CACHE STRING "User APB2")

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set(USER_APB3_BASE "0x41703000" CACHE STRING "User APB3")

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set(QSPI_XIP_BASE "0x41800000" CACHE STRING "QSPI XIP config Base Address ")

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set(QSPI_WRITE_BASE "0x41801000" CACHE STRING "QSPI write config Base Address ")

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Cisco Cervellera

f085fa5

2021-08-02 09:32:07 +0100

[diff] [blame]

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if (ETHOS_U_NPU_ENABLED)

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set(ETHOS_U_NPU_BASE "0x48102000" CACHE STRING "Ethos-U NPU base address")

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set(ETHOS_U_NPU_TA0_BASE "0x48103000" CACHE STRING "Ethos-U NPU's timing adapter 0 base address")

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set(ETHOS_U_NPU_TA1_BASE "0x48103200" CACHE STRING "Ethos-U NPU's timing adapter 1 base address")

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endif (ETHOS_U_NPU_ENABLED)

alexander

2021-03-26 21:42:19 +0000

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set(MPS3_I2C0_BASE "0x49200000" CACHE STRING "Touch Screen I2C Base Address ")

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set(MPS3_I2C1_BASE "0x49201000" CACHE STRING "Audio Interface I2C Base Address ")

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set(MPS3_SSP2_BASE "0x49202000" CACHE STRING "ADC SPI PL022 Base Address")

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set(MPS3_SSP3_BASE "0x49203000" CACHE STRING "Shield 0 SPI PL022 Base Address")

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set(MPS3_SSP4_BASE "0x49204000" CACHE STRING "Shield 1 SPI PL022 Base Address")

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set(MPS3_I2C2_BASE "0x49205000" CACHE STRING "Shield 0 SBCon Base Address ")

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set(MPS3_I2C3_BASE "0x49206000" CACHE STRING "Shield 1 SBCon Base Address ")

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set(USER_APB_BASE "0x49207000" CACHE STRING "User APB")

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set(MPS3_I2C5_BASE "0x49208000" CACHE STRING "DDR EPROM I2C SBCon Base Address ")

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set(MPS3_SCC_BASE "0x49300000" CACHE STRING "SCC Base Address ")

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set(MPS3_AAIC_I2S_BASE "0x49301000" CACHE STRING "Audio Interface I2S Base Address ")

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set(MPS3_FPGAIO_BASE "0x49302000" CACHE STRING "FPGA IO Base Address ")

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set(CMSDK_UART0_BASE "0x49303000" CACHE STRING "UART 0 Base Address ")

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set(CMSDK_UART1_BASE "0x49304000" CACHE STRING "UART 1 Base Address ")

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set(CMSDK_UART2_BASE "0x49305000" CACHE STRING "UART 2 Base Address ")

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set(CMSDK_UART3_BASE "0x49306000" CACHE STRING "UART 3 Base Address Shield 0")

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set(CMSDK_UART4_BASE "0x49307000" CACHE STRING "UART 4 Base Address Shield 1")

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set(CMSDK_UART5_BASE "0x49308000" CACHE STRING "UART 5 Base Address ")

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set(CLCD_CONFIG_BASE "0x4930A000" CACHE STRING "CLCD CONFIG Base Address ")

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set(RTC_BASE "0x4930B000" CACHE STRING "RTC Base address ")

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###################################################################################################

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# Base addresses for peripherals - secure #

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###################################################################################################

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set(SEC_CMSDK_GPIO0_BASE "0x51100000" CACHE STRING "User GPIO 0 Base Address (4KB)")

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set(SEC_CMSDK_GPIO1_BASE "0x51101000" CACHE STRING "User GPIO 1 Base Address (4KB)")

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set(SEC_CMSDK_GPIO2_BASE "0x51102000" CACHE STRING "User GPIO 2 Base Address (4KB)")

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set(SEC_CMSDK_GPIO3_BASE "0x51103000" CACHE STRING "User GPIO 3 Base Address (4KB)")

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set(SEC_AHB_USER0_BASE "0x51104000" CACHE STRING "AHB USER 0 Base Address (4KB)")

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set(SEC_AHB_USER1_BASE "0x51105000" CACHE STRING "AHB USER 1 Base Address (4KB)")

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set(SEC_AHB_USER2_BASE "0x51106000" CACHE STRING "AHB USER 2 Base Address (4KB)")

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set(SEC_AHB_USER3_BASE "0x51107000" CACHE STRING "AHB USER 3 Base Address (4KB)")

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Liam Barry

2022-02-02 17:03:06 +0000

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set(SEC_DMA0_BASE "0x51200000" CACHE STRING "DMA0 ExternalManager0 (4KB)")

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set(SEC_DMA1_BASE "0x51201000" CACHE STRING "DMA1 ExternalManager1 (4KB)")

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set(SEC_DMA2_BASE "0x51202000" CACHE STRING "DMA2 ExternalManager2 (4KB)")

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set(SEC_DMA3_BASE "0x51203000" CACHE STRING "DMA3 ExternalManager3 (4KB)")

alexander

2021-03-26 21:42:19 +0000

[diff] [blame]

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set(SEC_SMSC9220_BASE "0x51400000" CACHE STRING "Ethernet SMSC9220 Base Address (1MB)")

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set(SEC_USB_BASE "0x51500000" CACHE STRING "USB Base Address (1MB)")

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set(SEC_USER_APB0_BASE "0x51700000" CACHE STRING "User APB0 Base Address")

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set(SEC_USER_APB1_BASE "0x51701000" CACHE STRING "User APB1 Base Address")

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set(SEC_USER_APB2_BASE "0x51702000" CACHE STRING "User APB2 Base Address")

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set(SEC_USER_APB3_BASE "0x51703000" CACHE STRING "User APB3 Base Address")

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set(SEC_QSPI_XIP_BASE "0x51800000" CACHE STRING "QSPI XIP config Base Address ")

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set(SEC_QSPI_WRITE_BASE "0x51801000" CACHE STRING "QSPI write config Base Address ")

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Cisco Cervellera

f085fa5

2021-08-02 09:32:07 +0100

[diff] [blame]

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if (ETHOS_U_NPU_ENABLED)

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set(SEC_ETHOS_U_NPU_BASE "0x58102000" CACHE STRING "Ethos-U NPU base address")

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set(SEC_ETHOS_U_NPU_TA0_BASE "0x58103000" CACHE STRING "Ethos-U NPU's timing adapter 0 base address")

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set(SEC_ETHOS_U_NPU_TA1_BASE "0x58103200" CACHE STRING "Ethos-U NPU's timing adapter 1 base address")

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endif (ETHOS_U_NPU_ENABLED)

alexander

2021-03-26 21:42:19 +0000

[diff] [blame]

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Liam Barry

2022-02-02 17:03:06 +0000

[diff] [blame]

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set(SEC_MPS3_I2C0_BASE "0x59200000" CACHE STRING "Touch Screen I2C Base Address ")

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set(SEC_MPS3_I2C1_BASE "0x59201000" CACHE STRING "Audio Interface I2C Base Address ")

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set(SEC_MPS3_SSP2_BASE "0x59202000" CACHE STRING "ADC SPI PL022 Base Address")

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set(SEC_MPS3_SSP3_BASE "0x59203000" CACHE STRING "Shield 0 SPI PL022 Base Address")

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set(SEC_MPS3_SSP4_BASE "0x59204000" CACHE STRING "Shield 1 SPI PL022 Base Address")

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set(SEC_MPS3_I2C2_BASE "0x59205000" CACHE STRING "Shield 0 SBCon Base Address ")

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set(SEC_MPS3_I2C3_BASE "0x59206000" CACHE STRING "Shield 1 SBCon Base Address ")

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set(SEC_USER_APB_BASE "0x59207000" CACHE STRING "User APB Base Address")

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set(SEC_MPS3_I2C5_BASE "0x59208000" CACHE STRING "DDR EPROM I2C SBCon Base Address ")

alexander

2021-03-26 21:42:19 +0000

[diff] [blame]

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Liam Barry

2022-02-02 17:03:06 +0000

[diff] [blame]

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set(SEC_MPS3_SCC_BASE "0x59300000" CACHE STRING "SCC Base Address ")

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set(SEC_MPS3_AAIC_I2S_BASE "0x59301000" CACHE STRING "Audio Interface I2S Base Address ")

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set(SEC_MPS3_FPGAIO_BASE "0x59302000" CACHE STRING "FPGA IO Base Address ")

alexander

2021-03-26 21:42:19 +0000

[diff] [blame]

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Liam Barry

2022-02-02 17:03:06 +0000

[diff] [blame]

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set(SEC_CMSDK_UART0_BASE "0x59303000" CACHE STRING "UART 0 Base Address ")

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set(SEC_CMSDK_UART1_BASE "0x59304000" CACHE STRING "UART 1 Base Address ")

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set(SEC_CMSDK_UART2_BASE "0x59305000" CACHE STRING "UART 2 Base Address ")

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set(SEC_CMSDK_UART3_BASE "0x59306000" CACHE STRING "UART 3 Base Address Shield 0")

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set(SEC_CMSDK_UART4_BASE "0x59307000" CACHE STRING "UART 4 Base Address Shield 1")

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set(SEC_CMSDK_UART5_BASE "0x59308000" CACHE STRING "UART 5 Base Address ")

alexander

2021-03-26 21:42:19 +0000

[diff] [blame]

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Liam Barry

2022-02-02 17:03:06 +0000

[diff] [blame]

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set(SEC_CLCD_CONFIG_BASE "0x5930A000" CACHE STRING "CLCD CONFIG Base Address ")

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set(SEC_RTC_BASE "0x5930B000" CACHE STRING "RTC Base address ")

alexander

2021-03-26 21:42:19 +0000

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###################################################################################################

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# MPCs #

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###################################################################################################

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set(MPC_ISRAM0_BASE_S "0x50083000" CACHE STRING "ISRAM0 Memory Protection Controller Secure base address")

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set(MPC_ISRAM1_BASE_S "0x50084000" CACHE STRING "ISRAM1 Memory Protection Controller Secure base address")

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set(MPC_BRAM_BASE_S "0x57000000" CACHE STRING "SRAM Memory Protection Controller Secure base address")

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set(MPC_QSPI_BASE_S "0x57001000" CACHE STRING "QSPI Memory Protection Controller Secure base address")

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set(MPC_DDR4_BASE_S "0x57002000" CACHE STRING "DDR4 Memory Protection Controller Secure base address")

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###################################################################################################

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# IRQ numbers #

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###################################################################################################

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set(NONSEC_WATCHDOG_RESET_IRQn " 0" CACHE STRING " Non-Secure Watchdog Reset Interrupt")

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set(NONSEC_WATCHDOG_IRQn " 1" CACHE STRING " Non-Secure Watchdog Interrupt ")

Liam Barry

2022-02-02 17:03:06 +0000

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set(S32K_TIMER_IRQn " 2" CACHE STRING " S32K SLOWCLK Timer Interrupt ")

alexander

2021-03-26 21:42:19 +0000

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set(TIMER0_IRQn " 3" CACHE STRING " TIMER 0 Interrupt ")

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set(TIMER1_IRQn " 4" CACHE STRING " TIMER 1 Interrupt ")

Liam Barry

2022-02-02 17:03:06 +0000

[diff] [blame]

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set(TIMER2_IRQn " 5" CACHE STRING " TIMER 2 Interrupt ")

alexander

2021-03-26 21:42:19 +0000

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set(MPC_IRQn " 9" CACHE STRING " MPC Combined (Secure) Interrupt ")

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set(PPC_IRQn "10" CACHE STRING " PPC Combined (Secure) Interrupt ")

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set(MSC_IRQn "11" CACHE STRING " MSC Combined (Secure) Interrput ")

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set(BRIDGE_ERROR_IRQn "12" CACHE STRING " Bridge Error Combined (Secure) Interrupt ")

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set(MGMT_PPU_IRQn "14" CACHE STRING " MGMT_PPU" )

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set(SYS_PPU_IRQn "15" CACHE STRING " SYS_PPU" )

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set(CPU0_PPU_IRQn "16" CACHE STRING " CPU0_PPU" )

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set(DEBUG_PPU_IRQn "26" CACHE STRING " DEBUG_PPU" )

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set(TIMER3_AON_IRQn "27" CACHE STRING " TIMER3_AON" )

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set(CPU0CTIIQ0_IRQn "28" CACHE STRING " CPU0CTIIQ0" )

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set(CPU0CTIIQ01_IRQn "29" CACHE STRING " CPU0CTIIQ01" )

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Liam Barry

2022-02-02 17:03:06 +0000

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set(SYS_TSTAMP_COUNTER_IRQn "32" CACHE STRING " System timestamp counter interrupt ")

alexander

2021-03-26 21:42:19 +0000

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set(UARTRX0_IRQn "33" CACHE STRING " UART 0 RX Interrupt ")

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set(UARTTX0_IRQn "34" CACHE STRING " UART 0 TX Interrupt ")

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set(UARTRX1_IRQn "35" CACHE STRING " UART 1 RX Interrupt ")

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set(UARTTX1_IRQn "36" CACHE STRING " UART 1 TX Interrupt ")

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set(UARTRX2_IRQn "37" CACHE STRING " UART 2 RX Interrupt ")

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set(UARTTX2_IRQn "38" CACHE STRING " UART 2 TX Interrupt ")

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set(UARTRX3_IRQn "39" CACHE STRING " UART 3 RX Interrupt ")

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set(UARTTX3_IRQn "40" CACHE STRING " UART 3 TX Interrupt ")

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set(UARTRX4_IRQn "41" CACHE STRING " UART 4 RX Interrupt ")

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set(UARTTX4_IRQn "42" CACHE STRING " UART 4 TX Interrupt ")

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set(UART0_IRQn "43" CACHE STRING " UART 0 combined Interrupt ")

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set(UART1_IRQn "44" CACHE STRING " UART 1 combined Interrupt ")

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set(UART2_IRQn "45" CACHE STRING " UART 2 combined Interrupt ")

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set(UART3_IRQn "46" CACHE STRING " UART 3 combined Interrupt ")

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set(UART4_IRQn "47" CACHE STRING " UART 4 combined Interrupt ")

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set(UARTOVF_IRQn "48" CACHE STRING " UART 0,1,2,3,4 Overflow Interrupt ")

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set(ETHERNET_IRQn "49" CACHE STRING " Ethernet Interrupt ")

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set(I2S_IRQn "50" CACHE STRING " Audio I2S Interrupt ")

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set(TSC_IRQn "51" CACHE STRING " Touch Screen Interrupt ")

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set(USB_IRQn "52" CACHE STRING " USB Interrupt ")

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set(SPI2_IRQn "53" CACHE STRING " ADC (SPI) Interrupt ")

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set(SPI3_IRQn "54" CACHE STRING " SPI 3 Interrupt (Shield 0) ")

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set(SPI4_IRQn "55" CACHE STRING " SPI 4 Interrupt (Sheild 1) ")

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Cisco Cervellera

f085fa5

2021-08-02 09:32:07 +0100

[diff] [blame]

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if (ETHOS_U_NPU_ENABLED)

Kshitij Sisodia

2021-11-24 10:39:52 +0000

[diff] [blame]

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set(EthosU_IRQn "56" CACHE STRING " Ethos-U55 Interrupt ")

alexander

2021-03-26 21:42:19 +0000

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endif ()

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set(GPIO0_IRQn "69" CACHE STRING " GPIO 0 Combined Interrupt ")

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set(GPIO1_IRQn "70" CACHE STRING " GPIO 1 Combined Interrupt ")

263

set(GPIO2_IRQn "71" CACHE STRING " GPIO 2 Combined Interrupt ")

264

set(GPIO3_IRQn "72" CACHE STRING " GPIO 3 Combined Interrupt ")

alexander