alexander | 3c79893 | 2021-03-26 21:42:19 +0000 | [diff] [blame] | 1 | /* |
Kshitij Sisodia | a1256e3 | 2022-02-23 14:40:45 +0000 | [diff] [blame] | 2 | * Copyright (c) 2022 Arm Limited. All rights reserved. |
alexander | 3c79893 | 2021-03-26 21:42:19 +0000 | [diff] [blame] | 3 | * SPDX-License-Identifier: Apache-2.0 |
| 4 | * |
| 5 | * Licensed under the Apache License, Version 2.0 (the "License"); |
| 6 | * you may not use this file except in compliance with the License. |
| 7 | * You may obtain a copy of the License at |
| 8 | * |
| 9 | * http://www.apache.org/licenses/LICENSE-2.0 |
| 10 | * |
| 11 | * Unless required by applicable law or agreed to in writing, software |
| 12 | * distributed under the License is distributed on an "AS IS" BASIS, |
| 13 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 14 | * See the License for the specific language governing permissions and |
| 15 | * limitations under the License. |
| 16 | */ |
alexander | 3c79893 | 2021-03-26 21:42:19 +0000 | [diff] [blame] | 17 | |
Kshitij Sisodia | a1256e3 | 2022-02-23 14:40:45 +0000 | [diff] [blame] | 18 | #include "platform_drivers.h" |
alexander | 3c79893 | 2021-03-26 21:42:19 +0000 | [diff] [blame] | 19 | |
Kshitij Sisodia | a1256e3 | 2022-02-23 14:40:45 +0000 | [diff] [blame] | 20 | #include "log_macros.h" /* Logging functions */ |
| 21 | #include "device_mps3.h" /* FPGA level definitions and functions. */ |
Kshitij Sisodia | acc6b85 | 2022-03-01 10:23:11 +0000 | [diff] [blame] | 22 | #include "uart_stdout.h" /* stdout over UART. */ |
Kshitij Sisodia | a1256e3 | 2022-02-23 14:40:45 +0000 | [diff] [blame] | 23 | |
Kshitij Sisodia | d5679cc | 2022-03-03 16:30:07 +0000 | [diff] [blame^] | 24 | #include "smm_mps3.h" /* Memory map for MPS3. */ |
| 25 | |
Kshitij Sisodia | a1256e3 | 2022-02-23 14:40:45 +0000 | [diff] [blame] | 26 | #include <string.h> /* For strncpy */ |
| 27 | |
Isabella Gottardi | ee4920b | 2022-02-25 14:29:32 +0000 | [diff] [blame] | 28 | #if defined(ARM_NPU) |
| 29 | #include "ethosu_npu_init.h" |
| 30 | |
Kshitij Sisodia | d5679cc | 2022-03-03 16:30:07 +0000 | [diff] [blame^] | 31 | #if defined(ETHOS_U_NPU_TIMING_ADAPTER_ENABLED) |
Isabella Gottardi | ee4920b | 2022-02-25 14:29:32 +0000 | [diff] [blame] | 32 | #include "ethosu_ta_init.h" |
Kshitij Sisodia | d5679cc | 2022-03-03 16:30:07 +0000 | [diff] [blame^] | 33 | #endif /* ETHOS_U_NPU_TIMING_ADAPTER_ENABLED */ |
Isabella Gottardi | ee4920b | 2022-02-25 14:29:32 +0000 | [diff] [blame] | 34 | |
| 35 | #endif /* ARM_NPU */ |
| 36 | |
Kshitij Sisodia | a1256e3 | 2022-02-23 14:40:45 +0000 | [diff] [blame] | 37 | /** |
| 38 | * @brief Checks if the platform is valid by checking |
| 39 | * the CPU ID for the FPGA implementation against |
| 40 | * the register from the CPU core. |
| 41 | * @return 0 if successful, 1 otherwise |
| 42 | */ |
| 43 | static int verify_platform(void); |
| 44 | |
| 45 | int platform_init(void) |
| 46 | { |
| 47 | int err = 0; |
| 48 | |
| 49 | SystemCoreClockUpdate(); /* From start up code */ |
| 50 | |
| 51 | /* UART init - will enable valid use of printf (stdout |
| 52 | * re-directed at this UART (UART0) */ |
| 53 | UartStdOutInit(); |
| 54 | |
| 55 | if (0 != (err = verify_platform())) { |
| 56 | return err; |
| 57 | } |
| 58 | |
Isabella Gottardi | ee4920b | 2022-02-25 14:29:32 +0000 | [diff] [blame] | 59 | #if defined(ARM_NPU) |
| 60 | |
Kshitij Sisodia | d5679cc | 2022-03-03 16:30:07 +0000 | [diff] [blame^] | 61 | #if defined(ETHOS_U_NPU_TIMING_ADAPTER_ENABLED) |
Isabella Gottardi | ee4920b | 2022-02-25 14:29:32 +0000 | [diff] [blame] | 62 | /* If the platform has timing adapter blocks along with Ethos-U core |
| 63 | * block, initialise them here. */ |
| 64 | if (0 != (err = arm_ethosu_timing_adapter_init())) |
| 65 | { |
| 66 | return err; |
| 67 | } |
Kshitij Sisodia | d5679cc | 2022-03-03 16:30:07 +0000 | [diff] [blame^] | 68 | #endif /* ETHOS_U_NPU_TIMING_ADAPTER_ENABLED */ |
Isabella Gottardi | ee4920b | 2022-02-25 14:29:32 +0000 | [diff] [blame] | 69 | |
| 70 | int state; |
| 71 | |
| 72 | /* If Arm Ethos-U NPU is to be used, we initialise it here */ |
| 73 | if (0 != (state = arm_ethosu_npu_init())) |
| 74 | { |
| 75 | return state; |
| 76 | } |
| 77 | |
| 78 | #endif /* ARM_NPU */ |
| 79 | |
| 80 | /* Print target design info */ |
| 81 | info("Target system design: %s\n", DESIGN_NAME); |
| 82 | |
Kshitij Sisodia | a1256e3 | 2022-02-23 14:40:45 +0000 | [diff] [blame] | 83 | return 0; |
| 84 | } |
| 85 | |
| 86 | void platform_release(void) |
| 87 | { |
| 88 | __disable_irq(); |
| 89 | } |
| 90 | |
| 91 | void platform_name(char* name, size_t size) |
| 92 | { |
| 93 | strncpy(name, DESIGN_NAME, size); |
| 94 | } |
| 95 | |
Kshitij Sisodia | f9c19ea | 2021-05-07 16:08:14 +0100 | [diff] [blame] | 96 | #define CREATE_MASK(msb, lsb) (int)(((1U << ((msb) - (lsb) + 1)) - 1) << (lsb)) |
| 97 | #define MASK_BITS(arg, msb, lsb) (int)((arg) & CREATE_MASK(msb, lsb)) |
| 98 | #define EXTRACT_BITS(arg, msb, lsb) (int)(MASK_BITS(arg, msb, lsb) >> (lsb)) |
alexander | 3c79893 | 2021-03-26 21:42:19 +0000 | [diff] [blame] | 99 | |
Kshitij Sisodia | a1256e3 | 2022-02-23 14:40:45 +0000 | [diff] [blame] | 100 | static int verify_platform(void) |
alexander | 3c79893 | 2021-03-26 21:42:19 +0000 | [diff] [blame] | 101 | { |
alexander | 3c79893 | 2021-03-26 21:42:19 +0000 | [diff] [blame] | 102 | uint32_t id = 0; |
| 103 | uint32_t fpgaid = 0; |
| 104 | uint32_t apnote = 0; |
| 105 | uint32_t rev = 0; |
| 106 | uint32_t aid = 0; |
| 107 | uint32_t fpga_clk = 0; |
Kshitij Sisodia | f9c19ea | 2021-05-07 16:08:14 +0100 | [diff] [blame] | 108 | const uint32_t ascii_A = (uint32_t)('A'); |
alexander | 3c79893 | 2021-03-26 21:42:19 +0000 | [diff] [blame] | 109 | |
| 110 | /* Initialise the LEDs as the switches are */ |
| 111 | MPS3_FPGAIO->LED = MPS3_FPGAIO->SWITCHES & 0xFF; |
alexander | 3c79893 | 2021-03-26 21:42:19 +0000 | [diff] [blame] | 112 | |
Kshitij Sisodia | a1256e3 | 2022-02-23 14:40:45 +0000 | [diff] [blame] | 113 | info("Processor internal clock: %" PRIu32 "Hz\n", GetMPS3CoreClock()); |
alexander | 3c79893 | 2021-03-26 21:42:19 +0000 | [diff] [blame] | 114 | |
alexander | 3c79893 | 2021-03-26 21:42:19 +0000 | [diff] [blame] | 115 | /* Get revision information from various registers */ |
| 116 | rev = MPS3_SCC->CFG_REG4; |
| 117 | fpgaid = MPS3_SCC->SCC_ID; |
| 118 | aid = MPS3_SCC->SCC_AID; |
| 119 | apnote = EXTRACT_BITS(fpgaid, 15, 4); |
| 120 | fpga_clk = GetMPS3CoreClock(); |
| 121 | |
Kshitij Sisodia | f9c19ea | 2021-05-07 16:08:14 +0100 | [diff] [blame] | 122 | info("V2M-MPS3 revision %c\n\n", (char)(rev + ascii_A)); |
| 123 | info("Application Note AN%" PRIx32 ", Revision %c\n", apnote, |
| 124 | (char)(EXTRACT_BITS(aid, 23, 20) + ascii_A)); |
alexander | 3c79893 | 2021-03-26 21:42:19 +0000 | [diff] [blame] | 125 | info("MPS3 build %d\n", EXTRACT_BITS(aid, 31, 24)); |
Kshitij Sisodia | f9c19ea | 2021-05-07 16:08:14 +0100 | [diff] [blame] | 126 | info("MPS3 core clock has been set to: %" PRIu32 "Hz\n", fpga_clk); |
alexander | 3c79893 | 2021-03-26 21:42:19 +0000 | [diff] [blame] | 127 | |
| 128 | /* Display CPU ID */ |
| 129 | id = SCB->CPUID; |
Kshitij Sisodia | f9c19ea | 2021-05-07 16:08:14 +0100 | [diff] [blame] | 130 | info("CPU ID: 0x%08" PRIx32 "\n", id); |
alexander | 3c79893 | 2021-03-26 21:42:19 +0000 | [diff] [blame] | 131 | |
| 132 | if(EXTRACT_BITS(id, 15, 8) == 0xD2) { |
| 133 | if (EXTRACT_BITS(id, 7, 4) == 2) { |
| 134 | info ("CPU: Cortex-M55 r%dp%d\n\n", |
| 135 | EXTRACT_BITS(id, 23, 20),EXTRACT_BITS(id, 3, 0)); |
| 136 | #if defined (CPU_CORTEX_M55) |
| 137 | /* CPU ID should be "0x_41_0f_d2_20" for Cortex-M55 */ |
| 138 | return 0; |
| 139 | #endif /* CPU_CORTEX_M55 */ |
| 140 | } else if (EXTRACT_BITS(id, 7, 4) == 1) { |
| 141 | info ("CPU: Cortex-M33 r%dp%d\n\n", |
| 142 | EXTRACT_BITS(id, 23, 20),EXTRACT_BITS(id, 3, 0)); |
| 143 | #if defined (CPU_CORTEX_M33) |
| 144 | return 0; |
| 145 | #endif /* CPU_CORTEX_M33 */ |
| 146 | } else if (EXTRACT_BITS(id, 7, 4) == 0) { |
| 147 | info ("CPU: Cortex-M23 r%dp%d\n\n", |
| 148 | EXTRACT_BITS(id, 23, 20),EXTRACT_BITS(id, 3, 0)); |
| 149 | } else { |
| 150 | info ("CPU: Cortex-M processor family"); |
| 151 | } |
| 152 | } else if (EXTRACT_BITS(id, 15, 8) == 0xC6) { |
| 153 | info ("CPU: Cortex-M%d+ r%dp%d\n\n", |
| 154 | EXTRACT_BITS(id, 7, 4), EXTRACT_BITS(id, 23, 20), |
| 155 | EXTRACT_BITS(id, 3, 0)); |
| 156 | } else { |
| 157 | info ("CPU: Cortex-M%d r%dp%d\n\n", |
| 158 | EXTRACT_BITS(id, 7, 4), EXTRACT_BITS(id, 23, 20), |
| 159 | EXTRACT_BITS(id, 3, 0)); |
| 160 | } |
alexander | 3c79893 | 2021-03-26 21:42:19 +0000 | [diff] [blame] | 161 | |
| 162 | /* If the CPU is anything other than M33 or M55, we return 1 */ |
| 163 | printf_err("CPU mismatch!\n"); |
| 164 | return 1; |
| 165 | } |